| Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| Arthur Heymans | 1f2ae91 | 2018-06-12 23:48:30 +0200 | [diff] [blame] | 2 | |
| 3 | #ifndef SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H |
| 4 | #define SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H |
| 5 | |
| 6 | #ifndef __ACPI__ |
| Arthur Heymans | 1f2ae91 | 2018-06-12 23:48:30 +0200 | [diff] [blame] | 7 | |
| Peter Lemenkov | 7b42811 | 2018-10-23 11:12:46 +0200 | [diff] [blame] | 8 | #define DEFAULT_RCBA ((u8 *)0xfed1c000) |
| 9 | |
| 10 | /* Root Complex Register Block */ |
| 11 | #define RCBA 0xf0 |
| 12 | #define RCBA_ENABLE 0x01 |
| Arthur Heymans | 1f2ae91 | 2018-06-12 23:48:30 +0200 | [diff] [blame] | 13 | |
| Angel Pons | cf445ea | 2021-01-28 13:40:02 +0100 | [diff] [blame^] | 14 | #define RCBA8(x) (*((volatile u8 *)(DEFAULT_RCBA + (x)))) |
| 15 | #define RCBA16(x) (*((volatile u16 *)(DEFAULT_RCBA + (x)))) |
| 16 | #define RCBA32(x) (*((volatile u32 *)(DEFAULT_RCBA + (x)))) |
| 17 | #define RCBA64(x) (*((volatile u64 *)(DEFAULT_RCBA + (x)))) |
| Arthur Heymans | 1f2ae91 | 2018-06-12 23:48:30 +0200 | [diff] [blame] | 18 | |
| 19 | #define RCBA_AND_OR(bits, x, and, or) \ |
| 20 | (RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or))) |
| 21 | #define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or) |
| 22 | #define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or) |
| 23 | #define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or) |
| 24 | #define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or) |
| 25 | |
| Peter Lemenkov | 7b42811 | 2018-10-23 11:12:46 +0200 | [diff] [blame] | 26 | #else |
| 27 | |
| 28 | #define DEFAULT_RCBA 0xfed1c000 |
| Arthur Heymans | 1f2ae91 | 2018-06-12 23:48:30 +0200 | [diff] [blame] | 29 | |
| 30 | #endif /* __ACPI__ */ |
| Peter Lemenkov | 7b42811 | 2018-10-23 11:12:46 +0200 | [diff] [blame] | 31 | |
| Arthur Heymans | 1f2ae91 | 2018-06-12 23:48:30 +0200 | [diff] [blame] | 32 | #endif /* SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H */ |