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Angel Pons182dbde2020-04-02 23:49:05 +02001/* SPDX-License-Identifier: GPL-2.0-only */
2/* This file is part of the coreboot project. */
Arthur Heymans1f2ae912018-06-12 23:48:30 +02003
4#ifndef SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H
5#define SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H
6
7#ifndef __ACPI__
Arthur Heymans1f2ae912018-06-12 23:48:30 +02008
Peter Lemenkov7b428112018-10-23 11:12:46 +02009#define DEFAULT_RCBA ((u8 *)0xfed1c000)
10
11/* Root Complex Register Block */
12#define RCBA 0xf0
13#define RCBA_ENABLE 0x01
Arthur Heymans1f2ae912018-06-12 23:48:30 +020014
15#define RCBA8(x) (*((volatile u8 *)(DEFAULT_RCBA + x)))
16#define RCBA16(x) (*((volatile u16 *)(DEFAULT_RCBA + x)))
17#define RCBA32(x) (*((volatile u32 *)(DEFAULT_RCBA + x)))
Peter Lemenkov522a1b52019-01-10 12:19:01 +010018#define RCBA64(x) (*((volatile u64 *)(DEFAULT_RCBA + x)))
Arthur Heymans1f2ae912018-06-12 23:48:30 +020019
20#define RCBA_AND_OR(bits, x, and, or) \
21 (RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or)))
22#define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or)
23#define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or)
24#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or)
25#define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or)
26
Peter Lemenkov7b428112018-10-23 11:12:46 +020027#else
28
29#define DEFAULT_RCBA 0xfed1c000
Arthur Heymans1f2ae912018-06-12 23:48:30 +020030
31#endif /* __ACPI__ */
Peter Lemenkov7b428112018-10-23 11:12:46 +020032
Arthur Heymans1f2ae912018-06-12 23:48:30 +020033#endif /* SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H */