| Arthur Heymans | 1f2ae91 | 2018-06-12 23:48:30 +0200 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
| 17 | #ifndef SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H |
| 18 | #define SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H |
| 19 | |
| 20 | #ifndef __ACPI__ |
| 21 | #define DEFAULT_RCBA ((u8 *)0xfed1c000) |
| 22 | #else |
| 23 | #define DEFAULT_RCBA 0xfed1c000 |
| 24 | #endif |
| 25 | |
| 26 | #ifndef __ACPI__ |
| 27 | |
| 28 | #define RCBA8(x) (*((volatile u8 *)(DEFAULT_RCBA + x))) |
| 29 | #define RCBA16(x) (*((volatile u16 *)(DEFAULT_RCBA + x))) |
| 30 | #define RCBA32(x) (*((volatile u32 *)(DEFAULT_RCBA + x))) |
| 31 | |
| 32 | #define RCBA_AND_OR(bits, x, and, or) \ |
| 33 | (RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or))) |
| 34 | #define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or) |
| 35 | #define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or) |
| 36 | #define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or) |
| 37 | #define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or) |
| 38 | |
| 39 | |
| 40 | #endif /* __ACPI__ */ |
| 41 | #endif /* SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H */ |