| Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 1 | ## |
| 2 | ## SPDX-License-Identifier: GPL-2.0-only |
| 3 | ## This file is part of the coreboot project. |
| 4 | ## |
| 5 | |
| 6 | if SOC_INTEL_COOPERLAKE_SP |
| 7 | |
| 8 | config MAINBOARD_USES_FSP2_0 |
| 9 | bool |
| 10 | default y |
| 11 | |
| 12 | config USE_FSP2_0_DRIVER |
| 13 | def_bool y |
| 14 | depends on MAINBOARD_USES_FSP2_0 |
| 15 | select PLATFORM_USES_FSP2_0 |
| 16 | select UDK_2015_BINDING |
| 17 | select POSTCAR_CONSOLE |
| 18 | select POSTCAR_STAGE |
| Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 19 | |
| 20 | config FSP_HEADER_PATH |
| 21 | string "Location of FSP headers" |
| 22 | depends on MAINBOARD_USES_FSP2_0 |
| 23 | default "src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp" |
| 24 | |
| 25 | config MAX_SOCKET |
| 26 | int |
| 27 | default 2 |
| 28 | |
| 29 | config MAX_CPUS |
| 30 | int |
| Andrey Petrov | e37d1f7 | 2020-04-20 21:11:51 -0700 | [diff] [blame] | 31 | default 255 |
| Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 32 | |
| 33 | config PCR_BASE_ADDRESS |
| 34 | hex |
| 35 | default 0xfd000000 |
| 36 | help |
| 37 | This option allows you to select MMIO Base Address of sideband bus. |
| 38 | |
| 39 | # currently FSP hardcodes [0fe800000;fe930000] for its heap |
| 40 | config DCACHE_RAM_BASE |
| 41 | hex |
| Andrey Petrov | dddb9a8 | 2020-04-20 18:07:08 -0700 | [diff] [blame] | 42 | default 0xfe9a0000 |
| Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 43 | |
| 44 | config DCACHE_RAM_SIZE |
| 45 | hex |
| Andrey Petrov | dddb9a8 | 2020-04-20 18:07:08 -0700 | [diff] [blame] | 46 | default 0x60000 |
| Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 47 | |
| 48 | config DCACHE_BSP_STACK_SIZE |
| 49 | hex |
| 50 | default 0x10000 |
| 51 | |
| 52 | config CPU_MICROCODE_CBFS_LOC |
| 53 | hex |
| 54 | default 0xfff0fdc0 |
| 55 | |
| 56 | config CPU_MICROCODE_CBFS_LEN |
| 57 | hex |
| 58 | default 0x7C00 |
| 59 | |
| 60 | config C_ENV_BOOTBLOCK_SIZE |
| 61 | hex |
| 62 | default 0xC000 |
| 63 | |
| 64 | config HEAP_SIZE |
| 65 | hex |
| 66 | default 0x80000 |
| 67 | |
| 68 | config FSP_TEMP_RAM_SIZE |
| 69 | hex |
| 70 | depends on FSP_USES_CB_STACK |
| 71 | default 0x70000 |
| 72 | help |
| 73 | The amount of anticipated heap usage in CAR by FSP. |
| 74 | Refer to Platform FSP integration guide document to know |
| 75 | the exact FSP requirement for Heap setup. |
| 76 | |
| 77 | endif |