Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <arch/io.h> |
Duncan Laurie | 04c5bae | 2012-08-13 09:37:42 -0700 | [diff] [blame] | 18 | #include <console/post_codes.h> |
Tristan Corrick | 63626b1 | 2018-11-30 22:53:50 +1300 | [diff] [blame] | 19 | #include <device/pci_ops.h> |
Patrick Rudolph | 2dc6389 | 2018-06-28 14:13:06 +0200 | [diff] [blame] | 20 | #include <southbridge/intel/common/pmbase.h> |
Tristan Corrick | 63626b1 | 2018-11-30 22:53:50 +1300 | [diff] [blame] | 21 | #include <southbridge/intel/common/pmutil.h> |
| 22 | #include <southbridge/intel/common/rcba.h> |
Zheng Bao | 600784e | 2013-02-07 17:30:23 +0800 | [diff] [blame] | 23 | #include <spi-generic.h> |
Tristan Corrick | 63626b1 | 2018-11-30 22:53:50 +1300 | [diff] [blame] | 24 | |
| 25 | #include "finalize.h" |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 26 | |
| 27 | void intel_pch_finalize_smm(void) |
| 28 | { |
Tristan Corrick | 63626b1 | 2018-11-30 22:53:50 +1300 | [diff] [blame] | 29 | const pci_devfn_t lpc_dev = PCI_DEV(0, 0x1f, 0); |
| 30 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame^] | 31 | if (CONFIG(LOCK_SPI_FLASH_RO) || |
| 32 | CONFIG(LOCK_SPI_FLASH_NO_ACCESS)) { |
Vladimir Serbinenko | d3b194e | 2015-05-12 12:39:53 +0200 | [diff] [blame] | 33 | int i; |
Tristan Corrick | 63626b1 | 2018-11-30 22:53:50 +1300 | [diff] [blame] | 34 | u32 lockmask = 1UL << 31; |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame^] | 35 | if (CONFIG(LOCK_SPI_FLASH_NO_ACCESS)) |
Tristan Corrick | 63626b1 | 2018-11-30 22:53:50 +1300 | [diff] [blame] | 36 | lockmask |= 1 << 15; |
Vladimir Serbinenko | d3b194e | 2015-05-12 12:39:53 +0200 | [diff] [blame] | 37 | for (i = 0; i < 20; i += 4) |
| 38 | RCBA32(0x3874 + i) = RCBA32(0x3854 + i) | lockmask; |
| 39 | } |
Nico Huber | d1fb564 | 2013-07-01 16:02:36 +0200 | [diff] [blame] | 40 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 41 | /* Lock SPIBAR */ |
| 42 | RCBA32_OR(0x3804, (1 << 15)); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 43 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame^] | 44 | if (CONFIG(SPI_FLASH_SMM)) |
Tristan Corrick | 63626b1 | 2018-11-30 22:53:50 +1300 | [diff] [blame] | 45 | /* Re-init SPI driver to handle locked BAR */ |
| 46 | spi_init(); |
Duncan Laurie | 312ee0c | 2012-09-09 20:12:32 -0700 | [diff] [blame] | 47 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 48 | /* TCLOCKDN: TC Lockdown */ |
Tristan Corrick | 63626b1 | 2018-11-30 22:53:50 +1300 | [diff] [blame] | 49 | RCBA32_OR(0x0050, (1UL << 31)); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 50 | |
| 51 | /* BIOS Interface Lockdown */ |
| 52 | RCBA32_OR(0x3410, (1 << 0)); |
| 53 | |
| 54 | /* Function Disable SUS Well Lockdown */ |
| 55 | RCBA_AND_OR(8, 0x3420, ~0U, (1 << 7)); |
| 56 | |
Tristan Corrick | 63626b1 | 2018-11-30 22:53:50 +1300 | [diff] [blame] | 57 | pci_or_config16(lpc_dev, D31F0_GEN_PMCON_1, SMI_LOCK); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 58 | |
Tristan Corrick | 63626b1 | 2018-11-30 22:53:50 +1300 | [diff] [blame] | 59 | pci_or_config8(lpc_dev, D31F0_GEN_PMCON_LOCK, |
| 60 | ACPI_BASE_LOCK | SLP_STR_POL_LOCK); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 61 | |
Tristan Corrick | 63626b1 | 2018-11-30 22:53:50 +1300 | [diff] [blame] | 62 | pci_update_config32(lpc_dev, D31F0_ETR3, ~ETR3_CF9GR, ETR3_CF9LOCK); |
| 63 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame^] | 64 | if (CONFIG(SOUTHBRIDGE_INTEL_LYNXPOINT)) |
Tristan Corrick | 63626b1 | 2018-11-30 22:53:50 +1300 | [diff] [blame] | 65 | /* PMSYNC */ |
| 66 | RCBA32_OR(0x33c4, (1UL << 31)); |
Patrick Rudolph | 7565cf1 | 2017-05-03 18:38:21 +0200 | [diff] [blame] | 67 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 68 | /* R/WO registers */ |
| 69 | RCBA32(0x21a4) = RCBA32(0x21a4); |
Kyösti Mälkki | fd98c65 | 2013-07-26 08:50:53 +0300 | [diff] [blame] | 70 | pci_write_config32(PCI_DEV(0, 27, 0), 0x74, |
| 71 | pci_read_config32(PCI_DEV(0, 27, 0), 0x74)); |
Duncan Laurie | 04c5bae | 2012-08-13 09:37:42 -0700 | [diff] [blame] | 72 | |
Patrick Rudolph | 2dc6389 | 2018-06-28 14:13:06 +0200 | [diff] [blame] | 73 | write_pmbase16(TCO1_CNT, read_pmbase16(TCO1_CNT) | TCO_LOCK); |
Dennis Wassenberg | 0c04720 | 2015-09-10 12:03:45 +0200 | [diff] [blame] | 74 | |
Tristan Corrick | 63626b1 | 2018-11-30 22:53:50 +1300 | [diff] [blame] | 75 | outb(POST_OS_BOOT, CONFIG_POST_IO_PORT); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 76 | } |