sb/intel/bd82x6x: Add TCO_Lock in finalize step
CHIPSEC found that the TCO_Lock was not set.
This is used to prevent changing the TCO_EN bit.
Change-Id: I42364dbef2511e656662566cf94591e76c6847ed
Signed-off-by: Dennis Wassenberg <dennis.wassenberg@secunet.com>
Reviewed-on: https://review.coreboot.org/17351
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c
index 90932e1..c9296fd 100644
--- a/src/southbridge/intel/bd82x6x/finalize.c
+++ b/src/southbridge/intel/bd82x6x/finalize.c
@@ -16,11 +16,15 @@
#include <arch/io.h>
#include <console/post_codes.h>
+#include <cpu/x86/smm.h>
#include "pch.h"
#include <spi-generic.h>
void intel_pch_finalize_smm(void)
{
+ u16 tco1_cnt;
+ u16 pmbase;
+
if (CONFIG_LOCK_SPI_ON_RESUME_RO || CONFIG_LOCK_SPI_ON_RESUME_NO_ACCESS) {
/* Copy flash regions from FREG0-4 to PR0-4
and enable write protection bit31 */
@@ -66,6 +70,12 @@
pci_write_config32(PCI_DEV(0, 27, 0), 0x74,
pci_read_config32(PCI_DEV(0, 27, 0), 0x74));
+ /* TCO_Lock */
+ pmbase = smm_get_pmbase();
+ tco1_cnt = inw(pmbase + TCO1_CNT);
+ tco1_cnt |= TCO_LOCK;
+ outw(tco1_cnt, pmbase + TCO1_CNT);
+
/* Indicate finalize step with post code */
outb(POST_OS_BOOT, 0x80);
}