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review.coreboot.org / coreboot / cd49cce7b70e80b4acc49b56bb2bb94370b4d867 / . / src / drivers / intel / fsp1_0 / cache_as_ram.inc
blob: 7897dd400374065fee307c8cedfb5ab7afbc0ac4 [file] [log] [blame]
Martin Rotha6427162014-04-25 14:12:13 -0600[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
5 * Copyright (C) 2007-2008 coresystems GmbH
6 * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
Martin Rotha6427162014-04-25 14:12:13 -0600[diff] [blame]16 */
17
Martin Rotha6427162014-04-25 14:12:13 -0600[diff] [blame]18#include <cpu/x86/mtrr.h>
19#include <cpu/x86/cache.h>
20#include <cpu/x86/post_code.h>
Martin Rotha6427162014-04-25 14:12:13 -0600[diff] [blame]21
Elyes HAOUAS6ece0ad2018-12-27 09:42:58 +0100[diff] [blame]22 cmp $0, %eax
23 je cache_as_ram
24 mov $0xa0, %eax
25 jmp .Lhlt
Martin Rotha6427162014-04-25 14:12:13 -0600[diff] [blame]26
27cache_as_ram:
28 post_code(0x20)
29
30 /*
31 * Find the FSP binary in cbfs.
32 * Make a fake stack that has the return value back to this code.
33 */
Elyes HAOUAS6ece0ad2018-12-27 09:42:58 +0100[diff] [blame]34 lea fake_fsp_stack, %esp
35 jmp find_fsp_bypass_prologue
Martin Rotha6427162014-04-25 14:12:13 -0600[diff] [blame]36find_fsp_ret:
37 /* Save the FSP location */
Elyes HAOUAS6ece0ad2018-12-27 09:42:58 +0100[diff] [blame]38 mov %eax, %ebp
39 cmp $CONFIG_FSP_LOC, %eax
40 jae find_fsp_ok
41 mov $0xb0, %eax
42 jmp .Lhlt
Martin Rotha6427162014-04-25 14:12:13 -0600[diff] [blame]43
Alexandru Gagniuc47818b42015-02-18 14:51:41 -0600[diff] [blame]44find_fsp_ok:
Duncan Lauriefb509832015-11-22 14:53:57 -0800[diff] [blame]45 post_code(POST_FSP_TEMP_RAM_INIT)
Martin Rotha6427162014-04-25 14:12:13 -0600[diff] [blame]46
47 /* Calculate entry into FSP */
Elyes HAOUAS6ece0ad2018-12-27 09:42:58 +0100[diff] [blame]48 mov 0x30(%ebp), %eax /* Load TempRamInitEntry */
49 add 0x1c(%ebp), %eax /* add in the offset for the FSP base address */
Martin Rotha6427162014-04-25 14:12:13 -0600[diff] [blame]50
51 /*
52 * Pass early init variables on a fake stack (no memory yet)
53 * as well as the return location
54 */
Elyes HAOUAS6ece0ad2018-12-27 09:42:58 +0100[diff] [blame]55 lea CAR_init_stack, %esp
Martin Rotha6427162014-04-25 14:12:13 -0600[diff] [blame]56
57 /* call FSP binary to setup temporary stack */
Elyes HAOUAS6ece0ad2018-12-27 09:42:58 +0100[diff] [blame]58 jmp *%eax
Martin Rotha6427162014-04-25 14:12:13 -0600[diff] [blame]59
60CAR_init_done:
Elyes HAOUAS6ece0ad2018-12-27 09:42:58 +0100[diff] [blame]61 addl $4, %esp
62 cmp $0, %eax
63 je car_init_ok
64 add $0xc0, %eax
65 jmp .Lhlt
Alexandru Gagniuc47818b42015-02-18 14:51:41 -0600[diff] [blame]66
67car_init_ok:
Martin Rotha6427162014-04-25 14:12:13 -0600[diff] [blame]68
69 /* Save FSP_INFO_HEADER location in ebx */
Elyes HAOUAS6ece0ad2018-12-27 09:42:58 +0100[diff] [blame]70 mov %ebp, %ebx
Martin Rotha6427162014-04-25 14:12:13 -0600[diff] [blame]71
72 /*
73 * set up bootloader stack
74 * ecx: stack base
75 * edx: stack top
76 */
Elyes HAOUAS6ece0ad2018-12-27 09:42:58 +0100[diff] [blame]77 mov %edx, %esp
78 movl %esp, %ebp
Martin Roth9cd15532015-01-11 14:58:47 -0700[diff] [blame]79
80 /* Clear the cbmem CAR memory region. */
Elyes HAOUAS6ece0ad2018-12-27 09:42:58 +0100[diff] [blame]81 movl %ecx, %edi
82 movl %edx, %ecx
83 sub %edi, %ecx
84 shr $2, %ecx
85 xorl %eax, %eax
86 rep stosl
Martin Rotha6427162014-04-25 14:12:13 -0600[diff] [blame]87
88before_romstage:
89 post_code(0x23)
90
91 /* Call romstage.c main function. */
Elyes HAOUAS6ece0ad2018-12-27 09:42:58 +0100[diff] [blame]92 pushl %ebx /* main takes FSP_INFO_HEADER as its argument */
93 call main /* does not return */
94 movb $0xB8, %ah
95 jmp .Lhlt
Martin Rotha6427162014-04-25 14:12:13 -0600[diff] [blame]96
Martin Rotha6427162014-04-25 14:12:13 -0600[diff] [blame]97.Lhlt:
Julius Wernercd49cce2019-03-05 16:53:33 -0800[diff] [blame^]98#if CONFIG(POST_IO)
Elyes HAOUAS6ece0ad2018-12-27 09:42:58 +0100[diff] [blame]99 outb %al, $CONFIG_POST_IO_PORT
Martin Rotha6427162014-04-25 14:12:13 -0600[diff] [blame]100#endif
Alexandru Gagniuc47818b42015-02-18 14:51:41 -0600[diff] [blame]101 hlt
Elyes HAOUAS6ece0ad2018-12-27 09:42:58 +0100[diff] [blame]102 jmp .Lhlt
Martin Rotha6427162014-04-25 14:12:13 -0600[diff] [blame]103
104/*
105 * esp is set to this location so that the call into and return from the FSP
106 * in find_fsp will work.
107 */
108 .align 4
109fake_fsp_stack:
Elyes HAOUAS6ece0ad2018-12-27 09:42:58 +0100[diff] [blame]110 .long find_fsp_ret
Martin Rotha6427162014-04-25 14:12:13 -0600[diff] [blame]111
112CAR_init_params:
Elyes HAOUAS6ece0ad2018-12-27 09:42:58 +0100[diff] [blame]113 .long dummy_microcode
114 .long 0
115 .long CACHE_ROM_BASE /* Firmware Location */
116 .long CACHE_ROM_SIZE /* Total Firmware Length */
Martin Rotha6427162014-04-25 14:12:13 -0600[diff] [blame]117
118CAR_init_stack:
Elyes HAOUAS6ece0ad2018-12-27 09:42:58 +0100[diff] [blame]119 .long CAR_init_done
120 .long CAR_init_params
York Yang3ecfdbd2015-10-14 06:52:32 -0700[diff] [blame]121
122dummy_microcode:
Elyes HAOUAS6ece0ad2018-12-27 09:42:58 +0100[diff] [blame]123 .long 0