| Martin Roth | a642716 | 2014-04-25 14:12:13 -0600 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com> |
| 5 | * Copyright (C) 2007-2008 coresystems GmbH |
| 6 | * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 20 | */ |
| 21 | |
| 22 | #include <cpu/x86/stack.h> |
| 23 | #include <cpu/x86/mtrr.h> |
| 24 | #include <cpu/x86/cache.h> |
| 25 | #include <cpu/x86/post_code.h> |
| 26 | #include <cbmem.h> |
| 27 | |
| 28 | #ifndef CONFIG_FSP_LOC |
| 29 | # error "CONFIG_FSP_LOC must be set." |
| 30 | #endif |
| 31 | |
| 32 | #ifndef CONFIG_POST_IO |
| 33 | # error "CONFIG_POST_IO must be set." |
| 34 | #endif |
| 35 | |
| 36 | #if CONFIG_POST_IO |
| 37 | # ifndef CONFIG_POST_IO_PORT |
| 38 | # error "CONFIG_POST_IO_PORT must be set." |
| 39 | # endif |
| 40 | #endif |
| 41 | |
| 42 | #ifndef CONFIG_CPU_MICROCODE_CBFS_LOC |
| 43 | # error "CONFIG_CPU_MICROCODE_CBFS_LOC must be set." |
| 44 | #endif |
| 45 | |
| 46 | #define LHLT_DELAY 0x50000 /* I/O delay between post codes on failure */ |
| 47 | |
| 48 | cmp $0, %eax |
| 49 | jne bisthalt |
| 50 | |
| 51 | cache_as_ram: |
| 52 | post_code(0x20) |
| 53 | |
| 54 | /* |
| 55 | * Find the FSP binary in cbfs. |
| 56 | * Make a fake stack that has the return value back to this code. |
| 57 | */ |
| 58 | lea fake_fsp_stack, %esp |
| 59 | jmp find_fsp |
| 60 | find_fsp_ret: |
| 61 | /* Save the FSP location */ |
| 62 | mov %eax, %ebp |
| 63 | cmp $CONFIG_FSP_LOC, %eax |
| 64 | jb halt1 |
| 65 | |
| 66 | post_code(0x22) |
| 67 | |
| 68 | /* Calculate entry into FSP */ |
| 69 | mov 0x30(%ebp), %eax /* Load TempRamInitEntry */ |
| 70 | add 0x1c(%ebp), %eax /* add in the offset for the FSP base address */ |
| 71 | |
| 72 | /* |
| 73 | * Pass early init variables on a fake stack (no memory yet) |
| 74 | * as well as the return location |
| 75 | */ |
| 76 | lea CAR_init_stack, %esp |
| 77 | |
| 78 | /* call FSP binary to setup temporary stack */ |
| 79 | jmp *%eax |
| 80 | |
| 81 | CAR_init_done: |
| 82 | addl $4, %esp |
| 83 | cmp $0, %eax |
| 84 | jne halt2 |
| 85 | |
| 86 | /* Save FSP_INFO_HEADER location in ebx */ |
| 87 | mov %ebp, %ebx |
| 88 | |
| 89 | /* |
| 90 | * set up bootloader stack |
| 91 | * ecx: stack base |
| 92 | * edx: stack top |
| 93 | */ |
| 94 | lea -4(%edx), %esp |
| 95 | movl %esp, %ebp |
| 96 | pushl %ebx |
| 97 | |
| 98 | before_romstage: |
| 99 | post_code(0x23) |
| 100 | |
| 101 | /* Call romstage.c main function. */ |
| 102 | call main /* does not return */ |
| 103 | movb $0xB8, %ah |
| 104 | jmp .Lhlt |
| 105 | |
| 106 | bisthalt: |
| 107 | movb $0xB9, %ah |
| 108 | jmp .Lhlt |
| 109 | |
| 110 | halt1: |
| 111 | /* |
| 112 | * Failures for postcode 0xBA - failed in find_fsp() |
| 113 | * |
| 114 | * Values are: |
| 115 | * 0x01 - FV signature, "_FVH" not present |
| 116 | * 0x02 - FFS GUID not present |
| 117 | * 0x03 - FSP INFO Header not found |
| 118 | * 0x04 - ImageBase does not equal CONFIG_FSP_LOC - Is the FSP rebased to |
| 119 | * a different location, or does it need to be? |
| 120 | * 0x05 - FSP INFO Header signature "FSPH" not found |
| 121 | * 0x06 - FSP Image ID is not the expected ID. |
| 122 | */ |
| 123 | movb $0xBA, %ah |
| 124 | jmp .Lhlt |
| 125 | |
| 126 | halt2: |
| 127 | /* |
| 128 | * Failures for postcode 0xBB - failed in the FSP: |
| 129 | * |
| 130 | * 0x00 - FSP_SUCCESS: Temp RAM was initialized successfully. |
| 131 | * 0x02 - FSP_INVALID_PARAMETER: Input parameters are invalid. |
| 132 | * 0x0E - FSP_NOT_FOUND: No valid microcode was found in the microcode region. |
| 133 | * 0x03 - FSP_UNSUPPORTED: The FSP calling conditions were not met. |
| 134 | * 0x07 - FSP_DEVICE_ERROR: Temp RAM initialization failed |
| 135 | * 0x14 - FSP_ALREADY_STARTED: Temp RAM initialization has been invoked |
| 136 | */ |
| 137 | movb $0xBB, %ah |
| 138 | |
| 139 | .Lhlt: |
| 140 | xchg %al, %ah |
| 141 | #if CONFIG_POST_IO |
| 142 | outb %al, $CONFIG_POST_IO_PORT |
| 143 | #else |
| 144 | post_code(POST_DEAD_CODE) |
| 145 | #endif |
| 146 | movl $LHLT_DELAY, %ecx |
| 147 | .Lhlt_Delay: |
| 148 | outb %al, $0xED |
| 149 | loop .Lhlt_Delay |
| 150 | jmp .Lhlt |
| 151 | |
| 152 | /* |
| 153 | * esp is set to this location so that the call into and return from the FSP |
| 154 | * in find_fsp will work. |
| 155 | */ |
| 156 | .align 4 |
| 157 | fake_fsp_stack: |
| 158 | .long find_fsp_ret |
| 159 | |
| 160 | CAR_init_params: |
| 161 | .long CONFIG_CPU_MICROCODE_CBFS_LOC |
| 162 | .long CONFIG_CPU_MICROCODE_CBFS_LEN |
| 163 | .long 0xFFFFFFFF - CACHE_ROM_SIZE + 1 /* Firmware Location */ |
| 164 | .long CACHE_ROM_SIZE /* Total Firmware Length */ |
| 165 | |
| 166 | CAR_init_stack: |
| 167 | .long CAR_init_done |
| 168 | .long CAR_init_params |
| 169 | |