Patrick Georgi | ac95903 | 2020-05-05 22:49:26 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 2 | |
| 3 | #include <assert.h> |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 4 | #include <console/console.h> |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 5 | #include <device/pci.h> |
| 6 | #include <hob_iiouds.h> |
| 7 | #include <intelblocks/cpulib.h> |
| 8 | #include <intelblocks/pcr.h> |
| 9 | #include <soc/iomap.h> |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 10 | #include <soc/msr.h> |
| 11 | #include <soc/pci_devs.h> |
| 12 | #include <soc/pcr_ids.h> |
| 13 | #include <soc/soc_util.h> |
Andrey Petrov | 662da6c | 2020-03-16 22:46:57 -0700 | [diff] [blame] | 14 | #include <soc/util.h> |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 15 | |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 16 | |
| 17 | /* |
| 18 | * +-------------------------+ TOLM |
| 19 | * | System Management Mode | |
| 20 | * | code and data | |
| 21 | * | (TSEG) | |
| 22 | * +-------------------------+ SMM base (aligned) |
| 23 | * | | |
| 24 | * | Chipset Reserved Memory | |
| 25 | * | | |
| 26 | * +-------------------------+ top_of_ram (aligned) |
| 27 | * | | |
| 28 | * | CBMEM Root | |
| 29 | * | | |
| 30 | * +-------------------------+ |
| 31 | * | | |
| 32 | * | FSP Reserved Memory | |
| 33 | * | | |
| 34 | * +-------------------------+ |
| 35 | * | | |
| 36 | * | Various CBMEM Entries | |
| 37 | * | | |
| 38 | * +-------------------------+ top_of_stack (8 byte aligned) |
| 39 | * | | |
| 40 | * | stack (CBMEM Entry) | |
| 41 | * | | |
| 42 | * +-------------------------+ |
| 43 | */ |
| 44 | |
Marc Jones | 645bca4 | 2020-11-02 14:29:46 -0700 | [diff] [blame] | 45 | const struct SystemMemoryMapHob *get_system_memory_map(void) |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 46 | { |
| 47 | size_t hob_size; |
Marc Jones | 645bca4 | 2020-11-02 14:29:46 -0700 | [diff] [blame] | 48 | const uint8_t mem_hob_guid[16] = FSP_SYSTEM_MEMORYMAP_HOB_GUID; |
| 49 | const struct SystemMemoryMapHob *memmap_addr; |
| 50 | |
| 51 | memmap_addr = fsp_find_extension_hob_by_guid(mem_hob_guid, &hob_size); |
Elyes Haouas | f1ba7d6 | 2022-09-13 10:03:44 +0200 | [diff] [blame] | 52 | assert(memmap_addr && hob_size != 0); |
Marc Jones | 645bca4 | 2020-11-02 14:29:46 -0700 | [diff] [blame] | 53 | |
| 54 | return memmap_addr; |
| 55 | } |
| 56 | |
Arthur Heymans | 550f55e | 2022-08-24 14:44:26 +0200 | [diff] [blame] | 57 | bool stack_needs_resource_alloc(const STACK_RES *res) |
Marc Jones | 645bca4 | 2020-11-02 14:29:46 -0700 | [diff] [blame] | 58 | { |
Arthur Heymans | 6408ada | 2020-11-12 17:33:00 +0100 | [diff] [blame] | 59 | // TODO: do we have situation with only bux 0 and one stack? |
| 60 | return res->BusBase < res->BusLimit; |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 61 | } |
| 62 | |
Arthur Heymans | 550f55e | 2022-08-24 14:44:26 +0200 | [diff] [blame] | 63 | bool is_pcie_iio_stack_res(const STACK_RES *res) |
| 64 | { |
| 65 | return stack_needs_resource_alloc(res); |
| 66 | } |
| 67 | |
Jonathan Zhang | ca520a7 | 2023-01-23 18:14:53 -0800 | [diff] [blame] | 68 | uint8_t get_stack_busno(const uint8_t stack) |
| 69 | { |
| 70 | if (stack >= MAX_IIO_STACK) { |
| 71 | printk(BIOS_ERR, "%s: Stack %u does not exist!\n", __func__, stack); |
| 72 | return 0; |
| 73 | } |
| 74 | const pci_devfn_t dev = PCI_DEV(UBOX_DECS_BUS, UBOX_DECS_DEV, UBOX_DECS_FUNC); |
| 75 | const uint16_t offset = stack / 4 ? UBOX_DECS_CPUBUSNO1_CSR : UBOX_DECS_CPUBUSNO_CSR; |
| 76 | return pci_io_read_config32(dev, offset) >> (8 * (stack % 4)) & 0xff; |
| 77 | } |
| 78 | |
Marc Jones | 5851f9d | 2020-11-02 15:30:10 -0700 | [diff] [blame] | 79 | uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack) |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 80 | { |
Arthur Heymans | 83b2622 | 2020-11-06 11:50:55 +0100 | [diff] [blame] | 81 | const IIO_UDS *hob = get_iio_uds(); |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 82 | |
Marc Jones | 645bca4 | 2020-11-02 14:29:46 -0700 | [diff] [blame] | 83 | assert(socket < MAX_SOCKET && stack < MAX_IIO_STACK); |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 84 | |
Marc Jones | 645bca4 | 2020-11-02 14:29:46 -0700 | [diff] [blame] | 85 | return hob->PlatformData.CpuQpiInfo[socket].StackBus[stack]; |
| 86 | } |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 87 | |
Jonathan Zhang | ca520a7 | 2023-01-23 18:14:53 -0800 | [diff] [blame] | 88 | uint32_t get_socket_ubox_busno(uint32_t socket) |
| 89 | { |
| 90 | if (socket == 0) |
| 91 | return get_stack_busno(PCU_IIO_STACK); |
| 92 | |
| 93 | return get_socket_stack_busno(socket, PCU_IIO_STACK); |
| 94 | } |
| 95 | |
Marc Jones | 645bca4 | 2020-11-02 14:29:46 -0700 | [diff] [blame] | 96 | void config_reset_cpl3_csrs(void) |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 97 | { |
Marc Jones | 645bca4 | 2020-11-02 14:29:46 -0700 | [diff] [blame] | 98 | uint32_t data, plat_info, max_min_turbo_limit_ratio; |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 99 | |
Marc Jones | 645bca4 | 2020-11-02 14:29:46 -0700 | [diff] [blame] | 100 | for (uint32_t socket = 0; socket < MAX_SOCKET; ++socket) { |
| 101 | uint32_t bus = get_socket_stack_busno(socket, PCU_IIO_STACK); |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 102 | |
Marc Jones | 645bca4 | 2020-11-02 14:29:46 -0700 | [diff] [blame] | 103 | /* configure PCU_CR0_FUN csrs */ |
| 104 | pci_devfn_t cr0_dev = PCI_DEV(bus, PCU_DEV, PCU_CR0_FUN); |
Nico Huber | f4f365f | 2021-10-14 18:16:39 +0200 | [diff] [blame] | 105 | data = pci_s_read_config32(cr0_dev, PCU_CR0_P_STATE_LIMITS); |
Marc Jones | 645bca4 | 2020-11-02 14:29:46 -0700 | [diff] [blame] | 106 | data |= P_STATE_LIMITS_LOCK; |
Nico Huber | f4f365f | 2021-10-14 18:16:39 +0200 | [diff] [blame] | 107 | pci_s_write_config32(cr0_dev, PCU_CR0_P_STATE_LIMITS, data); |
Marc Jones | 645bca4 | 2020-11-02 14:29:46 -0700 | [diff] [blame] | 108 | |
Nico Huber | f4f365f | 2021-10-14 18:16:39 +0200 | [diff] [blame] | 109 | plat_info = pci_s_read_config32(cr0_dev, PCU_CR0_PLATFORM_INFO); |
Marc Jones | 645bca4 | 2020-11-02 14:29:46 -0700 | [diff] [blame] | 110 | dump_csr64("", cr0_dev, PCU_CR0_PLATFORM_INFO); |
| 111 | max_min_turbo_limit_ratio = |
| 112 | (plat_info & MAX_NON_TURBO_LIM_RATIO_MASK) >> |
| 113 | MAX_NON_TURBO_LIM_RATIO_SHIFT; |
| 114 | printk(BIOS_SPEW, "plat_info: 0x%x, max_min_turbo_limit_ratio: 0x%x\n", |
| 115 | plat_info, max_min_turbo_limit_ratio); |
| 116 | |
| 117 | /* configure PCU_CR1_FUN csrs */ |
| 118 | pci_devfn_t cr1_dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN); |
| 119 | |
Nico Huber | f4f365f | 2021-10-14 18:16:39 +0200 | [diff] [blame] | 120 | data = pci_s_read_config32(cr1_dev, PCU_CR1_SAPMCTL); |
Marc Jones | 645bca4 | 2020-11-02 14:29:46 -0700 | [diff] [blame] | 121 | /* clear bits 27:31 - FSP sets this with 0x7 which needs to be cleared */ |
| 122 | data &= 0x0fffffff; |
| 123 | data |= SAPMCTL_LOCK_MASK; |
Nico Huber | f4f365f | 2021-10-14 18:16:39 +0200 | [diff] [blame] | 124 | pci_s_write_config32(cr1_dev, PCU_CR1_SAPMCTL, data); |
Marc Jones | 645bca4 | 2020-11-02 14:29:46 -0700 | [diff] [blame] | 125 | |
| 126 | /* configure PCU_CR1_FUN csrs */ |
| 127 | pci_devfn_t cr2_dev = PCI_DEV(bus, PCU_DEV, PCU_CR2_FUN); |
| 128 | |
| 129 | data = PCIE_IN_PKGCSTATE_L1_MASK; |
Nico Huber | f4f365f | 2021-10-14 18:16:39 +0200 | [diff] [blame] | 130 | pci_s_write_config32(cr2_dev, PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK, data); |
Marc Jones | 645bca4 | 2020-11-02 14:29:46 -0700 | [diff] [blame] | 131 | |
| 132 | data = KTI_IN_PKGCSTATE_L1_MASK; |
Nico Huber | f4f365f | 2021-10-14 18:16:39 +0200 | [diff] [blame] | 133 | pci_s_write_config32(cr2_dev, PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK2, data); |
Marc Jones | 645bca4 | 2020-11-02 14:29:46 -0700 | [diff] [blame] | 134 | |
| 135 | data = PROCHOT_RATIO; |
| 136 | printk(BIOS_SPEW, "PCU_CR2_PROCHOT_RESPONSE_RATIO_REG data: 0x%x\n", data); |
Nico Huber | f4f365f | 2021-10-14 18:16:39 +0200 | [diff] [blame] | 137 | pci_s_write_config32(cr2_dev, PCU_CR2_PROCHOT_RESPONSE_RATIO_REG, data); |
Marc Jones | 645bca4 | 2020-11-02 14:29:46 -0700 | [diff] [blame] | 138 | dump_csr("", cr2_dev, PCU_CR2_PROCHOT_RESPONSE_RATIO_REG); |
| 139 | |
Nico Huber | f4f365f | 2021-10-14 18:16:39 +0200 | [diff] [blame] | 140 | data = pci_s_read_config32(cr2_dev, PCU_CR2_DYNAMIC_PERF_POWER_CTL); |
Marc Jones | 645bca4 | 2020-11-02 14:29:46 -0700 | [diff] [blame] | 141 | data |= UNOCRE_PLIMIT_OVERRIDE_SHIFT; |
Nico Huber | f4f365f | 2021-10-14 18:16:39 +0200 | [diff] [blame] | 142 | pci_s_write_config32(cr2_dev, PCU_CR2_DYNAMIC_PERF_POWER_CTL, data); |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 143 | } |
Marc Jones | e1db55b | 2020-09-28 16:53:19 -0600 | [diff] [blame] | 144 | } |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 145 | |
Marc Jones | 995a7e2 | 2020-10-28 17:08:54 -0600 | [diff] [blame] | 146 | /* |
| 147 | * EX: SKX-SP |
| 148 | * Ports Stack Stack(HOB) IioConfigIou |
| 149 | * ========================================== |
| 150 | * 0 CSTACK stack 0 IOU0 |
| 151 | * 1A..1D PSTACKZ stack 1 IOU1 |
| 152 | * 2A..2D PSTACK1 stack 2 IOU2 |
| 153 | * 3A..3D PSTACK2 stack 3 IOU3 |
| 154 | * 5A..4D PSTACK3 stack 4 IOU4 |
| 155 | * 5A..5D PSTACK4 stack 5 IOU5 |
| 156 | */ |
| 157 | int soc_get_stack_for_port(int port) |
| 158 | { |
| 159 | if (port == PORT_0) |
| 160 | return CSTACK; |
| 161 | else if (port >= PORT_1A && port <= PORT_1D) |
| 162 | return PSTACK0; |
| 163 | else if (port >= PORT_2A && port <= PORT_2D) |
| 164 | return PSTACK1; |
| 165 | else if (port >= PORT_3A && port <= PORT_3D) |
| 166 | return PSTACK2; |
| 167 | else if (port >= PORT_4A && port <= PORT_4D) |
| 168 | return PSTACK3; // MCP0 |
| 169 | else if (port >= PORT_5A && port <= PORT_5D) |
| 170 | return PSTACK4; // MCP1 |
| 171 | else |
| 172 | return -1; |
| 173 | } |
Arthur Heymans | a1cc557 | 2020-11-06 12:53:33 +0100 | [diff] [blame] | 174 | |
| 175 | uint8_t soc_get_iio_ioapicid(int socket, int stack) |
| 176 | { |
| 177 | uint8_t ioapic_id = socket ? 0xf : 0x9; |
| 178 | switch (stack) { |
| 179 | case CSTACK: |
| 180 | break; |
| 181 | case PSTACK0: |
| 182 | ioapic_id += 1; |
| 183 | break; |
| 184 | case PSTACK1: |
| 185 | ioapic_id += 2; |
| 186 | break; |
| 187 | case PSTACK2: |
| 188 | ioapic_id += 3; |
| 189 | break; |
| 190 | default: |
| 191 | return 0xff; |
| 192 | } |
| 193 | return ioapic_id; |
| 194 | } |