Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 1 | config SOC_INTEL_BAYTRAIL |
| 2 | bool |
| 3 | help |
| 4 | Bay Trail M/D part support. |
| 5 | |
| 6 | if SOC_INTEL_BAYTRAIL |
| 7 | |
| 8 | config CPU_SPECIFIC_OPTIONS |
| 9 | def_bool y |
Kyösti Mälkki | 6437409 | 2023-04-08 23:42:14 +0300 | [diff] [blame] | 10 | select ACPI_COMMON_MADT_IOAPIC |
Kyösti Mälkki | 69a1396 | 2023-04-08 14:10:48 +0300 | [diff] [blame] | 11 | select ACPI_COMMON_MADT_LAPIC |
Aaron Durbin | f5cfaa3 | 2016-07-13 23:20:07 -0500 | [diff] [blame] | 12 | select ACPI_INTEL_HARDWARE_SLEEP_VALUES |
Angel Pons | 8e035e3 | 2021-06-22 12:58:20 +0200 | [diff] [blame] | 13 | select ARCH_X86 |
Shelley Chen | 6c2568f | 2020-09-25 09:30:44 -0700 | [diff] [blame] | 14 | select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES |
Aaron Durbin | e8e118d | 2016-08-12 15:00:10 -0500 | [diff] [blame] | 15 | select BOOT_DEVICE_SUPPORTS_WRITES |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 16 | select CACHE_MRC_SETTINGS |
Aaron Durbin | 59d1d87 | 2014-01-14 17:34:10 -0600 | [diff] [blame] | 17 | select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED |
Kyösti Mälkki | 4851bf2 | 2014-12-27 12:57:06 +0200 | [diff] [blame] | 18 | select SUPPORT_CPU_UCODE_IN_CBFS |
Vadim Bendebury | c04e171 | 2013-09-27 16:21:04 -0700 | [diff] [blame] | 19 | select HAVE_SMI_HANDLER |
Patrick Rudolph | 45022ae | 2018-10-01 19:17:11 +0200 | [diff] [blame] | 20 | select SOUTHBRIDGE_INTEL_COMMON_RESET |
Kyösti Mälkki | 542fa6d | 2020-01-07 02:18:02 +0200 | [diff] [blame] | 21 | select SOUTHBRIDGE_INTEL_COMMON_SMBUS |
Arthur Heymans | b48d633 | 2019-06-04 14:51:19 +0200 | [diff] [blame] | 22 | select SOUTHBRIDGE_INTEL_COMMON_SPI_SILVERMONT |
Duncan Laurie | c6313db | 2014-01-16 11:18:36 -0800 | [diff] [blame] | 23 | select PCIEXP_ASPM |
| 24 | select PCIEXP_COMMON_CLOCK |
Isaac Christensen | d2044cc | 2014-10-01 13:37:36 -0600 | [diff] [blame] | 25 | select REG_SCRIPT |
Aaron Durbin | 16246ea | 2016-08-05 21:23:37 -0500 | [diff] [blame] | 26 | select RTC |
Vadim Bendebury | c04e171 | 2013-09-27 16:21:04 -0700 | [diff] [blame] | 27 | select SPI_FLASH |
| 28 | select SSE2 |
Aaron Durbin | ce7ecf9 | 2013-10-24 08:42:10 -0500 | [diff] [blame] | 29 | select TSC_MONOTONIC_TIMER |
Vadim Bendebury | c04e171 | 2013-09-27 16:21:04 -0700 | [diff] [blame] | 30 | select TSC_SYNC_MFENCE |
| 31 | select UDELAY_TSC |
Stefan Reinauer | 9616f3c | 2015-04-29 10:45:22 -0700 | [diff] [blame] | 32 | select SOC_INTEL_COMMON |
Stefan Tauner | ef8b957 | 2018-09-06 00:34:28 +0200 | [diff] [blame] | 33 | select INTEL_DESCRIPTOR_MODE_CAPABLE |
Angel Pons | 12d48cd | 2020-10-03 12:22:04 +0200 | [diff] [blame] | 34 | select HAVE_EM100PRO_SPI_CONSOLE_SUPPORT |
Matt DeVillier | be33a67 | 2018-03-11 22:44:41 -0500 | [diff] [blame] | 35 | select INTEL_GMA_ACPI |
| 36 | select INTEL_GMA_SWSMISCI |
Matt DeVillier | e5a1a4c | 2017-01-19 21:13:02 -0600 | [diff] [blame] | 37 | select CPU_INTEL_COMMON |
Arthur Heymans | b1c57d1 | 2019-01-10 20:28:48 +0100 | [diff] [blame] | 38 | select CPU_HAS_L2_ENABLE_MSR |
Kyösti Mälkki | e8a3af1 | 2022-11-19 18:39:22 +0200 | [diff] [blame] | 39 | select TCO_SPACE_NOT_YET_SPLIT |
Elyes Haouas | c876762 | 2023-07-09 12:36:49 +0200 | [diff] [blame^] | 40 | select NO_DDR5 |
| 41 | select NO_LPDDR4 |
| 42 | select NO_DDR4 |
| 43 | select USE_DDR3 |
| 44 | select NO_DDR2 |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 45 | |
Julius Werner | 1210b41 | 2017-03-27 19:26:32 -0700 | [diff] [blame] | 46 | config VBOOT |
Joel Kitching | 6672bd8 | 2019-04-10 16:06:21 +0800 | [diff] [blame] | 47 | select VBOOT_MUST_REQUEST_DISPLAY |
Julius Werner | 1210b41 | 2017-03-27 19:26:32 -0700 | [diff] [blame] | 48 | select VBOOT_STARTS_IN_ROMSTAGE |
| 49 | |
Shelley Chen | 4e9bb33 | 2021-10-20 15:43:45 -0700 | [diff] [blame] | 50 | config ECAM_MMCONF_BASE_ADDRESS |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 51 | default 0xe0000000 |
| 52 | |
Shelley Chen | 4e9bb33 | 2021-10-20 15:43:45 -0700 | [diff] [blame] | 53 | config ECAM_MMCONF_BUS_NUMBER |
Kyösti Mälkki | 6d08544 | 2021-02-14 01:55:18 +0200 | [diff] [blame] | 54 | int |
| 55 | default 256 |
| 56 | |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 57 | config MAX_CPUS |
| 58 | int |
| 59 | default 4 |
| 60 | |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 61 | config SMM_TSEG_SIZE |
| 62 | hex |
| 63 | default 0x800000 |
| 64 | |
| 65 | config SMM_RESERVED_SIZE |
| 66 | hex |
| 67 | default 0x100000 |
| 68 | |
| 69 | config HAVE_MRC |
Arthur Heymans | abe62be | 2018-06-17 21:36:22 +0200 | [diff] [blame] | 70 | bool "Add a System Agent binary" |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 71 | help |
Arthur Heymans | abe62be | 2018-06-17 21:36:22 +0200 | [diff] [blame] | 72 | Select this option to add a System Agent binary to |
| 73 | the resulting coreboot image. |
| 74 | |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 75 | Note: Without this binary coreboot will not work |
| 76 | |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 77 | config MRC_FILE |
Arthur Heymans | abe62be | 2018-06-17 21:36:22 +0200 | [diff] [blame] | 78 | string "Intel System Agent path and filename" |
| 79 | depends on HAVE_MRC |
| 80 | default "mrc.bin" |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 81 | help |
| 82 | The path and filename of the file to use as System Agent |
Arthur Heymans | abe62be | 2018-06-17 21:36:22 +0200 | [diff] [blame] | 83 | binary. |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 84 | |
| 85 | config MRC_BIN_ADDRESS |
| 86 | hex |
| 87 | default 0xfffa0000 |
| 88 | |
Shawn Nematbakhsh | 13d9341 | 2013-11-26 15:37:43 -0800 | [diff] [blame] | 89 | config MRC_RMT |
| 90 | bool "Enable MRC RMT training + debug prints" |
| 91 | default n |
| 92 | |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 93 | # Cache As RAM region layout: |
| 94 | # |
| 95 | # +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE + DCACHE_RAM_MRC_VAR_SIZE |
| 96 | # | MRC usage | |
| 97 | # | | |
Arthur Heymans | 179da7f | 2019-11-15 12:51:51 +0100 | [diff] [blame] | 98 | # -------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE |
| 99 | # | coreboot | |
| 100 | # | usage | |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 101 | # +-------------+ DCACHE_RAM_BASE |
| 102 | # |
| 103 | # Note that the MRC binary is linked to assume the region marked as "MRC usage" |
| 104 | # starts at DCACHE_RAM_BASE + DCACHE_RAM_SIZE. If those values change then |
| 105 | # a new MRC binary needs to be produced with the updated start and size |
| 106 | # information. |
| 107 | |
| 108 | config DCACHE_RAM_BASE |
| 109 | hex |
Aaron Durbin | 89f5292 | 2014-03-19 11:48:33 -0500 | [diff] [blame] | 110 | default 0xfe000000 |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 111 | |
| 112 | config DCACHE_RAM_SIZE |
| 113 | hex |
Aaron Durbin | 08a4613 | 2013-10-07 16:24:44 -0500 | [diff] [blame] | 114 | default 0x8000 |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 115 | help |
| 116 | The size of the cache-as-ram region required during bootblock |
| 117 | and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE |
| 118 | must add up to a power of 2. |
| 119 | |
| 120 | config DCACHE_RAM_MRC_VAR_SIZE |
| 121 | hex |
Aaron Durbin | 08a4613 | 2013-10-07 16:24:44 -0500 | [diff] [blame] | 122 | default 0x8000 |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 123 | help |
| 124 | The amount of cache-as-ram region required by the reference code. |
| 125 | |
Arthur Heymans | 179da7f | 2019-11-15 12:51:51 +0100 | [diff] [blame] | 126 | config DCACHE_BSP_STACK_SIZE |
| 127 | hex |
| 128 | default 0x2000 |
| 129 | |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 130 | config ENABLE_BUILTIN_COM1 |
| 131 | bool "Enable builtin COM1 Serial Port" |
| 132 | default n |
| 133 | help |
| 134 | The PMC has a legacy COM1 serial port. Choose this option to |
| 135 | configure the pads and enable it. This serial port can be used for |
| 136 | the debug console. |
| 137 | |
Vladimir Serbinenko | f1d6e7e | 2014-08-09 07:16:10 +0200 | [diff] [blame] | 138 | config HAVE_REFCODE_BLOB |
| 139 | depends on ARCH_X86 |
Mate Kukri | e231949 | 2020-07-04 11:20:07 +0200 | [diff] [blame] | 140 | bool "Use a binary refcode blob instead of native ModPHY init" |
Vladimir Serbinenko | f1d6e7e | 2014-08-09 07:16:10 +0200 | [diff] [blame] | 141 | default n |
| 142 | help |
Martin Roth | 26f97f9 | 2021-10-01 14:53:22 -0600 | [diff] [blame] | 143 | Use the ChromeBook refcode to initialize high-speed PHYs instead of |
Mate Kukri | e231949 | 2020-07-04 11:20:07 +0200 | [diff] [blame] | 144 | native code. |
Vladimir Serbinenko | f1d6e7e | 2014-08-09 07:16:10 +0200 | [diff] [blame] | 145 | |
| 146 | if HAVE_REFCODE_BLOB |
| 147 | |
Mate Kukri | e231949 | 2020-07-04 11:20:07 +0200 | [diff] [blame] | 148 | # Ask for the blob if the user wants it |
Vladimir Serbinenko | f1d6e7e | 2014-08-09 07:16:10 +0200 | [diff] [blame] | 149 | config REFCODE_BLOB_FILE |
| 150 | string "Path and filename to reference code blob." |
| 151 | default "refcode.elf" |
| 152 | help |
| 153 | The path and filename to the file to be added to cbfs. |
| 154 | |
| 155 | endif # HAVE_REFCODE_BLOB |
| 156 | |
Matt DeVillier | 0da3a8a | 2019-05-27 02:09:24 -0500 | [diff] [blame] | 157 | config VGA_BIOS_ID |
| 158 | string |
| 159 | depends on VGA_BIOS |
| 160 | default "8086,0f31" |
| 161 | |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 162 | endif |