nyan*: pinmux: fix PWM1/2 conflicts
GPIO_PU4/PH1 and _PU5/PH2 were set to use the same PWM1/2 SFIO.
Even though no problems were caused by this, correct it here
so we get a conflict-free pinmux map.
BUG=chrome-os-partner:27091
BRANCH=none
TEST=Built and booted on Nyan, ran TegraShell "pinmux check"
and saw no conflicts.
Original-Change-Id: Ib16341aa0c92b9a078d7f3254d4151e9592f40b0
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/194582
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit e06a5a62d381f803dd6574787795a51ce1f1fe74)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I055359dc80c0c878ba5f5faac17884a5506a826c
Reviewed-on: http://review.coreboot.org/7759
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
diff --git a/src/mainboard/google/nyan_big/romstage.c b/src/mainboard/google/nyan_big/romstage.c
index 48d3842..62cbd50 100644
--- a/src/mainboard/google/nyan_big/romstage.c
+++ b/src/mainboard/google/nyan_big/romstage.c
@@ -94,6 +94,10 @@
// EC in RW.
gpio_input_pullup(GPIO(U4));
+ // route PU4/5 to GMI to remove conflict w/PWM1/2.
+ pinmux_set_config(PINMUX_GPIO_PU4_INDEX, PINMUX_GPIO_PU4_FUNC_NOR); //s/b GMI
+ pinmux_set_config(PINMUX_GPIO_PU5_INDEX, PINMUX_GPIO_PU5_FUNC_NOR); //s/b GMI
+
// SOC and TPM reset GPIO, active low.
gpio_output(GPIO(I5), 1);