Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <assert.h> |
Subrata Banik | 99289a8 | 2020-12-22 10:54:44 +0530 | [diff] [blame] | 4 | #include <cbfs.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 5 | #include <console/console.h> |
| 6 | #include <device/device.h> |
| 7 | #include <device/pci.h> |
| 8 | #include <fsp/api.h> |
| 9 | #include <fsp/ppi/mp_service_ppi.h> |
| 10 | #include <fsp/util.h> |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 11 | #include <intelblocks/irq.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 12 | #include <intelblocks/lpss.h> |
| 13 | #include <intelblocks/xdci.h> |
| 14 | #include <intelpch/lockdown.h> |
| 15 | #include <intelblocks/mp_init.h> |
Deepti Deshatty | 8e7facf | 2021-05-12 17:45:37 +0530 | [diff] [blame] | 16 | #include <intelblocks/tcss.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 17 | #include <soc/gpio_soc_defs.h> |
| 18 | #include <soc/intel/common/vbt.h> |
| 19 | #include <soc/pci_devs.h> |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 20 | #include <soc/pcie.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 21 | #include <soc/ramstage.h> |
| 22 | #include <soc/soc_chip.h> |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 23 | #include <stdlib.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 24 | #include <string.h> |
| 25 | |
| 26 | /* THC assignment definition */ |
| 27 | #define THC_NONE 0 |
| 28 | #define THC_0 1 |
| 29 | #define THC_1 2 |
| 30 | |
| 31 | /* SATA DEVSLP idle timeout default values */ |
| 32 | #define DEF_DMVAL 15 |
| 33 | #define DEF_DITOVAL 625 |
| 34 | |
Tim Wawrzynczak | c0e82e7 | 2021-06-17 12:42:35 -0600 | [diff] [blame] | 35 | /* |
| 36 | * ME End of Post configuration |
| 37 | * 0 - Disable EOP. |
| 38 | * 1 - Send in PEI (Applicable for FSP in API mode) |
| 39 | * 2 - Send in DXE (Not applicable for FSP in API mode) |
| 40 | */ |
| 41 | enum fsp_end_of_post { |
| 42 | EOP_DISABLE = 0, |
| 43 | EOP_PEI = 1, |
| 44 | EOP_DXE = 2, |
| 45 | }; |
| 46 | |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 47 | static const struct slot_irq_constraints irq_constraints[] = { |
| 48 | { |
| 49 | .slot = SA_DEV_SLOT_IGD, |
| 50 | .fns = { |
| 51 | ANY_PIRQ(SA_DEVFN_IGD), |
| 52 | }, |
| 53 | }, |
| 54 | { |
| 55 | .slot = SA_DEV_SLOT_DPTF, |
| 56 | .fns = { |
| 57 | ANY_PIRQ(SA_DEVFN_DPTF), |
| 58 | }, |
| 59 | }, |
| 60 | { |
| 61 | .slot = SA_DEV_SLOT_IPU, |
| 62 | .fns = { |
| 63 | ANY_PIRQ(SA_DEVFN_IPU), |
| 64 | }, |
| 65 | }, |
| 66 | { |
| 67 | .slot = SA_DEV_SLOT_CPU_6, |
| 68 | .fns = { |
| 69 | ANY_PIRQ(SA_DEVFN_CPU_PCIE6_0), |
| 70 | ANY_PIRQ(SA_DEVFN_CPU_PCIE6_2), |
| 71 | }, |
| 72 | }, |
| 73 | { |
| 74 | .slot = SA_DEV_SLOT_TBT, |
| 75 | .fns = { |
| 76 | ANY_PIRQ(SA_DEVFN_TBT0), |
| 77 | ANY_PIRQ(SA_DEVFN_TBT1), |
| 78 | ANY_PIRQ(SA_DEVFN_TBT2), |
| 79 | ANY_PIRQ(SA_DEVFN_TBT3), |
| 80 | }, |
| 81 | }, |
| 82 | { |
| 83 | .slot = SA_DEV_SLOT_TCSS, |
| 84 | .fns = { |
| 85 | ANY_PIRQ(SA_DEVFN_TCSS_XHCI), |
| 86 | }, |
| 87 | }, |
| 88 | { |
| 89 | .slot = PCH_DEV_SLOT_ISH, |
| 90 | .fns = { |
| 91 | DIRECT_IRQ(PCH_DEVFN_ISH), |
| 92 | DIRECT_IRQ(PCH_DEVFN_GSPI2), |
| 93 | }, |
| 94 | }, |
| 95 | { |
| 96 | .slot = PCH_DEV_SLOT_XHCI, |
| 97 | .fns = { |
| 98 | ANY_PIRQ(PCH_DEVFN_XHCI), |
| 99 | ANY_PIRQ(PCH_DEVFN_CNVI_WIFI), |
| 100 | }, |
| 101 | }, |
| 102 | { |
| 103 | .slot = PCH_DEV_SLOT_SIO3, |
| 104 | .fns = { |
| 105 | DIRECT_IRQ(PCH_DEVFN_I2C0), |
| 106 | DIRECT_IRQ(PCH_DEVFN_I2C1), |
| 107 | DIRECT_IRQ(PCH_DEVFN_I2C2), |
| 108 | DIRECT_IRQ(PCH_DEVFN_I2C3), |
| 109 | }, |
| 110 | }, |
| 111 | { |
| 112 | .slot = PCH_DEV_SLOT_CSE, |
| 113 | .fns = { |
| 114 | ANY_PIRQ(PCH_DEVFN_CSE), |
| 115 | ANY_PIRQ(PCH_DEVFN_CSE_2), |
| 116 | ANY_PIRQ(PCH_DEVFN_CSE_IDER), |
| 117 | ANY_PIRQ(PCH_DEVFN_CSE_KT), |
| 118 | ANY_PIRQ(PCH_DEVFN_CSE_3), |
| 119 | ANY_PIRQ(PCH_DEVFN_CSE_4), |
| 120 | }, |
| 121 | }, |
| 122 | { |
| 123 | .slot = PCH_DEV_SLOT_SATA, |
| 124 | .fns = { |
| 125 | ANY_PIRQ(PCH_DEVFN_SATA), |
| 126 | }, |
| 127 | }, |
| 128 | { |
| 129 | .slot = PCH_DEV_SLOT_SIO4, |
| 130 | .fns = { |
| 131 | DIRECT_IRQ(PCH_DEVFN_I2C4), |
| 132 | DIRECT_IRQ(PCH_DEVFN_I2C5), |
| 133 | DIRECT_IRQ(PCH_DEVFN_UART2), |
| 134 | }, |
| 135 | }, |
| 136 | { |
| 137 | .slot = PCH_DEV_SLOT_PCIE, |
| 138 | .fns = { |
| 139 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE1, PCI_INT_A, PIRQ_A), |
| 140 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE2, PCI_INT_B, PIRQ_B), |
| 141 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE3, PCI_INT_C, PIRQ_C), |
| 142 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE4, PCI_INT_D, PIRQ_D), |
| 143 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE5, PCI_INT_A, PIRQ_A), |
| 144 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE6, PCI_INT_B, PIRQ_B), |
| 145 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE7, PCI_INT_C, PIRQ_C), |
| 146 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE8, PCI_INT_D, PIRQ_D), |
| 147 | }, |
| 148 | }, |
| 149 | { |
| 150 | .slot = PCH_DEV_SLOT_PCIE_1, |
| 151 | .fns = { |
| 152 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE9, PCI_INT_A, PIRQ_A), |
| 153 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE10, PCI_INT_B, PIRQ_B), |
| 154 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE11, PCI_INT_C, PIRQ_C), |
| 155 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE12, PCI_INT_D, PIRQ_D), |
| 156 | }, |
| 157 | }, |
| 158 | { |
| 159 | .slot = PCH_DEV_SLOT_SIO5, |
| 160 | .fns = { |
| 161 | FIXED_INT_ANY_PIRQ(PCH_DEVFN_UART0, PCI_INT_A), |
| 162 | FIXED_INT_ANY_PIRQ(PCH_DEVFN_UART1, PCI_INT_B), |
| 163 | ANY_PIRQ(PCH_DEVFN_GSPI0), |
| 164 | ANY_PIRQ(PCH_DEVFN_GSPI1), |
| 165 | }, |
| 166 | }, |
| 167 | { |
| 168 | .slot = PCH_DEV_SLOT_ESPI, |
| 169 | .fns = { |
| 170 | ANY_PIRQ(PCH_DEVFN_HDA), |
| 171 | ANY_PIRQ(PCH_DEVFN_SMBUS), |
| 172 | ANY_PIRQ(PCH_DEVFN_GBE), |
| 173 | FIXED_INT_ANY_PIRQ(PCH_DEVFN_TRACEHUB, PCI_INT_A), |
| 174 | }, |
| 175 | }, |
| 176 | }; |
| 177 | |
| 178 | static const SI_PCH_DEVICE_INTERRUPT_CONFIG *pci_irq_to_fsp(size_t *out_count) |
| 179 | { |
| 180 | const struct pci_irq_entry *entry = get_cached_pci_irqs(); |
| 181 | SI_PCH_DEVICE_INTERRUPT_CONFIG *config; |
| 182 | size_t pch_total = 0; |
| 183 | size_t cfg_count = 0; |
| 184 | |
| 185 | if (!entry) |
| 186 | return NULL; |
| 187 | |
| 188 | /* Count PCH devices */ |
| 189 | while (entry) { |
| 190 | if (PCI_SLOT(entry->devfn) >= MIN_PCH_SLOT) |
| 191 | ++pch_total; |
| 192 | entry = entry->next; |
| 193 | } |
| 194 | |
| 195 | /* Convert PCH device entries to FSP format */ |
| 196 | config = calloc(pch_total, sizeof(*config)); |
| 197 | entry = get_cached_pci_irqs(); |
| 198 | while (entry) { |
| 199 | if (PCI_SLOT(entry->devfn) < MIN_PCH_SLOT) { |
| 200 | entry = entry->next; |
| 201 | continue; |
| 202 | } |
| 203 | |
| 204 | config[cfg_count].Device = PCI_SLOT(entry->devfn); |
| 205 | config[cfg_count].Function = PCI_FUNC(entry->devfn); |
| 206 | config[cfg_count].IntX = (SI_PCH_INT_PIN)entry->pin; |
| 207 | config[cfg_count].Irq = entry->irq; |
| 208 | ++cfg_count; |
| 209 | |
| 210 | entry = entry->next; |
| 211 | } |
| 212 | |
| 213 | *out_count = cfg_count; |
| 214 | |
| 215 | return config; |
| 216 | } |
| 217 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 218 | /* |
| 219 | * Chip config parameter PcieRpL1Substates uses (UPD value + 1) |
| 220 | * because UPD value of 0 for PcieRpL1Substates means disabled for FSP. |
| 221 | * In order to ensure that mainboard setting does not disable L1 substates |
| 222 | * incorrectly, chip config parameter values are offset by 1 with 0 meaning |
| 223 | * use FSP UPD default. get_l1_substate_control() ensures that the right UPD |
| 224 | * value is set in fsp_params. |
| 225 | * 0: Use FSP UPD default |
| 226 | * 1: Disable L1 substates |
| 227 | * 2: Use L1.1 |
| 228 | * 3: Use L1.2 (FSP UPD default) |
| 229 | */ |
| 230 | static int get_l1_substate_control(enum L1_substates_control ctl) |
| 231 | { |
| 232 | if ((ctl > L1_SS_L1_2) || (ctl == L1_SS_FSP_DEFAULT)) |
| 233 | ctl = L1_SS_L1_2; |
| 234 | return ctl - 1; |
| 235 | } |
| 236 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 237 | __weak void mainboard_update_soc_chip_config(struct soc_intel_alderlake_config *config) |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 238 | { |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 239 | /* Override settings per board. */ |
| 240 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 241 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 242 | static void fill_fsps_lpss_params(FSP_S_CONFIG *s_cfg, |
| 243 | const struct soc_intel_alderlake_config *config) |
| 244 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 245 | for (int i = 0; i < CONFIG_SOC_INTEL_I2C_DEV_MAX; i++) |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 246 | s_cfg->SerialIoI2cMode[i] = config->SerialIoI2cMode[i]; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 247 | |
| 248 | for (int i = 0; i < CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX; i++) { |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 249 | s_cfg->SerialIoSpiMode[i] = config->SerialIoGSpiMode[i]; |
| 250 | s_cfg->SerialIoSpiCsMode[i] = config->SerialIoGSpiCsMode[i]; |
| 251 | s_cfg->SerialIoSpiCsState[i] = config->SerialIoGSpiCsState[i]; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 252 | } |
| 253 | |
| 254 | for (int i = 0; i < CONFIG_SOC_INTEL_UART_DEV_MAX; i++) |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 255 | s_cfg->SerialIoUartMode[i] = config->SerialIoUartMode[i]; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 256 | } |
| 257 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 258 | static void fill_fsps_cpu_params(FSP_S_CONFIG *s_cfg, |
| 259 | const struct soc_intel_alderlake_config *config) |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 260 | { |
Subrata Banik | 99289a8 | 2020-12-22 10:54:44 +0530 | [diff] [blame] | 261 | const struct microcode *microcode_file; |
| 262 | size_t microcode_len; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 263 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 264 | /* Locate microcode and pass to FSP-S for 2nd microcode loading */ |
Subrata Banik | 99289a8 | 2020-12-22 10:54:44 +0530 | [diff] [blame] | 265 | microcode_file = cbfs_map("cpu_microcode_blob.bin", µcode_len); |
| 266 | |
| 267 | if ((microcode_file != NULL) && (microcode_len != 0)) { |
| 268 | /* Update CPU Microcode patch base address/size */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 269 | s_cfg->MicrocodeRegionBase = (uint32_t)microcode_file; |
| 270 | s_cfg->MicrocodeRegionSize = (uint32_t)microcode_len; |
Subrata Banik | 99289a8 | 2020-12-22 10:54:44 +0530 | [diff] [blame] | 271 | } |
| 272 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 273 | /* Use coreboot MP PPI services if Kconfig is enabled */ |
| 274 | if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) |
| 275 | s_cfg->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); |
| 276 | } |
| 277 | |
| 278 | static void fill_fsps_igd_params(FSP_S_CONFIG *s_cfg, |
| 279 | const struct soc_intel_alderlake_config *config) |
| 280 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 281 | /* Load VBT before devicetree-specific config. */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 282 | s_cfg->GraphicsConfigPtr = (uintptr_t)vbt_get(); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 283 | |
| 284 | /* Check if IGD is present and fill Graphics init param accordingly */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 285 | s_cfg->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD); |
| 286 | s_cfg->LidStatus = CONFIG(RUN_FSP_GOP); |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 287 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 288 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 289 | static void fill_fsps_tcss_params(FSP_S_CONFIG *s_cfg, |
| 290 | const struct soc_intel_alderlake_config *config) |
| 291 | { |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 292 | s_cfg->TcssAuxOri = config->TcssAuxOri; |
Deepti Deshatty | 8e7facf | 2021-05-12 17:45:37 +0530 | [diff] [blame] | 293 | |
| 294 | /* Explicitly clear this field to avoid using defaults */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 295 | memset(s_cfg->IomTypeCPortPadCfg, 0, sizeof(s_cfg->IomTypeCPortPadCfg)); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 296 | |
| 297 | /* |
| 298 | * Set FSPS UPD ITbtConnectTopologyTimeoutInMs with value 0. FSP will |
| 299 | * evaluate this UPD value and skip sending command. There will be no |
| 300 | * delay for command completion. |
| 301 | */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 302 | s_cfg->ITbtConnectTopologyTimeoutInMs = 0; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 303 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 304 | /* D3Hot and D3Cold for TCSS */ |
| 305 | s_cfg->D3HotEnable = !config->TcssD3HotDisable; |
| 306 | s_cfg->D3ColdEnable = !config->TcssD3ColdDisable; |
| 307 | } |
| 308 | |
| 309 | static void fill_fsps_chipset_lockdown_params(FSP_S_CONFIG *s_cfg, |
| 310 | const struct soc_intel_alderlake_config *config) |
| 311 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 312 | /* Chipset Lockdown */ |
| 313 | if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) { |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 314 | s_cfg->PchLockDownGlobalSmi = 0; |
| 315 | s_cfg->PchLockDownBiosInterface = 0; |
| 316 | s_cfg->PchUnlockGpioPads = 1; |
| 317 | s_cfg->RtcMemoryLock = 0; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 318 | } else { |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 319 | s_cfg->PchLockDownGlobalSmi = 1; |
| 320 | s_cfg->PchLockDownBiosInterface = 1; |
| 321 | s_cfg->PchUnlockGpioPads = 0; |
| 322 | s_cfg->RtcMemoryLock = 1; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 323 | } |
Tim Wawrzynczak | c0e82e7 | 2021-06-17 12:42:35 -0600 | [diff] [blame] | 324 | |
| 325 | /* coreboot will send EOP before loading payload */ |
| 326 | s_cfg->EndOfPostMessage = EOP_DISABLE; |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 327 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 328 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 329 | static void fill_fsps_xhci_params(FSP_S_CONFIG *s_cfg, |
| 330 | const struct soc_intel_alderlake_config *config) |
| 331 | { |
| 332 | int i; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 333 | /* USB */ |
| 334 | for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 335 | s_cfg->PortUsb20Enable[i] = config->usb2_ports[i].enable; |
| 336 | s_cfg->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias; |
| 337 | s_cfg->Usb2PhyTxiset[i] = config->usb2_ports[i].tx_bias; |
| 338 | s_cfg->Usb2PhyPredeemp[i] = config->usb2_ports[i].tx_emp_enable; |
| 339 | s_cfg->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 340 | |
| 341 | if (config->usb2_ports[i].enable) |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 342 | s_cfg->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 343 | else |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 344 | s_cfg->Usb2OverCurrentPin[i] = OC_SKIP; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 345 | } |
| 346 | |
| 347 | for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 348 | s_cfg->PortUsb30Enable[i] = config->usb3_ports[i].enable; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 349 | if (config->usb3_ports[i].enable) |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 350 | s_cfg->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 351 | else |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 352 | s_cfg->Usb3OverCurrentPin[i] = OC_SKIP; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 353 | |
| 354 | if (config->usb3_ports[i].tx_de_emp) { |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 355 | s_cfg->Usb3HsioTxDeEmphEnable[i] = 1; |
| 356 | s_cfg->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 357 | } |
| 358 | if (config->usb3_ports[i].tx_downscale_amp) { |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 359 | s_cfg->Usb3HsioTxDownscaleAmpEnable[i] = 1; |
| 360 | s_cfg->Usb3HsioTxDownscaleAmp[i] = |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 361 | config->usb3_ports[i].tx_downscale_amp; |
| 362 | } |
| 363 | } |
| 364 | |
Maulik V Vaghela | 6935350 | 2021-04-14 14:01:02 +0530 | [diff] [blame] | 365 | for (i = 0; i < ARRAY_SIZE(config->tcss_ports); i++) { |
| 366 | if (config->tcss_ports[i].enable) |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 367 | s_cfg->CpuUsb3OverCurrentPin[i] = config->tcss_ports[i].ocpin; |
Maulik V Vaghela | 6935350 | 2021-04-14 14:01:02 +0530 | [diff] [blame] | 368 | } |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 369 | } |
Maulik V Vaghela | 6935350 | 2021-04-14 14:01:02 +0530 | [diff] [blame] | 370 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 371 | static void fill_fsps_xdci_params(FSP_S_CONFIG *s_cfg, |
| 372 | const struct soc_intel_alderlake_config *config) |
| 373 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 374 | /* Enable xDCI controller if enabled in devicetree and allowed */ |
Subrata Banik | e633804 | 2021-06-21 19:26:10 +0530 | [diff] [blame] | 375 | if (!xdci_can_enable()) |
| 376 | devfn_disable(pci_root_bus(), PCH_DEVFN_USBOTG); |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 377 | s_cfg->XdciEnable = is_devfn_enabled(PCH_DEVFN_USBOTG); |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 378 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 379 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 380 | static void fill_fsps_uart_params(FSP_S_CONFIG *s_cfg, |
| 381 | const struct soc_intel_alderlake_config *config) |
| 382 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 383 | /* PCH UART selection for FSP Debug */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 384 | s_cfg->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; |
| 385 | ASSERT(ARRAY_SIZE(s_cfg->SerialIoUartAutoFlow) > CONFIG_UART_FOR_CONSOLE); |
| 386 | s_cfg->SerialIoUartAutoFlow[CONFIG_UART_FOR_CONSOLE] = 0; |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 387 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 388 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 389 | static void fill_fsps_sata_params(FSP_S_CONFIG *s_cfg, |
| 390 | const struct soc_intel_alderlake_config *config) |
| 391 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 392 | /* SATA */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 393 | s_cfg->SataEnable = is_devfn_enabled(PCH_DEVFN_SATA); |
| 394 | if (s_cfg->SataEnable) { |
| 395 | s_cfg->SataMode = config->SataMode; |
| 396 | s_cfg->SataSalpSupport = config->SataSalpSupport; |
| 397 | memcpy(s_cfg->SataPortsEnable, config->SataPortsEnable, |
| 398 | sizeof(s_cfg->SataPortsEnable)); |
| 399 | memcpy(s_cfg->SataPortsDevSlp, config->SataPortsDevSlp, |
| 400 | sizeof(s_cfg->SataPortsDevSlp)); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 401 | } |
| 402 | |
| 403 | /* |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 404 | * Power Optimizer for SATA. |
| 405 | * SataPwrOptimizeDisable is default to 0. |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 406 | * Boards not needing the optimizers explicitly disables them by setting |
| 407 | * these disable variables to 1 in devicetree overrides. |
| 408 | */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 409 | s_cfg->SataPwrOptEnable = !(config->SataPwrOptimizeDisable); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 410 | /* |
| 411 | * Enable DEVSLP Idle Timeout settings DmVal and DitoVal. |
| 412 | * SataPortsDmVal is the DITO multiplier. Default is 15. |
| 413 | * SataPortsDitoVal is the DEVSLP Idle Timeout (DITO), Default is 625ms. |
| 414 | * The default values can be changed from devicetree. |
| 415 | */ |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 416 | for (size_t i = 0; i < ARRAY_SIZE(config->SataPortsEnableDitoConfig); i++) { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 417 | if (config->SataPortsEnableDitoConfig[i]) { |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 418 | s_cfg->SataPortsDmVal[i] = config->SataPortsDmVal[i]; |
| 419 | s_cfg->SataPortsDitoVal[i] = config->SataPortsDitoVal[i]; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 420 | } |
| 421 | } |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 422 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 423 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 424 | static void fill_fsps_thermal_params(FSP_S_CONFIG *s_cfg, |
| 425 | const struct soc_intel_alderlake_config *config) |
| 426 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 427 | /* Enable TCPU for processor thermal control */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 428 | s_cfg->Device4Enable = is_devfn_enabled(SA_DEVFN_DPTF); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 429 | |
| 430 | /* Set TccActivationOffset */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 431 | s_cfg->TccActivationOffset = config->tcc_offset; |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 432 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 433 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 434 | static void fill_fsps_lan_params(FSP_S_CONFIG *s_cfg, |
| 435 | const struct soc_intel_alderlake_config *config) |
| 436 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 437 | /* LAN */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 438 | s_cfg->PchLanEnable = is_devfn_enabled(PCH_DEVFN_GBE); |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 439 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 440 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 441 | static void fill_fsps_cnvi_params(FSP_S_CONFIG *s_cfg, |
| 442 | const struct soc_intel_alderlake_config *config) |
| 443 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 444 | /* CNVi */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 445 | s_cfg->CnviMode = is_devfn_enabled(PCH_DEVFN_CNVI_WIFI); |
| 446 | s_cfg->CnviBtCore = config->CnviBtCore; |
| 447 | s_cfg->CnviBtAudioOffload = config->CnviBtAudioOffload; |
Cliff Huang | bc1941f | 2021-02-10 17:41:41 -0800 | [diff] [blame] | 448 | /* Assert if CNVi BT is enabled without CNVi being enabled. */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 449 | assert(s_cfg->CnviMode || !s_cfg->CnviBtCore); |
Cliff Huang | bc1941f | 2021-02-10 17:41:41 -0800 | [diff] [blame] | 450 | /* Assert if CNVi BT offload is enabled without CNVi BT being enabled. */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 451 | assert(s_cfg->CnviBtCore || !s_cfg->CnviBtAudioOffload); |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 452 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 453 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 454 | static void fill_fsps_vmd_params(FSP_S_CONFIG *s_cfg, |
| 455 | const struct soc_intel_alderlake_config *config) |
| 456 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 457 | /* VMD */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 458 | s_cfg->VmdEnable = is_devfn_enabled(SA_DEVFN_VMD); |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 459 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 460 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 461 | static void fill_fsps_thc_params(FSP_S_CONFIG *s_cfg, |
| 462 | const struct soc_intel_alderlake_config *config) |
| 463 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 464 | /* THC */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 465 | s_cfg->ThcPort0Assignment = is_devfn_enabled(PCH_DEVFN_THC0) ? THC_0 : THC_NONE; |
| 466 | s_cfg->ThcPort1Assignment = is_devfn_enabled(PCH_DEVFN_THC1) ? THC_1 : THC_NONE; |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 467 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 468 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 469 | static void fill_fsps_tbt_params(FSP_S_CONFIG *s_cfg, |
| 470 | const struct soc_intel_alderlake_config *config) |
| 471 | { |
Bernardo Perez Priego | 095f97b | 2021-05-18 18:39:19 -0700 | [diff] [blame] | 472 | /* USB4/TBT */ |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 473 | for (int i = 0; i < ARRAY_SIZE(s_cfg->ITbtPcieRootPortEn); i++) |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 474 | s_cfg->ITbtPcieRootPortEn[i] = is_devfn_enabled(SA_DEVFN_TBT(i)); |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 475 | } |
Bernardo Perez Priego | 095f97b | 2021-05-18 18:39:19 -0700 | [diff] [blame] | 476 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 477 | static void fill_fsps_8254_params(FSP_S_CONFIG *s_cfg, |
| 478 | const struct soc_intel_alderlake_config *config) |
| 479 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 480 | /* Legacy 8254 timer support */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 481 | s_cfg->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER); |
| 482 | s_cfg->Enable8254ClockGatingOnS3 = !CONFIG(USE_LEGACY_8254_TIMER); |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 483 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 484 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 485 | static void fill_fsps_storage_params(FSP_S_CONFIG *s_cfg, |
| 486 | const struct soc_intel_alderlake_config *config) |
| 487 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 488 | /* Enable Hybrid storage auto detection */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 489 | s_cfg->HybridStorageMode = config->HybridStorageMode; |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 490 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 491 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 492 | static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg, |
| 493 | const struct soc_intel_alderlake_config *config) |
| 494 | { |
| 495 | uint32_t enable_mask = pcie_rp_enable_mask(get_pch_pcie_rp_table()); |
| 496 | for (int i = 0; i < CONFIG_MAX_PCH_ROOT_PORTS; i++) { |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 497 | if (!(enable_mask & BIT(i))) |
| 498 | continue; |
| 499 | const struct pcie_rp_config *rp_cfg = &config->pch_pcie_rp[i]; |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 500 | s_cfg->PcieRpL1Substates[i] = |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 501 | get_l1_substate_control(rp_cfg->PcieRpL1Substates); |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 502 | s_cfg->PcieRpLtrEnable[i] = !!(rp_cfg->flags & PCIE_RP_LTR); |
| 503 | s_cfg->PcieRpAdvancedErrorReporting[i] = !!(rp_cfg->flags & PCIE_RP_AER); |
| 504 | s_cfg->PcieRpHotPlug[i] = !!(rp_cfg->flags & PCIE_RP_HOTPLUG); |
| 505 | s_cfg->PcieRpClkReqDetect[i] = !!(rp_cfg->flags & PCIE_RP_CLK_REQ_DETECT); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 506 | } |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 507 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 508 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 509 | static void fill_fsps_misc_power_params(FSP_S_CONFIG *s_cfg, |
| 510 | const struct soc_intel_alderlake_config *config) |
| 511 | { |
| 512 | /* |
| 513 | * Power Optimizer for DMI |
| 514 | * DmiPwrOptimizeDisable is default to 0. |
| 515 | * Boards not needing the optimizers explicitly disables them by setting |
| 516 | * these disable variables to 1 in devicetree overrides. |
| 517 | */ |
| 518 | s_cfg->PchPwrOptEnable = !(config->DmiPwrOptimizeDisable); |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 519 | s_cfg->PmSupport = 1; |
| 520 | s_cfg->Hwp = 1; |
| 521 | s_cfg->Cx = 1; |
| 522 | s_cfg->PsOnEnable = 1; |
Subrata Banik | 6f1cb40 | 2021-06-09 22:11:12 +0530 | [diff] [blame] | 523 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 524 | |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 525 | static void fill_fsps_irq_params(FSP_S_CONFIG *s_cfg, |
| 526 | const struct soc_intel_alderlake_config *config) |
| 527 | { |
| 528 | if (!assign_pci_irqs(irq_constraints, ARRAY_SIZE(irq_constraints))) |
| 529 | die("ERROR: Unable to assign PCI IRQs, and no _PRT table available\n"); |
| 530 | |
| 531 | size_t pch_count = 0; |
| 532 | const SI_PCH_DEVICE_INTERRUPT_CONFIG *upd_irqs = pci_irq_to_fsp(&pch_count); |
| 533 | |
| 534 | s_cfg->DevIntConfigPtr = (UINT32)((uintptr_t)upd_irqs); |
| 535 | s_cfg->NumOfDevIntConfig = pch_count; |
| 536 | printk(BIOS_INFO, "IRQ: Using dynamically assigned PCI IO-APIC IRQs\n"); |
| 537 | } |
| 538 | |
Subrata Banik | 6f1cb40 | 2021-06-09 22:11:12 +0530 | [diff] [blame] | 539 | static void arch_silicon_init_params(FSPS_ARCH_UPD *s_arch_cfg) |
| 540 | { |
| 541 | /* EnableMultiPhaseSiliconInit for running MultiPhaseSiInit */ |
| 542 | s_arch_cfg->EnableMultiPhaseSiliconInit = 1; |
| 543 | } |
| 544 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 545 | static void soc_silicon_init_params(FSP_S_CONFIG *s_cfg, |
| 546 | struct soc_intel_alderlake_config *config) |
| 547 | { |
| 548 | /* Override settings per board if required. */ |
| 549 | mainboard_update_soc_chip_config(config); |
| 550 | |
V Sowmya | 6464c2a | 2021-06-25 10:20:25 +0530 | [diff] [blame] | 551 | const void (*fill_fsps_params[])(FSP_S_CONFIG *s_cfg, |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 552 | const struct soc_intel_alderlake_config *config) = { |
| 553 | fill_fsps_lpss_params, |
| 554 | fill_fsps_cpu_params, |
| 555 | fill_fsps_igd_params, |
| 556 | fill_fsps_tcss_params, |
| 557 | fill_fsps_chipset_lockdown_params, |
| 558 | fill_fsps_xhci_params, |
| 559 | fill_fsps_xdci_params, |
| 560 | fill_fsps_uart_params, |
| 561 | fill_fsps_sata_params, |
| 562 | fill_fsps_thermal_params, |
| 563 | fill_fsps_lan_params, |
| 564 | fill_fsps_cnvi_params, |
| 565 | fill_fsps_vmd_params, |
| 566 | fill_fsps_thc_params, |
| 567 | fill_fsps_tbt_params, |
| 568 | fill_fsps_8254_params, |
| 569 | fill_fsps_storage_params, |
| 570 | fill_fsps_pcie_params, |
| 571 | fill_fsps_misc_power_params, |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 572 | fill_fsps_irq_params, |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 573 | }; |
| 574 | |
| 575 | for (size_t i = 0; i < ARRAY_SIZE(fill_fsps_params); i++) |
| 576 | fill_fsps_params[i](s_cfg, config); |
| 577 | } |
| 578 | |
Subrata Banik | 6f1cb40 | 2021-06-09 22:11:12 +0530 | [diff] [blame] | 579 | /* UPD parameters to be initialized before SiliconInit */ |
| 580 | void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) |
| 581 | { |
| 582 | struct soc_intel_alderlake_config *config; |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 583 | FSP_S_CONFIG *s_cfg = &supd->FspsConfig; |
Subrata Banik | 6f1cb40 | 2021-06-09 22:11:12 +0530 | [diff] [blame] | 584 | FSPS_ARCH_UPD *s_arch_cfg = &supd->FspsArchUpd; |
| 585 | |
| 586 | config = config_of_soc(); |
Subrata Banik | 6f1cb40 | 2021-06-09 22:11:12 +0530 | [diff] [blame] | 587 | arch_silicon_init_params(s_arch_cfg); |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 588 | soc_silicon_init_params(s_cfg, config); |
| 589 | mainboard_silicon_init_params(s_cfg); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 590 | } |
| 591 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 592 | /* |
| 593 | * Callbacks for SoC/Mainboard specific overrides for FspMultiPhaseSiInit |
| 594 | * This platform supports below MultiPhaseSIInit Phase(s): |
| 595 | * Phase | FSP return point | Purpose |
| 596 | * ------- + ------------------------------------------------ + ------------------------------- |
| 597 | * 1 | After TCSS initialization completed | for TCSS specific init |
| 598 | */ |
| 599 | void platform_fsp_multi_phase_init_cb(uint32_t phase_index) |
| 600 | { |
| 601 | switch (phase_index) { |
| 602 | case 1: |
| 603 | /* TCSS specific initialization here */ |
Deepti Deshatty | 8e7facf | 2021-05-12 17:45:37 +0530 | [diff] [blame] | 604 | printk(BIOS_DEBUG, "FSP MultiPhaseSiInit %s/%s called\n", |
| 605 | __FILE__, __func__); |
| 606 | |
| 607 | if (CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS)) { |
| 608 | const config_t *config = config_of_soc(); |
| 609 | tcss_configure(config->typec_aux_bias_pads); |
| 610 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 611 | break; |
| 612 | default: |
| 613 | break; |
| 614 | } |
| 615 | } |
| 616 | |
| 617 | /* Mainboard GPIO Configuration */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 618 | __weak void mainboard_silicon_init_params(FSP_S_CONFIG *s_cfg) |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 619 | { |
| 620 | printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); |
| 621 | } |