Praveen hodagatta pranesh | 7e48b47 | 2019-01-04 01:10:25 +0800 | [diff] [blame] | 1 | chip soc/intel/skylake |
| 2 | |
| 3 | # GPE configuration |
| 4 | register "gpe0_dw0" = "GPP_C" |
| 5 | |
| 6 | # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f |
| 7 | register "gen2_dec" = "0x000c0201" |
| 8 | |
| 9 | # FSP Configuration |
Angel Pons | e16692e | 2020-08-03 12:54:48 +0200 | [diff] [blame] | 10 | register "DspEnable" = "1" |
Praveen hodagatta pranesh | 7e48b47 | 2019-01-04 01:10:25 +0800 | [diff] [blame] | 11 | |
| 12 | # VR Settings Configuration for 4 Domains |
| 13 | #+----------------+-------+-------+-------+-------+ |
| 14 | #| Domain/Setting | SA | IA | GTUS | GTS | |
| 15 | #+----------------+-------+-------+-------+-------+ |
| 16 | #| Psi1Threshold | 20A | 20A | 20A | 20A | |
| 17 | #| Psi2Threshold | 5A | 5A | 5A | 5A | |
| 18 | #| Psi3Threshold | 1A | 1A | 1A | 1A | |
| 19 | #| Psi3Enable | 1 | 1 | 1 | 1 | |
| 20 | #| Psi4Enable | 1 | 1 | 1 | 1 | |
| 21 | #| ImonSlope | 0 | 0 | 0 | 0 | |
| 22 | #| ImonOffset | 0 | 0 | 0 | 0 | |
| 23 | #| IccMax | 7A | 34A | 35A | 35A | |
| 24 | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | |
| 25 | #+----------------+-------+-------+-------+-------+ |
| 26 | register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ |
Felix Singer | 21b5a9a | 2023-10-23 07:26:28 +0200 | [diff] [blame] | 27 | .vr_config_enable = 1, |
| 28 | .psi1threshold = VR_CFG_AMP(20), |
| 29 | .psi2threshold = VR_CFG_AMP(5), |
| 30 | .psi3threshold = VR_CFG_AMP(1), |
| 31 | .psi3enable = 1, |
| 32 | .psi4enable = 1, |
| 33 | .imon_slope = 0, |
| 34 | .imon_offset = 0, |
| 35 | .icc_max = VR_CFG_AMP(7), |
| 36 | .voltage_limit = 1520 |
Praveen hodagatta pranesh | 7e48b47 | 2019-01-04 01:10:25 +0800 | [diff] [blame] | 37 | }" |
| 38 | |
| 39 | # Enable Root ports. |
| 40 | # PCIE Port 1 x4 -> SLOT1 |
| 41 | register "PcieRpEnable[0]" = "1" |
| 42 | register "PcieRpClkReqSupport[0]" = "1" |
| 43 | register "PcieRpClkReqNumber[0]" = "2" |
Alexander Goncharov | 893c3ae8 | 2023-02-04 15:20:37 +0400 | [diff] [blame] | 44 | # RP1, uses CLK SRC 2 |
Praveen hodagatta pranesh | 7e48b47 | 2019-01-04 01:10:25 +0800 | [diff] [blame] | 45 | register "PcieRpClkSrcNumber[0]" = "2" |
| 46 | |
| 47 | # PCIE Port 5 x1 -> SLOT2/LAN |
| 48 | register "PcieRpEnable[4]" = "1" |
| 49 | register "PcieRpClkReqSupport[4]" = "1" |
| 50 | register "PcieRpClkReqNumber[4]" = "3" |
Alexander Goncharov | 893c3ae8 | 2023-02-04 15:20:37 +0400 | [diff] [blame] | 51 | # RP5, uses CLK SRC 3 |
Praveen hodagatta pranesh | 7e48b47 | 2019-01-04 01:10:25 +0800 | [diff] [blame] | 52 | register "PcieRpClkSrcNumber[4]" = "3" |
| 53 | |
| 54 | # PCIE Port 6 x1 -> SLOT3 |
| 55 | register "PcieRpEnable[5]" = "1" |
| 56 | register "PcieRpClkReqSupport[5]" = "1" |
| 57 | register "PcieRpClkReqNumber[5]" = "1" |
Alexander Goncharov | 893c3ae8 | 2023-02-04 15:20:37 +0400 | [diff] [blame] | 58 | # RP6, uses CLK SRC 1 |
Praveen hodagatta pranesh | 7e48b47 | 2019-01-04 01:10:25 +0800 | [diff] [blame] | 59 | register "PcieRpClkSrcNumber[5]" = "1" |
| 60 | |
| 61 | # PCIE Port 7 Disabled |
| 62 | # PCIE Port 8 Disabled |
| 63 | # PCIE Port 9 x1 -> WLAN |
| 64 | register "PcieRpEnable[8]" = "1" |
| 65 | register "PcieRpClkReqSupport[8]" = "1" |
| 66 | register "PcieRpClkReqNumber[8]" = "5" |
Alexander Goncharov | 893c3ae8 | 2023-02-04 15:20:37 +0400 | [diff] [blame] | 67 | # RP9, uses CLK SRC 5 |
Praveen hodagatta pranesh | 7e48b47 | 2019-01-04 01:10:25 +0800 | [diff] [blame] | 68 | register "PcieRpClkSrcNumber[8]" = "5" |
| 69 | |
| 70 | # PCIE Port 10 x1 -> WiGig |
| 71 | register "PcieRpEnable[9]" = "1" |
| 72 | register "PcieRpClkReqSupport[9]" = "1" |
| 73 | register "PcieRpClkReqNumber[9]" = "4" |
Alexander Goncharov | 893c3ae8 | 2023-02-04 15:20:37 +0400 | [diff] [blame] | 74 | # RP10, uses CLK SRC 4 |
Praveen hodagatta pranesh | 7e48b47 | 2019-01-04 01:10:25 +0800 | [diff] [blame] | 75 | register "PcieRpClkSrcNumber[9]" = "4" |
| 76 | |
Felix Singer | cc93db9 | 2023-10-23 16:26:20 +0200 | [diff] [blame] | 77 | register "usb2_ports" = "{ |
| 78 | [0] = USB2_PORT_MAX(OC0), /* TYPE-A Port */ |
| 79 | [1] = USB2_PORT_MAX(OC2), /* TYPE-A Port */ |
| 80 | [2] = USB2_PORT_MAX(OC_SKIP), /* Bluetooth */ |
| 81 | [4] = USB2_PORT_MAX(OC_SKIP), /* Type-A Port */ |
| 82 | [5] = USB2_PORT_MAX(OC2), /* TYPE-A Port */ |
| 83 | [6] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ |
| 84 | [7] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ |
| 85 | [8] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ |
| 86 | [9] = USB2_PORT_MAX(OC1), /* TYPE-A Port */ |
| 87 | [10] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ |
| 88 | [11] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ |
| 89 | }" |
Praveen hodagatta pranesh | 7e48b47 | 2019-01-04 01:10:25 +0800 | [diff] [blame] | 90 | |
Felix Singer | cc93db9 | 2023-10-23 16:26:20 +0200 | [diff] [blame] | 91 | register "usb3_ports" = "{ |
| 92 | [0] = USB3_PORT_DEFAULT(OC0), /* TYPE-A Port */ |
| 93 | [1] = USB3_PORT_DEFAULT(OC_SKIP), /* TYPE-A Port */ |
| 94 | [2] = USB3_PORT_DEFAULT(OC_SKIP), /* TYPE-A Port */ |
| 95 | [3] = USB3_PORT_DEFAULT(OC1), /* TYPE-A Port */ |
| 96 | }" |
Praveen hodagatta pranesh | 7e48b47 | 2019-01-04 01:10:25 +0800 | [diff] [blame] | 97 | |
| 98 | register "SsicPortEnable" = "1" # Enable SSIC for WWAN |
| 99 | |
| 100 | # Must leave UART0 enabled or SD/eMMC will not work as PCI |
Felix Singer | 21b5a9a | 2023-10-23 07:26:28 +0200 | [diff] [blame] | 101 | register "SerialIoDevMode" = "{ |
| 102 | [PchSerialIoIndexI2C0] = PchSerialIoPci, |
| 103 | [PchSerialIoIndexI2C1] = PchSerialIoPci, |
| 104 | [PchSerialIoIndexI2C2] = PchSerialIoPci, |
| 105 | [PchSerialIoIndexI2C3] = PchSerialIoPci, |
| 106 | [PchSerialIoIndexI2C4] = PchSerialIoPci, |
| 107 | [PchSerialIoIndexI2C5] = PchSerialIoDisabled, |
| 108 | [PchSerialIoIndexSpi0] = PchSerialIoDisabled, |
| 109 | [PchSerialIoIndexSpi1] = PchSerialIoDisabled, |
| 110 | [PchSerialIoIndexUart0] = PchSerialIoPci, |
| 111 | [PchSerialIoIndexUart1] = PchSerialIoDisabled, |
| 112 | [PchSerialIoIndexUart2] = PchSerialIoSkipInit, |
Praveen hodagatta pranesh | 7e48b47 | 2019-01-04 01:10:25 +0800 | [diff] [blame] | 113 | }" |
| 114 | |
Praveen hodagatta pranesh | 7e48b47 | 2019-01-04 01:10:25 +0800 | [diff] [blame] | 115 | device domain 0 on |
Felix Singer | 2dff4f0 | 2023-11-16 01:17:31 +0100 | [diff] [blame] | 116 | device ref imgu on end |
| 117 | device ref cio on end |
| 118 | device ref pcie_rp1 on end # x4 SLOT1 |
| 119 | device ref pcie_rp5 on end # x1 SLOT2/LAN |
| 120 | device ref pcie_rp6 on end # x1 SLOT3 |
| 121 | device ref pcie_rp9 on end # x1 WLAN |
| 122 | device ref pcie_rp10 on end # x1 WIGIG |
| 123 | device ref lpc_espi on |
Praveen hodagatta pranesh | 7e48b47 | 2019-01-04 01:10:25 +0800 | [diff] [blame] | 124 | chip drivers/pc80/tpm |
| 125 | device pnp 0c31.0 on end |
| 126 | end |
Felix Singer | 2dff4f0 | 2023-11-16 01:17:31 +0100 | [diff] [blame] | 127 | end |
| 128 | device ref hda on end |
Praveen hodagatta pranesh | 7e48b47 | 2019-01-04 01:10:25 +0800 | [diff] [blame] | 129 | end |
| 130 | end |