Praveen hodagatta pranesh | 7e48b47 | 2019-01-04 01:10:25 +0800 | [diff] [blame] | 1 | chip soc/intel/skylake |
| 2 | |
| 3 | # GPE configuration |
| 4 | register "gpe0_dw0" = "GPP_C" |
| 5 | |
| 6 | # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f |
| 7 | register "gen2_dec" = "0x000c0201" |
| 8 | |
| 9 | # FSP Configuration |
Angel Pons | e16692e | 2020-08-03 12:54:48 +0200 | [diff] [blame^] | 10 | register "DspEnable" = "1" |
| 11 | register "IoBufferOwnership" = "0" |
Praveen hodagatta pranesh | 7e48b47 | 2019-01-04 01:10:25 +0800 | [diff] [blame] | 12 | register "HeciEnabled" = "0" |
| 13 | register "PmTimerDisabled" = "1" |
| 14 | register "Cio2Enable" = "1" |
| 15 | register "SaImguEnable" = "1" |
| 16 | |
| 17 | # VR Settings Configuration for 4 Domains |
| 18 | #+----------------+-------+-------+-------+-------+ |
| 19 | #| Domain/Setting | SA | IA | GTUS | GTS | |
| 20 | #+----------------+-------+-------+-------+-------+ |
| 21 | #| Psi1Threshold | 20A | 20A | 20A | 20A | |
| 22 | #| Psi2Threshold | 5A | 5A | 5A | 5A | |
| 23 | #| Psi3Threshold | 1A | 1A | 1A | 1A | |
| 24 | #| Psi3Enable | 1 | 1 | 1 | 1 | |
| 25 | #| Psi4Enable | 1 | 1 | 1 | 1 | |
| 26 | #| ImonSlope | 0 | 0 | 0 | 0 | |
| 27 | #| ImonOffset | 0 | 0 | 0 | 0 | |
| 28 | #| IccMax | 7A | 34A | 35A | 35A | |
| 29 | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | |
| 30 | #+----------------+-------+-------+-------+-------+ |
| 31 | register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ |
| 32 | .vr_config_enable = 1, \ |
Wim Vervoorn | 57aa8e3 | 2019-12-06 11:30:33 +0100 | [diff] [blame] | 33 | .psi1threshold = VR_CFG_AMP(20), \ |
| 34 | .psi2threshold = VR_CFG_AMP(5), \ |
| 35 | .psi3threshold = VR_CFG_AMP(1), \ |
Praveen hodagatta pranesh | 7e48b47 | 2019-01-04 01:10:25 +0800 | [diff] [blame] | 36 | .psi3enable = 1, \ |
| 37 | .psi4enable = 1, \ |
Wim Vervoorn | 57aa8e3 | 2019-12-06 11:30:33 +0100 | [diff] [blame] | 38 | .imon_slope = 0, \ |
| 39 | .imon_offset = 0, \ |
| 40 | .icc_max = VR_CFG_AMP(7), \ |
| 41 | .voltage_limit = 1520 \ |
Praveen hodagatta pranesh | 7e48b47 | 2019-01-04 01:10:25 +0800 | [diff] [blame] | 42 | }" |
| 43 | |
| 44 | # Enable Root ports. |
| 45 | # PCIE Port 1 x4 -> SLOT1 |
| 46 | register "PcieRpEnable[0]" = "1" |
| 47 | register "PcieRpClkReqSupport[0]" = "1" |
| 48 | register "PcieRpClkReqNumber[0]" = "2" |
| 49 | # RP1, uses uses CLK SRC 2 |
| 50 | register "PcieRpClkSrcNumber[0]" = "2" |
| 51 | |
| 52 | # PCIE Port 5 x1 -> SLOT2/LAN |
| 53 | register "PcieRpEnable[4]" = "1" |
| 54 | register "PcieRpClkReqSupport[4]" = "1" |
| 55 | register "PcieRpClkReqNumber[4]" = "3" |
| 56 | # RP5, uses uses CLK SRC 3 |
| 57 | register "PcieRpClkSrcNumber[4]" = "3" |
| 58 | |
| 59 | # PCIE Port 6 x1 -> SLOT3 |
| 60 | register "PcieRpEnable[5]" = "1" |
| 61 | register "PcieRpClkReqSupport[5]" = "1" |
| 62 | register "PcieRpClkReqNumber[5]" = "1" |
| 63 | # RP6, uses uses CLK SRC 1 |
| 64 | register "PcieRpClkSrcNumber[5]" = "1" |
| 65 | |
| 66 | # PCIE Port 7 Disabled |
| 67 | # PCIE Port 8 Disabled |
| 68 | # PCIE Port 9 x1 -> WLAN |
| 69 | register "PcieRpEnable[8]" = "1" |
| 70 | register "PcieRpClkReqSupport[8]" = "1" |
| 71 | register "PcieRpClkReqNumber[8]" = "5" |
| 72 | # RP9, uses uses CLK SRC 5 |
| 73 | register "PcieRpClkSrcNumber[8]" = "5" |
| 74 | |
| 75 | # PCIE Port 10 x1 -> WiGig |
| 76 | register "PcieRpEnable[9]" = "1" |
| 77 | register "PcieRpClkReqSupport[9]" = "1" |
| 78 | register "PcieRpClkReqNumber[9]" = "4" |
| 79 | # RP10, uses uses CLK SRC 4 |
| 80 | register "PcieRpClkSrcNumber[9]" = "4" |
| 81 | |
| 82 | # USB 2.0 Enable all ports |
| 83 | register "usb2_ports[0]" = "USB2_PORT_MAX(OC0)" # TYPE-A Port |
| 84 | register "usb2_ports[1]" = "USB2_PORT_MAX(OC2)" # TYPE-A Port |
| 85 | register "usb2_ports[2]" = "USB2_PORT_MAX(OC_SKIP)" # Bluetooth |
| 86 | register "usb2_ports[4]" = "USB2_PORT_MAX(OC_SKIP)" # Type-A Port |
| 87 | register "usb2_ports[5]" = "USB2_PORT_MAX(OC2)" # TYPE-A Port |
| 88 | register "usb2_ports[6]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port |
| 89 | register "usb2_ports[7]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port |
| 90 | register "usb2_ports[8]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port |
| 91 | register "usb2_ports[9]" = "USB2_PORT_MAX(OC1)" # TYPE-A Port |
| 92 | register "usb2_ports[10]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port |
| 93 | register "usb2_ports[11]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port |
| 94 | |
| 95 | # USB 3.0 Enable Port 1-4. Port 5 & 6 Disabled |
| 96 | register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # TYPE-A Port |
| 97 | register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port |
| 98 | register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port |
| 99 | register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" # TYPE-A Port |
| 100 | register "usb3_ports[4]" = "USB3_PORT_EMPTY" # Disabled |
| 101 | register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Disabled |
| 102 | |
| 103 | register "SsicPortEnable" = "1" # Enable SSIC for WWAN |
| 104 | |
| 105 | # Must leave UART0 enabled or SD/eMMC will not work as PCI |
| 106 | register "SerialIoDevMode" = "{ \ |
| 107 | [PchSerialIoIndexI2C0] = PchSerialIoPci, \ |
| 108 | [PchSerialIoIndexI2C1] = PchSerialIoPci, \ |
| 109 | [PchSerialIoIndexI2C2] = PchSerialIoPci, \ |
| 110 | [PchSerialIoIndexI2C3] = PchSerialIoPci, \ |
| 111 | [PchSerialIoIndexI2C4] = PchSerialIoPci, \ |
| 112 | [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ |
| 113 | [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \ |
| 114 | [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ |
| 115 | [PchSerialIoIndexUart0] = PchSerialIoPci, \ |
| 116 | [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ |
| 117 | [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \ |
| 118 | }" |
| 119 | |
| 120 | # Lock Down |
| 121 | register "common_soc_config" = "{ |
| 122 | .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, |
| 123 | }" |
| 124 | |
| 125 | device domain 0 on |
| 126 | device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1 |
| 127 | device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN |
| 128 | device pci 1c.5 on end # PCI Express Port 6 x1 SLOT3 |
| 129 | device pci 1d.0 on end # PCI Express Port 9 x1 WLAN |
| 130 | device pci 1d.1 on end # PCI Express Port 10 x1 WIGIG |
| 131 | device pci 1f.0 on |
| 132 | chip drivers/pc80/tpm |
| 133 | device pnp 0c31.0 on end |
| 134 | end |
| 135 | end # LPC Interface |
Felix Singer | 048d9b5 | 2020-07-25 14:31:58 +0200 | [diff] [blame] | 136 | device pci 1f.3 on end # Intel HDA |
Praveen hodagatta pranesh | 7e48b47 | 2019-01-04 01:10:25 +0800 | [diff] [blame] | 137 | end |
| 138 | end |