Angel Pons | ba38f37 | 2020-04-05 15:46:45 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 2 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 3 | /* |
| 4 | * The devicetree parser expects chip.h to reside directly in the path |
| 5 | * specified by the devicetree. |
| 6 | */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 7 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 8 | #ifndef _SOC_CHIP_H_ |
| 9 | #define _SOC_CHIP_H_ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 10 | |
Matt DeVillier | 8ff2ecd | 2020-03-29 16:58:48 -0500 | [diff] [blame] | 11 | #include <drivers/intel/gma/i915.h> |
Aaron Durbin | 789f2b6 | 2015-09-09 17:05:06 -0500 | [diff] [blame] | 12 | #include <fsp/util.h> |
Frans Hendriks | 2c63017 | 2019-04-02 15:06:29 +0200 | [diff] [blame] | 13 | #include <intelblocks/lpc_lib.h> |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 14 | #include <soc/pci_devs.h> |
Angel Pons | fbca40c | 2021-09-27 12:59:26 +0200 | [diff] [blame] | 15 | #include <types.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 16 | |
Jenny TC | 153ae10 | 2015-06-18 14:55:10 +0530 | [diff] [blame] | 17 | #define SVID_CONFIG1 1 |
| 18 | #define SVID_CONFIG3 3 |
| 19 | #define SVID_PMIC_CONFIG 8 |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 20 | |
Frans Hendriks | f26a198 | 2019-10-02 10:16:26 +0200 | [diff] [blame] | 21 | #define IGD_MEMSIZE_32MB 0x01 |
| 22 | #define IGD_MEMSIZE_64MB 0x02 |
| 23 | #define IGD_MEMSIZE_96MB 0x03 |
| 24 | #define IGD_MEMSIZE_128MB 0x04 |
| 25 | |
fdurairx | aff502e | 2015-08-21 15:36:53 -0700 | [diff] [blame] | 26 | enum lpe_clk_src { |
Lee Leahy | 6598b91 | 2017-03-16 17:30:09 -0700 | [diff] [blame] | 27 | LPE_CLK_SRC_XTAL, |
| 28 | LPE_CLK_SRC_PLL, |
fdurairx | aff502e | 2015-08-21 15:36:53 -0700 | [diff] [blame] | 29 | }; |
| 30 | |
shkim | cc728f0 | 2015-09-22 17:53:58 +0900 | [diff] [blame] | 31 | enum usb_comp_bg_value { |
| 32 | USB_COMP_BG_575_MV = 7, |
| 33 | USB_COMP_BG_650_MV = 6, |
| 34 | USB_COMP_BG_550_MV = 5, |
| 35 | USB_COMP_BG_537_MV = 4, |
| 36 | USB_COMP_BG_625_MV = 3, |
| 37 | USB_COMP_BG_700_MV = 2, |
| 38 | USB_COMP_BG_600_MV = 1, |
| 39 | USB_COMP_BG_675_MV = 0, |
| 40 | }; |
| 41 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 42 | struct soc_intel_braswell_config { |
Angel Pons | fbca40c | 2021-09-27 12:59:26 +0200 | [diff] [blame] | 43 | bool enable_xdp_tap; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 44 | |
Frans Hendriks | 2c63017 | 2019-04-02 15:06:29 +0200 | [diff] [blame] | 45 | enum serirq_mode serirq_mode; |
| 46 | |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 47 | /* Disable SLP_X stretching after SUS power well loss */ |
Angel Pons | fbca40c | 2021-09-27 12:59:26 +0200 | [diff] [blame] | 48 | bool disable_slp_x_stretch_sus_fail; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 49 | |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 50 | /* LPE Audio Clock configuration */ |
| 51 | enum lpe_clk_src lpe_codec_clk_src; /* Both are 19.2MHz */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 52 | |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 53 | /* Native SD Card controller - override controller capabilities */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 54 | uint32_t sdcard_cap_low; |
| 55 | uint32_t sdcard_cap_high; |
| 56 | |
| 57 | /* Enable devices in ACPI mode */ |
Angel Pons | fbca40c | 2021-09-27 12:59:26 +0200 | [diff] [blame] | 58 | bool lpss_acpi_mode; |
| 59 | bool emmc_acpi_mode; |
| 60 | bool sd_acpi_mode; |
| 61 | bool lpe_acpi_mode; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 62 | |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 63 | /* Allow PCIe devices to wake system from suspend */ |
Angel Pons | fbca40c | 2021-09-27 12:59:26 +0200 | [diff] [blame] | 64 | bool pcie_wake_enable; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 65 | |
shkim | cc728f0 | 2015-09-22 17:53:58 +0900 | [diff] [blame] | 66 | /* Program USB2_COMPBG register. |
Lee Leahy | 6598b91 | 2017-03-16 17:30:09 -0700 | [diff] [blame] | 67 | * [10:7] - select vref to AFE port |
| 68 | * x111 - 575mV, x110 - 650mV, x101 - 550mV, x100 - 537.5mV, |
| 69 | * x011 - 625mV, x010 - 700mV, x001 - 600mV, x000 - 675mV |
| 70 | */ |
shkim | cc728f0 | 2015-09-22 17:53:58 +0900 | [diff] [blame] | 71 | enum usb_comp_bg_value usb_comp_bg; |
| 72 | |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 73 | /* |
| 74 | * The following fields come from fsp_vpd.h .aka. VpdHeader.h. |
| 75 | * These are configuration values that are passed to FSP during MemoryInit. |
| 76 | */ |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 77 | uint8_t PcdMrcInitSpdAddr1; |
| 78 | uint8_t PcdMrcInitSpdAddr2; |
| 79 | uint8_t PcdIgdDvmt50PreAlloc; |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 80 | uint8_t PcdDvfsEnable; |
| 81 | uint8_t PcdCaMirrorEn; /* Command Address Mirroring Enabled */ |
shkim | cc728f0 | 2015-09-22 17:53:58 +0900 | [diff] [blame] | 82 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 83 | /* |
| 84 | * The following fields come from fsp_vpd.h .aka. VpdHeader.h. |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 85 | * These are configuration values that are passed to FSP during SiliconInit. |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 86 | */ |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 87 | uint8_t PcdSdcardMode; |
| 88 | uint8_t PcdEnableHsuart0; |
| 89 | uint8_t PcdEnableHsuart1; |
| 90 | uint8_t PcdEnableAzalia; |
| 91 | uint8_t PcdEnableSata; |
| 92 | uint8_t PcdEnableXhci; |
| 93 | uint8_t PcdEnableLpe; |
| 94 | uint8_t PcdEnableDma0; |
| 95 | uint8_t PcdEnableDma1; |
| 96 | uint8_t PcdEnableI2C0; |
| 97 | uint8_t PcdEnableI2C1; |
| 98 | uint8_t PcdEnableI2C2; |
| 99 | uint8_t PcdEnableI2C3; |
| 100 | uint8_t PcdEnableI2C4; |
| 101 | uint8_t PcdEnableI2C5; |
| 102 | uint8_t PcdEnableI2C6; |
| 103 | uint8_t PunitPwrConfigDisable; |
| 104 | uint8_t ChvSvidConfig; |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 105 | uint8_t PcdEmmcMode; |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 106 | uint8_t Usb2Port0PerPortPeTxiSet; |
| 107 | uint8_t Usb2Port0PerPortTxiSet; |
| 108 | uint8_t Usb2Port0IUsbTxEmphasisEn; |
| 109 | uint8_t Usb2Port0PerPortTxPeHalf; |
| 110 | uint8_t Usb2Port1PerPortPeTxiSet; |
| 111 | uint8_t Usb2Port1PerPortTxiSet; |
| 112 | uint8_t Usb2Port1IUsbTxEmphasisEn; |
| 113 | uint8_t Usb2Port1PerPortTxPeHalf; |
| 114 | uint8_t Usb2Port2PerPortPeTxiSet; |
| 115 | uint8_t Usb2Port2PerPortTxiSet; |
| 116 | uint8_t Usb2Port2IUsbTxEmphasisEn; |
| 117 | uint8_t Usb2Port2PerPortTxPeHalf; |
| 118 | uint8_t Usb2Port3PerPortPeTxiSet; |
| 119 | uint8_t Usb2Port3PerPortTxiSet; |
| 120 | uint8_t Usb2Port3IUsbTxEmphasisEn; |
| 121 | uint8_t Usb2Port3PerPortTxPeHalf; |
| 122 | uint8_t Usb2Port4PerPortPeTxiSet; |
| 123 | uint8_t Usb2Port4PerPortTxiSet; |
| 124 | uint8_t Usb2Port4IUsbTxEmphasisEn; |
| 125 | uint8_t Usb2Port4PerPortTxPeHalf; |
| 126 | uint8_t Usb3Lane0Ow2tapgen2deemph3p5; |
| 127 | uint8_t Usb3Lane1Ow2tapgen2deemph3p5; |
| 128 | uint8_t Usb3Lane2Ow2tapgen2deemph3p5; |
| 129 | uint8_t Usb3Lane3Ow2tapgen2deemph3p5; |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 130 | uint8_t PcdPchUsbSsicPort; |
| 131 | uint8_t PcdPchUsbHsicPort; |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 132 | uint8_t PcdPchSsicEnable; |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 133 | uint8_t PMIC_I2CBus; |
| 134 | uint8_t ISPEnable; |
| 135 | uint8_t ISPPciDevConfig; |
| 136 | uint8_t PcdSdDetectChk; /* Enable / Disable SD Card Detect Simulation */ |
| 137 | uint8_t I2C0Frequency; /* 0 - 100KHz, 1 - 400KHz, 2 - 1MHz */ |
| 138 | uint8_t I2C1Frequency; |
| 139 | uint8_t I2C2Frequency; |
| 140 | uint8_t I2C3Frequency; |
| 141 | uint8_t I2C4Frequency; |
| 142 | uint8_t I2C5Frequency; |
| 143 | uint8_t I2C6Frequency; |
Matt DeVillier | 8ff2ecd | 2020-03-29 16:58:48 -0500 | [diff] [blame] | 144 | |
| 145 | struct i915_gpu_controller_info gfx; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 146 | }; |
| 147 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 148 | #endif /* _SOC_CHIP_H_ */ |