Angel Pons | c3f58f6 | 2020-04-05 15:46:41 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 2 | |
Elyes HAOUAS | 8ebad6d | 2020-07-10 10:46:47 +0200 | [diff] [blame] | 3 | #include <stdint.h> |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 4 | #include <acpi/acpi.h> |
Aaron Durbin | 31be2c9 | 2016-12-03 22:08:20 -0600 | [diff] [blame] | 5 | #include <assert.h> |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 6 | #include <cbfs.h> |
| 7 | #include <cbmem.h> |
Patrick Rudolph | 45022ae | 2018-10-01 19:17:11 +0200 | [diff] [blame] | 8 | #include <cf9_reset.h> |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 9 | #include <console/console.h> |
Matt DeVillier | 85360723 | 2020-04-23 00:46:56 -0500 | [diff] [blame] | 10 | #include <device/dram/ddr3.h> |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 11 | #include <device/pci_def.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 12 | #include <device/pci_ops.h> |
Kyösti Mälkki | f555a58 | 2020-01-06 19:41:42 +0200 | [diff] [blame] | 13 | #include <device/smbus_host.h> |
Aaron Durbin | decd062 | 2017-12-15 12:26:40 -0700 | [diff] [blame] | 14 | #include <mrc_cache.h> |
Julius Werner | 18ea2d3 | 2014-10-07 16:42:17 -0700 | [diff] [blame] | 15 | #include <soc/gpio.h> |
Julius Werner | 18ea2d3 | 2014-10-07 16:42:17 -0700 | [diff] [blame] | 16 | #include <soc/iomap.h> |
| 17 | #include <soc/iosf.h> |
| 18 | #include <soc/pci_devs.h> |
Julius Werner | 18ea2d3 | 2014-10-07 16:42:17 -0700 | [diff] [blame] | 19 | #include <soc/romstage.h> |
Philipp Deppenwiese | fea2429 | 2017-10-17 17:02:29 +0200 | [diff] [blame] | 20 | #include <security/vboot/vboot_common.h> |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 21 | |
Kyösti Mälkki | f555a58 | 2020-01-06 19:41:42 +0200 | [diff] [blame] | 22 | uintptr_t smbus_base(void) |
| 23 | { |
| 24 | return SMBUS_BASE_ADDRESS; |
| 25 | } |
| 26 | |
| 27 | int smbus_enable_iobar(uintptr_t base) |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 28 | { |
| 29 | uint32_t reg; |
| 30 | const uint32_t smbus_dev = PCI_DEV(0, SMBUS_DEV, SMBUS_FUNC); |
| 31 | |
| 32 | /* SMBus I/O BAR */ |
Kyösti Mälkki | f555a58 | 2020-01-06 19:41:42 +0200 | [diff] [blame] | 33 | reg = base | 2; |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 34 | pci_write_config32(smbus_dev, PCI_BASE_ADDRESS_4, reg); |
| 35 | /* Enable decode of I/O space. */ |
| 36 | reg = pci_read_config16(smbus_dev, PCI_COMMAND); |
Angel Pons | 89739ba | 2020-07-25 02:46:39 +0200 | [diff] [blame] | 37 | reg |= PCI_COMMAND_IO; |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 38 | pci_write_config16(smbus_dev, PCI_COMMAND, reg); |
| 39 | /* Enable Host Controller */ |
| 40 | reg = pci_read_config8(smbus_dev, 0x40); |
| 41 | reg |= 1; |
| 42 | pci_write_config8(smbus_dev, 0x40, reg); |
| 43 | |
| 44 | /* Configure pads to be used for SMBus */ |
| 45 | score_select_func(PCU_SMB_CLK_PAD, 1); |
| 46 | score_select_func(PCU_SMB_DATA_PAD, 1); |
Kyösti Mälkki | f555a58 | 2020-01-06 19:41:42 +0200 | [diff] [blame] | 47 | |
| 48 | return 0; |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 49 | } |
| 50 | |
Aaron Durbin | 833ff35 | 2013-10-02 11:06:31 -0500 | [diff] [blame] | 51 | static void ABI_X86 send_to_console(unsigned char b) |
| 52 | { |
Kyösti Mälkki | 657e0be | 2014-02-04 19:03:57 +0200 | [diff] [blame] | 53 | do_putchar(b); |
Aaron Durbin | 833ff35 | 2013-10-02 11:06:31 -0500 | [diff] [blame] | 54 | } |
| 55 | |
Matt DeVillier | 85360723 | 2020-04-23 00:46:56 -0500 | [diff] [blame] | 56 | static void populate_smbios_tables(void *dram_data, int speed, int num_channels) |
| 57 | { |
| 58 | dimm_attr dimm; |
| 59 | enum spd_status status; |
| 60 | |
| 61 | /* Decode into dimm_attr struct */ |
| 62 | status = spd_decode_ddr3(&dimm, *(spd_raw_data *)dram_data); |
| 63 | |
| 64 | /* Some SPDs have bad CRCs, nothing we can do about it */ |
| 65 | if (status == SPD_STATUS_OK || status == SPD_STATUS_CRC_ERROR) { |
| 66 | /* Add table 17 entry for each channel */ |
| 67 | for (int i = 0; i < num_channels; i++) |
| 68 | spd_add_smbios17(i, 0, speed, &dimm); |
| 69 | } |
| 70 | } |
| 71 | |
| 72 | static void print_dram_info(void *dram_data) |
Aaron Durbin | 3ccb3ce | 2013-10-11 00:26:04 -0500 | [diff] [blame] | 73 | { |
| 74 | const int mrc_ver_reg = 0xf0; |
| 75 | const uint32_t soc_dev = PCI_DEV(0, SOC_DEV, SOC_FUNC); |
| 76 | uint32_t reg; |
| 77 | int num_channels; |
| 78 | int speed; |
| 79 | uint32_t ch0; |
| 80 | uint32_t ch1; |
| 81 | |
| 82 | reg = pci_read_config32(soc_dev, mrc_ver_reg); |
| 83 | |
| 84 | printk(BIOS_INFO, "MRC v%d.%02d\n", (reg >> 8) & 0xff, reg & 0xff); |
| 85 | |
| 86 | /* Number of channels enabled and DDR3 type. Determine number of |
| 87 | * channels by keying of the rank enable bits [3:0]. * */ |
| 88 | ch0 = iosf_dunit_ch0_read(DRP); |
| 89 | ch1 = iosf_dunit_ch1_read(DRP); |
| 90 | num_channels = 0; |
| 91 | if (ch0 & DRP_RANK_MASK) |
| 92 | num_channels++; |
| 93 | if (ch1 & DRP_RANK_MASK) |
| 94 | num_channels++; |
| 95 | |
| 96 | printk(BIOS_INFO, "%d channels of %sDDR3 @ ", num_channels, |
| 97 | (reg & (1 << 22)) ? "LP" : ""); |
| 98 | |
| 99 | /* DRAM frequency -- all channels run at same frequency. */ |
| 100 | reg = iosf_dunit_read(DTR0); |
| 101 | switch (reg & 0x3) { |
| 102 | case 0: |
| 103 | speed = 800; break; |
| 104 | case 1: |
| 105 | speed = 1066; break; |
| 106 | case 2: |
| 107 | speed = 1333; break; |
| 108 | case 3: |
| 109 | speed = 1600; break; |
| 110 | } |
| 111 | printk(BIOS_INFO, "%dMHz\n", speed); |
Matt DeVillier | 85360723 | 2020-04-23 00:46:56 -0500 | [diff] [blame] | 112 | |
| 113 | populate_smbios_tables(dram_data, speed, num_channels); |
Aaron Durbin | 3ccb3ce | 2013-10-11 00:26:04 -0500 | [diff] [blame] | 114 | } |
| 115 | |
Mate Kukri | e053493 | 2020-08-01 11:45:13 +0200 | [diff] [blame] | 116 | #define SPD_SIZE 256 |
| 117 | static u8 spd_buf[NUM_CHANNELS][SPD_SIZE]; |
| 118 | |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 119 | void raminit(struct mrc_params *mp, int prev_sleep_state) |
| 120 | { |
| 121 | int ret; |
| 122 | mrc_wrapper_entry_t mrc_entry; |
Mate Kukri | e053493 | 2020-08-01 11:45:13 +0200 | [diff] [blame] | 123 | size_t i; |
Shelley Chen | ad9cd68 | 2020-07-23 16:10:52 -0700 | [diff] [blame] | 124 | size_t mrc_size; |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 125 | |
| 126 | /* Fill in default entries. */ |
| 127 | mp->version = MRC_PARAMS_VER; |
Aaron Durbin | 833ff35 | 2013-10-02 11:06:31 -0500 | [diff] [blame] | 128 | mp->console_out = &send_to_console; |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 129 | mp->prev_sleep_state = prev_sleep_state; |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 130 | mp->rmt_enabled = CONFIG(MRC_RMT); |
Shawn Nematbakhsh | 51d787a | 2014-01-16 17:52:21 -0800 | [diff] [blame] | 131 | |
| 132 | /* Default to 2GiB IO hole. */ |
| 133 | if (!mp->io_hole_mb) |
| 134 | mp->io_hole_mb = 2048; |
| 135 | |
Shelley Chen | ad9cd68 | 2020-07-23 16:10:52 -0700 | [diff] [blame] | 136 | /* Assume boot device is memory mapped. */ |
| 137 | assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); |
| 138 | |
| 139 | mp->saved_data = mrc_cache_current_mmap_leak(MRC_TRAINING_DATA, |
| 140 | 0, |
| 141 | &mrc_size); |
| 142 | if (mp->saved_data) { |
| 143 | mp->saved_data_size = mrc_size; |
Aaron Durbin | f5cfaa3 | 2016-07-13 23:20:07 -0500 | [diff] [blame] | 144 | } else if (prev_sleep_state == ACPI_S3) { |
Aaron Durbin | 6e32893 | 2013-11-06 12:04:50 -0600 | [diff] [blame] | 145 | /* If waking from S3 and no cache then. */ |
| 146 | printk(BIOS_DEBUG, "No MRC cache found in S3 resume path.\n"); |
| 147 | post_code(POST_RESUME_FAILURE); |
Patrick Rudolph | 45022ae | 2018-10-01 19:17:11 +0200 | [diff] [blame] | 148 | system_reset(); |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 149 | } else { |
| 150 | printk(BIOS_DEBUG, "No MRC cache found.\n"); |
| 151 | } |
| 152 | |
Aaron Durbin | 1131889 | 2014-04-02 20:46:13 -0500 | [diff] [blame] | 153 | /* Determine if mrc.bin is in the cbfs. */ |
Julius Werner | 834b3ec | 2020-03-04 16:52:08 -0800 | [diff] [blame] | 154 | if (cbfs_map("mrc.bin", NULL) == NULL) { |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 155 | printk(BIOS_DEBUG, "Couldn't find mrc.bin\n"); |
| 156 | return; |
| 157 | } |
Aaron Durbin | 1131889 | 2014-04-02 20:46:13 -0500 | [diff] [blame] | 158 | |
| 159 | /* |
| 160 | * The entry point is currently the first instruction. Handle the |
| 161 | * case of an ELF file being put in the cbfs by setting the entry |
| 162 | * to the CONFIG_MRC_BIN_ADDRESS. |
| 163 | */ |
| 164 | mrc_entry = (void *)(uintptr_t)CONFIG_MRC_BIN_ADDRESS; |
| 165 | |
Mate Kukri | e053493 | 2020-08-01 11:45:13 +0200 | [diff] [blame] | 166 | if (mp->mainboard.dram_info_location == DRAM_INFO_SPD_SMBUS) { |
| 167 | /* Workaround for broken SMBus support in the MRC */ |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 168 | enable_smbus(); |
Mate Kukri | e053493 | 2020-08-01 11:45:13 +0200 | [diff] [blame] | 169 | mp->mainboard.dram_info_location = DRAM_INFO_SPD_MEM; |
| 170 | for (i = 0; i < NUM_CHANNELS; ++i) { |
| 171 | if (mp->mainboard.spd_addrs[i]) { |
| 172 | i2c_eeprom_read(mp->mainboard.spd_addrs[i], |
| 173 | 0, SPD_SIZE, spd_buf[i]); |
| 174 | /* NOTE: MRC looks for Channel 1 SPD at array |
| 175 | index 1 */ |
| 176 | mp->mainboard.dram_data[i] = spd_buf; |
| 177 | } |
| 178 | } |
| 179 | } |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 180 | |
| 181 | ret = mrc_entry(mp); |
| 182 | |
Aaron Durbin | f5cfaa3 | 2016-07-13 23:20:07 -0500 | [diff] [blame] | 183 | if (prev_sleep_state != ACPI_S3) { |
Aaron Durbin | 6e32893 | 2013-11-06 12:04:50 -0600 | [diff] [blame] | 184 | cbmem_initialize_empty(); |
Aaron Durbin | 42e6856 | 2015-06-09 13:55:51 -0500 | [diff] [blame] | 185 | } else if (cbmem_initialize()) { |
Aaron Durbin | 42e6856 | 2015-06-09 13:55:51 -0500 | [diff] [blame] | 186 | printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n"); |
| 187 | /* Failed S3 resume, reset to come up cleanly */ |
Patrick Rudolph | 45022ae | 2018-10-01 19:17:11 +0200 | [diff] [blame] | 188 | system_reset(); |
Aaron Durbin | 6e32893 | 2013-11-06 12:04:50 -0600 | [diff] [blame] | 189 | } |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 190 | |
Matt DeVillier | 85360723 | 2020-04-23 00:46:56 -0500 | [diff] [blame] | 191 | print_dram_info(mp->mainboard.dram_data[0]); |
| 192 | |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 193 | printk(BIOS_DEBUG, "MRC Wrapper returned %d\n", ret); |
| 194 | printk(BIOS_DEBUG, "MRC data at %p %d bytes\n", mp->data_to_save, |
| 195 | mp->data_to_save_size); |
| 196 | |
| 197 | if (mp->data_to_save != NULL && mp->data_to_save_size > 0) |
Aaron Durbin | 31be2c9 | 2016-12-03 22:08:20 -0600 | [diff] [blame] | 198 | mrc_cache_stash_data(MRC_TRAINING_DATA, 0, mp->data_to_save, |
| 199 | mp->data_to_save_size); |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 200 | } |