Michał Żygowski | 48be6b2 | 2019-06-27 12:19:18 +0200 | [diff] [blame] | 1 | chip soc/intel/skylake |
| 2 | |
| 3 | # Enable deep Sx states |
| 4 | register "deep_s3_enable_ac" = "0" |
| 5 | register "deep_s3_enable_dc" = "0" |
| 6 | register "deep_s5_enable_ac" = "1" |
| 7 | register "deep_s5_enable_dc" = "1" |
| 8 | register "deep_sx_config" = "DSX_EN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD" |
Felix Singer | 743242b | 2023-06-16 01:33:25 +0200 | [diff] [blame] | 9 | register "s0ix_enable" = true |
Michał Żygowski | 48be6b2 | 2019-06-27 12:19:18 +0200 | [diff] [blame] | 10 | |
| 11 | register "gpe0_dw0" = "GPP_B" |
| 12 | register "gpe0_dw1" = "GPP_D" |
| 13 | register "gpe0_dw2" = "GPP_E" |
| 14 | |
| 15 | register "gen1_dec" = "0x00fc0201" |
| 16 | register "gen2_dec" = "0x007c0a01" |
| 17 | register "gen3_dec" = "0x000c03e1" |
| 18 | register "gen4_dec" = "0x001c02e1" |
| 19 | |
Michał Żygowski | 48be6b2 | 2019-06-27 12:19:18 +0200 | [diff] [blame] | 20 | register "eist_enable" = "1" |
| 21 | |
| 22 | # Disable DPTF |
| 23 | register "dptf_enable" = "0" |
| 24 | |
Michał Żygowski | 48be6b2 | 2019-06-27 12:19:18 +0200 | [diff] [blame] | 25 | # Enable SERIRQ continuous |
| 26 | register "serirq_mode" = "SERIRQ_CONTINUOUS" |
| 27 | |
| 28 | register "tcc_offset" = "5" # TCC of 95C |
| 29 | |
| 30 | # FSP Configuration |
Michał Żygowski | 48be6b2 | 2019-06-27 12:19:18 +0200 | [diff] [blame] | 31 | register "SataSalpSupport" = "0" |
Michał Żygowski | 48be6b2 | 2019-06-27 12:19:18 +0200 | [diff] [blame] | 32 | register "DspEnable" = "0" |
| 33 | register "IoBufferOwnership" = "0" |
Michał Żygowski | 48be6b2 | 2019-06-27 12:19:18 +0200 | [diff] [blame] | 34 | register "SsicPortEnable" = "0" |
Michał Żygowski | 48be6b2 | 2019-06-27 12:19:18 +0200 | [diff] [blame] | 35 | register "ScsEmmcHs400Enabled" = "0" |
Michał Żygowski | 48be6b2 | 2019-06-27 12:19:18 +0200 | [diff] [blame] | 36 | register "SkipExtGfxScan" = "1" |
Michał Żygowski | 48be6b2 | 2019-06-27 12:19:18 +0200 | [diff] [blame] | 37 | register "SaGv" = "SaGv_Enabled" |
Michał Żygowski | 48be6b2 | 2019-06-27 12:19:18 +0200 | [diff] [blame] | 38 | register "IslVrCmd" = "2" |
| 39 | register "PmConfigSlpS3MinAssert" = "2" # 50ms |
| 40 | register "PmConfigSlpS4MinAssert" = "4" # 4s |
| 41 | register "PmConfigSlpSusMinAssert" = "1" # 500ms |
| 42 | register "PmConfigSlpAMinAssert" = "3" # 2s |
| 43 | |
Michał Żygowski | 48be6b2 | 2019-06-27 12:19:18 +0200 | [diff] [blame] | 44 | # VR Settings Configuration for 4 Domains |
| 45 | #+----------------+-------+-------+-------+-------+ |
| 46 | #| Domain/Setting | SA | IA | GTUS | GTS | |
| 47 | #+----------------+-------+-------+-------+-------+ |
| 48 | #| Psi1Threshold | 20A | 20A | 20A | 20A | |
| 49 | #| Psi2Threshold | 4A | 5A | 5A | 5A | |
| 50 | #| Psi3Threshold | 1A | 1A | 1A | 1A | |
| 51 | #| Psi3Enable | 1 | 1 | 1 | 1 | |
| 52 | #| Psi4Enable | 1 | 1 | 1 | 1 | |
| 53 | #| ImonSlope | 0 | 0 | 0 | 0 | |
| 54 | #| ImonOffset | 0 | 0 | 0 | 0 | |
| 55 | #| IccMax | 7A | 34A | 35A | 35A | |
| 56 | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | |
| 57 | #| AcLoadline(ohm)| 10.3m | 2.4m | 3.1m | 3.1m | |
| 58 | #| DcLoadline(ohm)| 10.3m | 2.4m | 3.1m | 3.1m | |
| 59 | #+----------------+-------+-------+-------+-------+ |
| 60 | #Note: IccMax settings are moved to SoC code |
| 61 | register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ |
| 62 | .vr_config_enable = 1, |
| 63 | .psi1threshold = VR_CFG_AMP(20), |
| 64 | .psi2threshold = VR_CFG_AMP(4), |
| 65 | .psi3threshold = VR_CFG_AMP(1), |
| 66 | .psi3enable = 1, |
| 67 | .psi4enable = 1, |
| 68 | .imon_slope = 0x0, |
| 69 | .imon_offset = 0x0, |
| 70 | .voltage_limit = 1520, |
| 71 | }" |
| 72 | |
| 73 | register "domain_vr_config[VR_IA_CORE]" = "{ |
| 74 | .vr_config_enable = 1, |
| 75 | .psi1threshold = VR_CFG_AMP(20), |
| 76 | .psi2threshold = VR_CFG_AMP(5), |
| 77 | .psi3threshold = VR_CFG_AMP(1), |
| 78 | .psi3enable = 1, |
| 79 | .psi4enable = 1, |
| 80 | .imon_slope = 0x0, |
| 81 | .imon_offset = 0x0, |
| 82 | .voltage_limit = 1520, |
| 83 | }" |
| 84 | |
| 85 | register "domain_vr_config[VR_GT_UNSLICED]" = "{ |
| 86 | .vr_config_enable = 1, |
| 87 | .psi1threshold = VR_CFG_AMP(20), |
| 88 | .psi2threshold = VR_CFG_AMP(5), |
| 89 | .psi3threshold = VR_CFG_AMP(1), |
| 90 | .psi3enable = 1, |
| 91 | .psi4enable = 1, |
| 92 | .imon_slope = 0x0, |
| 93 | .imon_offset = 0x0, |
| 94 | .voltage_limit = 1520, |
| 95 | }" |
| 96 | |
| 97 | register "domain_vr_config[VR_GT_SLICED]" = "{ |
| 98 | .vr_config_enable = 1, |
| 99 | .psi1threshold = VR_CFG_AMP(20), |
| 100 | .psi2threshold = VR_CFG_AMP(5), |
| 101 | .psi3threshold = VR_CFG_AMP(1), |
| 102 | .psi3enable = 1, |
| 103 | .psi4enable = 1, |
| 104 | .imon_slope = 0x0, |
| 105 | .imon_offset = 0x0, |
| 106 | .voltage_limit = 1520, |
| 107 | }" |
| 108 | |
| 109 | # Send an extra VR mailbox command for the PS4 exit issue |
| 110 | register "SendVrMbxCmd" = "2" |
| 111 | |
| 112 | # Enable SATA ports 1,2 |
| 113 | register "SataPortsEnable[0]" = "1" |
| 114 | register "SataPortsEnable[1]" = "1" |
| 115 | register "SataPortsEnable[2]" = "0" |
| 116 | register "SataPortsDevSlp[0]" = "0" |
| 117 | register "SataPortsDevSlp[1]" = "0" |
| 118 | |
| 119 | # Enable Root ports. 1-6 for LAN and Root Port 9 |
| 120 | register "PcieRpEnable[0]" = "1" |
| 121 | register "PcieRpEnable[1]" = "1" |
| 122 | register "PcieRpEnable[2]" = "1" |
| 123 | register "PcieRpEnable[3]" = "1" |
| 124 | register "PcieRpEnable[4]" = "1" |
| 125 | register "PcieRpEnable[5]" = "1" |
| 126 | register "PcieRpEnable[8]" = "1" # mPCIe WiFi |
| 127 | |
| 128 | # Enable Advanced Error Reporting for RP 1-6, 9 |
| 129 | register "PcieRpAdvancedErrorReporting[0]" = "1" |
| 130 | register "PcieRpAdvancedErrorReporting[1]" = "1" |
| 131 | register "PcieRpAdvancedErrorReporting[2]" = "1" |
| 132 | register "PcieRpAdvancedErrorReporting[3]" = "1" |
| 133 | register "PcieRpAdvancedErrorReporting[4]" = "1" |
| 134 | register "PcieRpAdvancedErrorReporting[5]" = "1" |
| 135 | register "PcieRpAdvancedErrorReporting[8]" = "1" |
| 136 | |
| 137 | # Enable Latency Tolerance Reporting Mechanism RP 1-6, 9 |
| 138 | register "PcieRpLtrEnable[0]" = "1" |
| 139 | register "PcieRpLtrEnable[1]" = "1" |
| 140 | register "PcieRpLtrEnable[2]" = "1" |
| 141 | register "PcieRpLtrEnable[3]" = "1" |
| 142 | register "PcieRpLtrEnable[4]" = "1" |
| 143 | register "PcieRpLtrEnable[5]" = "1" |
| 144 | register "PcieRpLtrEnable[8]" = "1" |
| 145 | |
| 146 | # Enable RP 9 CLKREQ# support |
| 147 | register "PcieRpClkReqSupport[8]" = "1" |
| 148 | # RP 9 uses CLKREQ0# |
| 149 | register "PcieRpClkReqNumber[8]" = "0" |
| 150 | |
| 151 | # Clocks 0-5 for RP 1-6 |
| 152 | register "PcieRpClkSrcNumber[0]" = "0" |
| 153 | register "PcieRpClkSrcNumber[1]" = "1" |
| 154 | register "PcieRpClkSrcNumber[2]" = "2" |
| 155 | register "PcieRpClkSrcNumber[3]" = "3" |
| 156 | register "PcieRpClkSrcNumber[4]" = "4" |
| 157 | register "PcieRpClkSrcNumber[5]" = "5" |
| 158 | # RP 9 shares CLKSRC5# with RP 6 |
| 159 | register "PcieRpClkSrcNumber[8]" = "5" |
| 160 | |
| 161 | |
| 162 | # USB 2.0 enable ports 1-8, disable ports 9-12 |
| 163 | register "usb2_ports[0]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port |
| 164 | register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port |
| 165 | register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port |
| 166 | register "usb2_ports[3]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port |
| 167 | register "usb2_ports[4]" = "USB2_PORT_SHORT(OC_SKIP)" # Type-A Port |
| 168 | register "usb2_ports[5]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port |
| 169 | register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port |
| 170 | register "usb2_ports[7]" = "USB2_PORT_SHORT(OC_SKIP)" # mPCIe slot |
Michał Żygowski | 48be6b2 | 2019-06-27 12:19:18 +0200 | [diff] [blame] | 171 | |
| 172 | # USB 3.0 enable ports 1-4, disable ports 5-6 |
| 173 | register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port |
| 174 | register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port |
| 175 | register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port |
| 176 | register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port |
Michał Żygowski | 48be6b2 | 2019-06-27 12:19:18 +0200 | [diff] [blame] | 177 | |
Felix Singer | 21b5a9a | 2023-10-23 07:26:28 +0200 | [diff] [blame] | 178 | register "SerialIoDevMode" = "{ |
| 179 | [PchSerialIoIndexI2C0] = PchSerialIoDisabled, |
| 180 | [PchSerialIoIndexI2C1] = PchSerialIoDisabled, |
| 181 | [PchSerialIoIndexI2C2] = PchSerialIoDisabled, |
| 182 | [PchSerialIoIndexI2C3] = PchSerialIoDisabled, |
| 183 | [PchSerialIoIndexI2C4] = PchSerialIoDisabled, |
| 184 | [PchSerialIoIndexI2C5] = PchSerialIoDisabled, |
| 185 | [PchSerialIoIndexSpi0] = PchSerialIoDisabled, |
| 186 | [PchSerialIoIndexSpi1] = PchSerialIoDisabled, |
| 187 | [PchSerialIoIndexUart0] = PchSerialIoDisabled, |
| 188 | [PchSerialIoIndexUart1] = PchSerialIoDisabled, |
| 189 | [PchSerialIoIndexUart2] = PchSerialIoDisabled, |
Michał Żygowski | 48be6b2 | 2019-06-27 12:19:18 +0200 | [diff] [blame] | 190 | }" |
| 191 | |
Michał Żygowski | 48be6b2 | 2019-06-27 12:19:18 +0200 | [diff] [blame] | 192 | device domain 0 on |
Felix Singer | 1f7510f | 2023-11-12 18:34:28 +0000 | [diff] [blame] | 193 | device ref igpu on end |
| 194 | device ref south_xhci on end |
| 195 | device ref heci1 on end |
| 196 | device ref sata on end |
| 197 | device ref pcie_rp1 on end |
| 198 | device ref pcie_rp2 on end |
| 199 | device ref pcie_rp3 on end |
| 200 | device ref pcie_rp4 on end |
| 201 | device ref pcie_rp5 on end |
| 202 | device ref pcie_rp6 on end |
| 203 | device ref pcie_rp9 on |
| 204 | # WIFI |
Michał Żygowski | 48be6b2 | 2019-06-27 12:19:18 +0200 | [diff] [blame] | 205 | smbios_slot_desc |
| 206 | "SlotTypePciExpressMini52pinWithoutBSKO" |
| 207 | "SlotLengthShort" "WIFI1" "SlotDataBusWidth1X" |
| 208 | end |
Felix Singer | 1f7510f | 2023-11-12 18:34:28 +0000 | [diff] [blame] | 209 | device ref lpc_espi on |
Michał Żygowski | 48be6b2 | 2019-06-27 12:19:18 +0200 | [diff] [blame] | 210 | chip superio/ite/it8772f |
Joel Linn | fb51661 | 2024-03-29 14:08:35 +0100 | [diff] [blame] | 211 | register "TMPIN1.mode" = "THERMAL_RESISTOR" |
| 212 | register "TMPIN2.mode" = "THERMAL_RESISTOR" |
| 213 | register "TMPIN3.mode" = "THERMAL_PECI" |
Michał Żygowski | 48be6b2 | 2019-06-27 12:19:18 +0200 | [diff] [blame] | 214 | # FAN2 available on fan header but unused |
| 215 | device pnp 2e.0 off end # FDC |
| 216 | device pnp 2e.1 on # Serial Port 1 |
| 217 | io 0x60 = 0x3f8 |
| 218 | irq 0x70 = 4 |
| 219 | end |
| 220 | device pnp 2e.4 on # Environment Controller |
| 221 | io 0x60 = 0xa40 |
| 222 | io 0x62 = 0xa30 |
| 223 | irq 0x70 = 9 |
| 224 | end |
| 225 | device pnp 2e.5 off end # Keyboard |
| 226 | device pnp 2e.6 off end # Mouse |
| 227 | device pnp 2e.7 off end # GPIO |
| 228 | device pnp 2e.a off end # IR |
| 229 | end |
Felix Singer | 1f7510f | 2023-11-12 18:34:28 +0000 | [diff] [blame] | 230 | end |
| 231 | device ref smbus on end |
Michał Żygowski | 48be6b2 | 2019-06-27 12:19:18 +0200 | [diff] [blame] | 232 | end |
Michał Żygowski | 7896b8c | 2020-06-19 17:15:51 +0200 | [diff] [blame] | 233 | chip drivers/crb |
| 234 | device mmio 0xfed40000 on end |
| 235 | end |
Michał Żygowski | 48be6b2 | 2019-06-27 12:19:18 +0200 | [diff] [blame] | 236 | end |