| commit | 7896b8ce59f88d7cd65bf7c9dfc3f9b1f9f2c640 | [log] [tgz] |
|---|---|---|
| author | Michał Żygowski <michal.zygowski@3mdeb.com> | Fri Jun 19 17:15:51 2020 +0200 |
| committer | Michał Żygowski <michal.zygowski@3mdeb.com> | Sun Jun 21 17:02:58 2020 +0000 |
| tree | ca2d75027e4857be97ab3d0087660215c47cfba6 | |
| parent | 08e8cab57841cd1e2cc47bb9899b16a531e1a1f5 [diff] [blame] |
mb/protectli/vault_kbl: Enable Intel PTT TEST=tweak PCR banks in SeaBIOS TPM menu, run tpm2_pcrlist in Linux Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I7c443a25ca7259df9c0a07615d0502f47d25792e Reviewed-on: https://review.coreboot.org/c/coreboot/+/42565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index d3e8b23..bb408a4 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb
@@ -305,4 +305,7 @@ device pci 1f.5 off end # PCH SPI device pci 1f.6 off end # GbE end + chip drivers/crb + device mmio 0xfed40000 on end + end end