Michał Żygowski | 48be6b2 | 2019-06-27 12:19:18 +0200 | [diff] [blame] | 1 | chip soc/intel/skylake |
| 2 | |
| 3 | # Enable deep Sx states |
| 4 | register "deep_s3_enable_ac" = "0" |
| 5 | register "deep_s3_enable_dc" = "0" |
| 6 | register "deep_s5_enable_ac" = "1" |
| 7 | register "deep_s5_enable_dc" = "1" |
| 8 | register "deep_sx_config" = "DSX_EN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD" |
Felix Singer | 743242b | 2023-06-16 01:33:25 +0200 | [diff] [blame] | 9 | register "s0ix_enable" = true |
Michał Żygowski | 48be6b2 | 2019-06-27 12:19:18 +0200 | [diff] [blame] | 10 | |
| 11 | register "gpe0_dw0" = "GPP_B" |
| 12 | register "gpe0_dw1" = "GPP_D" |
| 13 | register "gpe0_dw2" = "GPP_E" |
| 14 | |
| 15 | register "gen1_dec" = "0x00fc0201" |
| 16 | register "gen2_dec" = "0x007c0a01" |
| 17 | register "gen3_dec" = "0x000c03e1" |
| 18 | register "gen4_dec" = "0x001c02e1" |
| 19 | |
Michał Żygowski | 48be6b2 | 2019-06-27 12:19:18 +0200 | [diff] [blame] | 20 | register "eist_enable" = "1" |
| 21 | |
| 22 | # Disable DPTF |
| 23 | register "dptf_enable" = "0" |
| 24 | |
Michał Żygowski | 48be6b2 | 2019-06-27 12:19:18 +0200 | [diff] [blame] | 25 | # Enable SERIRQ continuous |
| 26 | register "serirq_mode" = "SERIRQ_CONTINUOUS" |
| 27 | |
| 28 | register "tcc_offset" = "5" # TCC of 95C |
| 29 | |
| 30 | # FSP Configuration |
Michał Żygowski | 48be6b2 | 2019-06-27 12:19:18 +0200 | [diff] [blame] | 31 | register "SataSalpSupport" = "0" |
Michał Żygowski | 48be6b2 | 2019-06-27 12:19:18 +0200 | [diff] [blame] | 32 | register "DspEnable" = "0" |
| 33 | register "IoBufferOwnership" = "0" |
Michał Żygowski | 48be6b2 | 2019-06-27 12:19:18 +0200 | [diff] [blame] | 34 | register "SsicPortEnable" = "0" |
Michał Żygowski | 48be6b2 | 2019-06-27 12:19:18 +0200 | [diff] [blame] | 35 | register "ScsEmmcHs400Enabled" = "0" |
Michał Żygowski | 48be6b2 | 2019-06-27 12:19:18 +0200 | [diff] [blame] | 36 | register "SkipExtGfxScan" = "1" |
Michał Żygowski | 48be6b2 | 2019-06-27 12:19:18 +0200 | [diff] [blame] | 37 | register "SaGv" = "SaGv_Enabled" |
Michał Żygowski | 48be6b2 | 2019-06-27 12:19:18 +0200 | [diff] [blame] | 38 | register "IslVrCmd" = "2" |
| 39 | register "PmConfigSlpS3MinAssert" = "2" # 50ms |
| 40 | register "PmConfigSlpS4MinAssert" = "4" # 4s |
| 41 | register "PmConfigSlpSusMinAssert" = "1" # 500ms |
| 42 | register "PmConfigSlpAMinAssert" = "3" # 2s |
| 43 | |
Michał Żygowski | 48be6b2 | 2019-06-27 12:19:18 +0200 | [diff] [blame] | 44 | # VR Settings Configuration for 4 Domains |
| 45 | #+----------------+-------+-------+-------+-------+ |
| 46 | #| Domain/Setting | SA | IA | GTUS | GTS | |
| 47 | #+----------------+-------+-------+-------+-------+ |
| 48 | #| Psi1Threshold | 20A | 20A | 20A | 20A | |
| 49 | #| Psi2Threshold | 4A | 5A | 5A | 5A | |
| 50 | #| Psi3Threshold | 1A | 1A | 1A | 1A | |
| 51 | #| Psi3Enable | 1 | 1 | 1 | 1 | |
| 52 | #| Psi4Enable | 1 | 1 | 1 | 1 | |
| 53 | #| ImonSlope | 0 | 0 | 0 | 0 | |
| 54 | #| ImonOffset | 0 | 0 | 0 | 0 | |
| 55 | #| IccMax | 7A | 34A | 35A | 35A | |
| 56 | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | |
| 57 | #| AcLoadline(ohm)| 10.3m | 2.4m | 3.1m | 3.1m | |
| 58 | #| DcLoadline(ohm)| 10.3m | 2.4m | 3.1m | 3.1m | |
| 59 | #+----------------+-------+-------+-------+-------+ |
| 60 | #Note: IccMax settings are moved to SoC code |
| 61 | register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ |
| 62 | .vr_config_enable = 1, |
| 63 | .psi1threshold = VR_CFG_AMP(20), |
| 64 | .psi2threshold = VR_CFG_AMP(4), |
| 65 | .psi3threshold = VR_CFG_AMP(1), |
| 66 | .psi3enable = 1, |
| 67 | .psi4enable = 1, |
| 68 | .imon_slope = 0x0, |
| 69 | .imon_offset = 0x0, |
| 70 | .voltage_limit = 1520, |
| 71 | }" |
| 72 | |
| 73 | register "domain_vr_config[VR_IA_CORE]" = "{ |
| 74 | .vr_config_enable = 1, |
| 75 | .psi1threshold = VR_CFG_AMP(20), |
| 76 | .psi2threshold = VR_CFG_AMP(5), |
| 77 | .psi3threshold = VR_CFG_AMP(1), |
| 78 | .psi3enable = 1, |
| 79 | .psi4enable = 1, |
| 80 | .imon_slope = 0x0, |
| 81 | .imon_offset = 0x0, |
| 82 | .voltage_limit = 1520, |
| 83 | }" |
| 84 | |
| 85 | register "domain_vr_config[VR_GT_UNSLICED]" = "{ |
| 86 | .vr_config_enable = 1, |
| 87 | .psi1threshold = VR_CFG_AMP(20), |
| 88 | .psi2threshold = VR_CFG_AMP(5), |
| 89 | .psi3threshold = VR_CFG_AMP(1), |
| 90 | .psi3enable = 1, |
| 91 | .psi4enable = 1, |
| 92 | .imon_slope = 0x0, |
| 93 | .imon_offset = 0x0, |
| 94 | .voltage_limit = 1520, |
| 95 | }" |
| 96 | |
| 97 | register "domain_vr_config[VR_GT_SLICED]" = "{ |
| 98 | .vr_config_enable = 1, |
| 99 | .psi1threshold = VR_CFG_AMP(20), |
| 100 | .psi2threshold = VR_CFG_AMP(5), |
| 101 | .psi3threshold = VR_CFG_AMP(1), |
| 102 | .psi3enable = 1, |
| 103 | .psi4enable = 1, |
| 104 | .imon_slope = 0x0, |
| 105 | .imon_offset = 0x0, |
| 106 | .voltage_limit = 1520, |
| 107 | }" |
| 108 | |
| 109 | # Send an extra VR mailbox command for the PS4 exit issue |
| 110 | register "SendVrMbxCmd" = "2" |
| 111 | |
| 112 | # Enable SATA ports 1,2 |
| 113 | register "SataPortsEnable[0]" = "1" |
| 114 | register "SataPortsEnable[1]" = "1" |
| 115 | register "SataPortsEnable[2]" = "0" |
| 116 | register "SataPortsDevSlp[0]" = "0" |
| 117 | register "SataPortsDevSlp[1]" = "0" |
| 118 | |
| 119 | # Enable Root ports. 1-6 for LAN and Root Port 9 |
| 120 | register "PcieRpEnable[0]" = "1" |
| 121 | register "PcieRpEnable[1]" = "1" |
| 122 | register "PcieRpEnable[2]" = "1" |
| 123 | register "PcieRpEnable[3]" = "1" |
| 124 | register "PcieRpEnable[4]" = "1" |
| 125 | register "PcieRpEnable[5]" = "1" |
| 126 | register "PcieRpEnable[8]" = "1" # mPCIe WiFi |
| 127 | |
| 128 | # Enable Advanced Error Reporting for RP 1-6, 9 |
| 129 | register "PcieRpAdvancedErrorReporting[0]" = "1" |
| 130 | register "PcieRpAdvancedErrorReporting[1]" = "1" |
| 131 | register "PcieRpAdvancedErrorReporting[2]" = "1" |
| 132 | register "PcieRpAdvancedErrorReporting[3]" = "1" |
| 133 | register "PcieRpAdvancedErrorReporting[4]" = "1" |
| 134 | register "PcieRpAdvancedErrorReporting[5]" = "1" |
| 135 | register "PcieRpAdvancedErrorReporting[8]" = "1" |
| 136 | |
| 137 | # Enable Latency Tolerance Reporting Mechanism RP 1-6, 9 |
| 138 | register "PcieRpLtrEnable[0]" = "1" |
| 139 | register "PcieRpLtrEnable[1]" = "1" |
| 140 | register "PcieRpLtrEnable[2]" = "1" |
| 141 | register "PcieRpLtrEnable[3]" = "1" |
| 142 | register "PcieRpLtrEnable[4]" = "1" |
| 143 | register "PcieRpLtrEnable[5]" = "1" |
| 144 | register "PcieRpLtrEnable[8]" = "1" |
| 145 | |
| 146 | # Enable RP 9 CLKREQ# support |
| 147 | register "PcieRpClkReqSupport[8]" = "1" |
| 148 | # RP 9 uses CLKREQ0# |
| 149 | register "PcieRpClkReqNumber[8]" = "0" |
| 150 | |
| 151 | # Clocks 0-5 for RP 1-6 |
| 152 | register "PcieRpClkSrcNumber[0]" = "0" |
| 153 | register "PcieRpClkSrcNumber[1]" = "1" |
| 154 | register "PcieRpClkSrcNumber[2]" = "2" |
| 155 | register "PcieRpClkSrcNumber[3]" = "3" |
| 156 | register "PcieRpClkSrcNumber[4]" = "4" |
| 157 | register "PcieRpClkSrcNumber[5]" = "5" |
| 158 | # RP 9 shares CLKSRC5# with RP 6 |
| 159 | register "PcieRpClkSrcNumber[8]" = "5" |
| 160 | |
| 161 | |
| 162 | # USB 2.0 enable ports 1-8, disable ports 9-12 |
| 163 | register "usb2_ports[0]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port |
| 164 | register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port |
| 165 | register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port |
| 166 | register "usb2_ports[3]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port |
| 167 | register "usb2_ports[4]" = "USB2_PORT_SHORT(OC_SKIP)" # Type-A Port |
| 168 | register "usb2_ports[5]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port |
| 169 | register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port |
| 170 | register "usb2_ports[7]" = "USB2_PORT_SHORT(OC_SKIP)" # mPCIe slot |
Michał Żygowski | 48be6b2 | 2019-06-27 12:19:18 +0200 | [diff] [blame] | 171 | |
| 172 | # USB 3.0 enable ports 1-4, disable ports 5-6 |
| 173 | register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port |
| 174 | register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port |
| 175 | register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port |
| 176 | register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port |
Michał Żygowski | 48be6b2 | 2019-06-27 12:19:18 +0200 | [diff] [blame] | 177 | |
Felix Singer | 21b5a9a | 2023-10-23 07:26:28 +0200 | [diff] [blame^] | 178 | register "SerialIoDevMode" = "{ |
| 179 | [PchSerialIoIndexI2C0] = PchSerialIoDisabled, |
| 180 | [PchSerialIoIndexI2C1] = PchSerialIoDisabled, |
| 181 | [PchSerialIoIndexI2C2] = PchSerialIoDisabled, |
| 182 | [PchSerialIoIndexI2C3] = PchSerialIoDisabled, |
| 183 | [PchSerialIoIndexI2C4] = PchSerialIoDisabled, |
| 184 | [PchSerialIoIndexI2C5] = PchSerialIoDisabled, |
| 185 | [PchSerialIoIndexSpi0] = PchSerialIoDisabled, |
| 186 | [PchSerialIoIndexSpi1] = PchSerialIoDisabled, |
| 187 | [PchSerialIoIndexUart0] = PchSerialIoDisabled, |
| 188 | [PchSerialIoIndexUart1] = PchSerialIoDisabled, |
| 189 | [PchSerialIoIndexUart2] = PchSerialIoDisabled, |
Michał Żygowski | 48be6b2 | 2019-06-27 12:19:18 +0200 | [diff] [blame] | 190 | }" |
| 191 | |
Arthur Heymans | 69cd729 | 2022-11-07 13:52:11 +0100 | [diff] [blame] | 192 | device cpu_cluster 0 on end |
Michał Żygowski | 48be6b2 | 2019-06-27 12:19:18 +0200 | [diff] [blame] | 193 | device domain 0 on |
| 194 | device pci 00.0 on end # Host Bridge |
| 195 | device pci 02.0 on end # Integrated Graphics Device |
Felix Singer | 9c1c009 | 2020-07-29 20:48:08 +0200 | [diff] [blame] | 196 | device pci 04.0 off end # SA thermal subsystem |
Felix Singer | 4d5c4e0 | 2020-07-29 22:28:37 +0200 | [diff] [blame] | 197 | device pci 05.0 off end # SA IMGU |
Michał Żygowski | 48be6b2 | 2019-06-27 12:19:18 +0200 | [diff] [blame] | 198 | device pci 08.0 off end # Gaussian Mixture Model |
| 199 | device pci 13.0 off end # Integrated Sensor Hub |
| 200 | device pci 14.0 on end # USB xHCI |
| 201 | device pci 14.1 off end # USB xDCI (OTG) |
| 202 | device pci 14.2 off end # Thermal Subsystem |
| 203 | device pci 14.3 off end # Camera I/O Host Controller |
| 204 | device pci 15.0 off end # I2C #0 |
| 205 | device pci 15.1 off end # I2C #1 |
| 206 | device pci 15.2 off end # I2C #2 |
| 207 | device pci 15.3 off end # I2C #3 |
| 208 | device pci 16.0 on end # Management Engine Interface 1 |
| 209 | device pci 16.1 off end # Management Engine Interface 2 |
| 210 | device pci 16.2 off end # Management Engine IDE-R |
| 211 | device pci 16.3 off end # Management Engine KT Redirection |
| 212 | device pci 16.4 off end # Management Engine Interface 3 |
| 213 | device pci 17.0 on end # SATA |
| 214 | device pci 19.0 off end # UART #2 |
| 215 | device pci 19.1 off end # I2C #5 |
| 216 | device pci 19.2 off end # I2C #4 |
| 217 | device pci 1c.0 on end # PCI Express Port 1 |
| 218 | device pci 1c.1 on end # PCI Express Port 2 |
| 219 | device pci 1c.2 on end # PCI Express Port 3 |
| 220 | device pci 1c.3 on end # PCI Express Port 4 |
| 221 | device pci 1c.4 on end # PCI Express Port 5 |
| 222 | device pci 1c.5 on end # PCI Express Port 6 |
| 223 | device pci 1c.6 off end # PCI Express Port 7 |
| 224 | device pci 1c.7 off end # PCI Express Port 8 |
| 225 | device pci 1d.0 on # PCI Express Port 9 - WiFi |
| 226 | smbios_slot_desc |
| 227 | "SlotTypePciExpressMini52pinWithoutBSKO" |
| 228 | "SlotLengthShort" "WIFI1" "SlotDataBusWidth1X" |
| 229 | end |
| 230 | device pci 1d.1 off end # PCI Express Port 10 |
| 231 | device pci 1d.2 off end # PCI Express Port 11 |
| 232 | device pci 1d.3 off end # PCI Express Port 12 |
| 233 | device pci 1e.0 off end # UART #0 |
| 234 | device pci 1e.1 off end # UART #1 |
| 235 | device pci 1e.2 off end # GSPI #0 |
| 236 | device pci 1e.3 off end # GSPI #1 |
| 237 | device pci 1e.4 off end # eMMC |
| 238 | device pci 1e.5 off end # SDIO |
| 239 | device pci 1e.6 off end # SDCard |
| 240 | device pci 1f.0 on |
| 241 | chip superio/ite/it8772f |
| 242 | register "peci_tmpin" = "3" |
| 243 | register "tmpin1_mode" = "THERMAL_RESISTOR" |
| 244 | register "tmpin2_mode" = "THERMAL_RESISTOR" |
| 245 | # FAN2 available on fan header but unused |
| 246 | device pnp 2e.0 off end # FDC |
| 247 | device pnp 2e.1 on # Serial Port 1 |
| 248 | io 0x60 = 0x3f8 |
| 249 | irq 0x70 = 4 |
| 250 | end |
| 251 | device pnp 2e.4 on # Environment Controller |
| 252 | io 0x60 = 0xa40 |
| 253 | io 0x62 = 0xa30 |
| 254 | irq 0x70 = 9 |
| 255 | end |
| 256 | device pnp 2e.5 off end # Keyboard |
| 257 | device pnp 2e.6 off end # Mouse |
| 258 | device pnp 2e.7 off end # GPIO |
| 259 | device pnp 2e.a off end # IR |
| 260 | end |
| 261 | end # LPC Interface |
| 262 | device pci 1f.1 on end # P2SB |
| 263 | device pci 1f.2 on end # Power Management Controller |
| 264 | device pci 1f.3 off end # Intel HDA |
| 265 | device pci 1f.4 on end # SMBus |
| 266 | device pci 1f.5 off end # PCH SPI |
| 267 | device pci 1f.6 off end # GbE |
| 268 | end |
Michał Żygowski | 7896b8c | 2020-06-19 17:15:51 +0200 | [diff] [blame] | 269 | chip drivers/crb |
| 270 | device mmio 0xfed40000 on end |
| 271 | end |
Michał Żygowski | 48be6b2 | 2019-06-27 12:19:18 +0200 | [diff] [blame] | 272 | end |