Kyösti Mälkki | 7b73e852 | 2022-11-08 04:43:41 +0000 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
Kyösti Mälkki | 7b73e852 | 2022-11-08 04:43:41 +0000 | [diff] [blame] | 3 | #ifndef I82801DX_H |
| 4 | #define I82801DX_H |
| 5 | |
| 6 | #include <acpi/acpi.h> |
Kyösti Mälkki | 7b73e852 | 2022-11-08 04:43:41 +0000 | [diff] [blame] | 7 | #include <device/device.h> |
| 8 | |
| 9 | void i82801dx_enable(struct device *dev); |
| 10 | void i82801dx_early_init(void); |
Kyösti Mälkki | 8e679f7 | 2022-11-14 10:05:06 +0200 | [diff] [blame] | 11 | void i82801dx_lpc_setup(void); |
Kyösti Mälkki | 7b73e852 | 2022-11-08 04:43:41 +0000 | [diff] [blame] | 12 | |
Kyösti Mälkki | 7b73e852 | 2022-11-08 04:43:41 +0000 | [diff] [blame] | 13 | #define MAINBOARD_POWER_OFF 0 |
| 14 | #define MAINBOARD_POWER_ON 1 |
| 15 | #define MAINBOARD_POWER_KEEP 2 |
| 16 | |
| 17 | /* |
| 18 | * 000 = Non-combined. P0 is primary master. P1 is secondary master. |
| 19 | * 001 = Non-combined. P0 is secondary master. P1 is primary master. |
| 20 | * 100 = Combined. P0 is primary master. P1 is primary slave. IDE is secondary; |
| 21 | * Primary IDE channel disabled. |
| 22 | * 101 = Combined. P0 is primary slave. P1 is primary master. IDE is secondary. |
| 23 | * 110 = Combined. IDE is primary. P0 is secondary master. P1 is secondary |
| 24 | * slave; Secondary IDE channel disabled. |
| 25 | * 111 = Combined. IDE is primary. P0 is secondary slave. P1 is secondary master. |
| 26 | */ |
| 27 | /* PCI Configuration Space (D31:F1) */ |
| 28 | #define IDE_TIM_PRI 0x40 /* IDE timings, primary */ |
| 29 | #define IDE_TIM_SEC 0x42 /* IDE timings, secondary */ |
| 30 | |
| 31 | /* IDE_TIM bits */ |
| 32 | #define IDE_DECODE_ENABLE (1 << 15) |
| 33 | |
| 34 | #define PCI_DMA_CFG 0x90 |
| 35 | #define SERIRQ_CNTL 0x64 |
| 36 | #define GEN_CNTL 0xd0 |
| 37 | #define GEN_STS 0xd4 |
| 38 | #define RTC_CONF 0xd8 |
| 39 | #define GEN_PMCON_3 0xa4 |
| 40 | |
| 41 | #define PCICMD 0x04 |
| 42 | #define PMBASE 0x40 |
Kyösti Mälkki | 8e679f7 | 2022-11-14 10:05:06 +0200 | [diff] [blame] | 43 | #define DEFAULT_PMBASE 0x0400 |
Kyösti Mälkki | 7b73e852 | 2022-11-08 04:43:41 +0000 | [diff] [blame] | 44 | #define ACPI_CNTL 0x44 |
| 45 | #define ACPI_EN (1 << 4) |
| 46 | #define BIOS_CNTL 0x4E |
| 47 | #define GPIO_BASE 0x58 |
| 48 | #define GPIO_CNTL 0x5C |
| 49 | #define GPIOBASE_ADDR 0x0500 |
| 50 | #define PIRQA_ROUT 0x60 |
| 51 | #define PIRQB_ROUT 0x61 |
| 52 | #define PIRQC_ROUT 0x62 |
| 53 | #define PIRQD_ROUT 0x63 |
| 54 | #define PIRQE_ROUT 0x68 |
| 55 | #define PIRQF_ROUT 0x69 |
| 56 | #define PIRQG_ROUT 0x6A |
| 57 | #define PIRQH_ROUT 0x6B |
| 58 | #define COM_DEC 0xE0 |
Kyösti Mälkki | 458751c | 2019-12-19 06:45:56 +0200 | [diff] [blame] | 59 | #define GEN1_DEC 0xE4 |
Kyösti Mälkki | 7b73e852 | 2022-11-08 04:43:41 +0000 | [diff] [blame] | 60 | #define LPC_EN 0xE6 |
| 61 | #define FUNC_DIS 0xF2 |
| 62 | |
| 63 | /* 1e f0 244e */ |
| 64 | |
| 65 | #define CMD 0x04 |
| 66 | #define SBUS_NUM 0x19 |
| 67 | #define SUB_BUS_NUM 0x1A |
| 68 | #define SMLT 0x1B |
| 69 | #define IOBASE 0x1C |
| 70 | #define IOLIM 0x1D |
| 71 | #define MEMBASE 0x20 |
| 72 | #define MEMLIM 0x22 |
| 73 | #define CNF 0x50 |
| 74 | #define MTT 0x70 |
| 75 | #define PCI_MAST_STS 0x82 |
| 76 | |
| 77 | #define RTC_FAILED (1 << 2) |
| 78 | |
| 79 | #define PM1_STS 0x00 |
| 80 | #define WAK_STS (1 << 15) |
| 81 | #define PCIEXPWAK_STS (1 << 14) |
| 82 | #define PRBTNOR_STS (1 << 11) |
| 83 | #define RTC_STS (1 << 10) |
| 84 | #define PWRBTN_STS (1 << 8) |
| 85 | #define GBL_STS (1 << 5) |
| 86 | #define BM_STS (1 << 4) |
| 87 | #define TMROF_STS (1 << 0) |
| 88 | #define PM1_EN 0x02 |
| 89 | #define PCIEXPWAK_DIS (1 << 14) |
| 90 | #define RTC_EN (1 << 10) |
| 91 | #define PWRBTN_EN (1 << 8) |
| 92 | #define GBL_EN (1 << 5) |
| 93 | #define TMROF_EN (1 << 0) |
| 94 | #define PM1_CNT 0x04 |
| 95 | #define GBL_RLS (1 << 2) |
| 96 | #define BM_RLD (1 << 1) |
| 97 | #define SCI_EN (1 << 0) |
| 98 | #define PM1_TMR 0x08 |
| 99 | #define PROC_CNT 0x10 |
| 100 | #define LV2 0x14 |
Kyösti Mälkki | 7b73e852 | 2022-11-08 04:43:41 +0000 | [diff] [blame] | 101 | #define GPE0_STS 0x28 |
| 102 | #define PME_B0_STS (1 << 13) |
| 103 | #define USB3_STS (1 << 12) |
| 104 | #define PME_STS (1 << 11) |
| 105 | #define BATLOW_STS (1 << 10) |
| 106 | #define GST_STS (1 << 9) |
| 107 | #define RI_STS (1 << 8) |
| 108 | #define SMB_WAK_STS (1 << 7) |
| 109 | #define TCOSCI_STS (1 << 6) |
| 110 | #define AC97_STS (1 << 5) |
| 111 | #define USB2_STS (1 << 4) |
| 112 | #define USB1_STS (1 << 3) |
| 113 | #define SWGPE_STS (1 << 2) |
| 114 | #define HOT_PLUG_STS (1 << 1) |
| 115 | #define THRM_STS (1 << 0) |
| 116 | #define GPE0_EN 0x2c |
| 117 | #define PME_B0_EN (1 << 13) |
| 118 | #define PME_EN (1 << 11) |
| 119 | #define SMI_EN 0x30 |
| 120 | #define EL_SMI_EN (1 << 25) // Intel Quick Resume Technology |
| 121 | #define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic |
| 122 | #define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic |
| 123 | #define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS |
| 124 | #define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al) |
| 125 | #define MCSMI_EN (1 << 11) // Trap microcontroller range access |
| 126 | #define BIOS_RLS (1 << 7) // asserts SCI on bit set |
| 127 | #define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set |
| 128 | #define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI# |
| 129 | #define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI# |
| 130 | #define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic |
| 131 | #define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit |
| 132 | #define EOS (1 << 1) // End of SMI (deassert SMI#) |
| 133 | #define GBL_SMI_EN (1 << 0) // SMI# generation at all? |
| 134 | #define SMI_STS 0x34 |
| 135 | #define ALT_GP_SMI_EN 0x38 |
| 136 | #define ALT_GP_SMI_STS 0x3a |
| 137 | #define GPE_CNTL 0x42 |
| 138 | #define DEVACT_STS 0x44 |
| 139 | #define SS_CNT 0x50 |
Kyösti Mälkki | 7b73e852 | 2022-11-08 04:43:41 +0000 | [diff] [blame] | 140 | |
Kyösti Mälkki | e8a3af1 | 2022-11-19 18:39:22 +0200 | [diff] [blame] | 141 | #if CONFIG(TCO_SPACE_NOT_YET_SPLIT) |
Kyösti Mälkki | 560c3f5 | 2022-01-18 04:25:48 +0200 | [diff] [blame] | 142 | /* TCO1 Control Register */ |
| 143 | #define TCO1_CNT 0x68 |
Kyösti Mälkki | e8a3af1 | 2022-11-19 18:39:22 +0200 | [diff] [blame] | 144 | #endif |
Kyösti Mälkki | 7b73e852 | 2022-11-08 04:43:41 +0000 | [diff] [blame] | 145 | |
| 146 | #define GEN_PMCON_1 0xa0 |
| 147 | #define GEN_PMCON_2 0xa2 |
| 148 | #define GEN_PMCON_3 0xa4 |
| 149 | |
| 150 | /* GEN_PMCON_3 bits */ |
| 151 | #define RTC_BATTERY_DEAD (1 << 2) |
| 152 | #define RTC_POWER_FAILED (1 << 1) |
| 153 | #define SLEEP_AFTER_POWER_FAIL (1 << 0) |
| 154 | |
| 155 | #endif /* I82801DX_H */ |