| commit | 458751c2d5b5ebfdaa4397be44b2ac6a7fd9c8dc | [log] [tgz] |
|---|---|---|
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | Thu Dec 19 06:45:56 2019 +0200 |
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | Fri Nov 11 12:42:34 2022 +0000 |
| tree | 48377137abfcf0b7760497e442e27ca9373499d9 | |
| parent | a83c502d5a0a889b9ccd9ed053bad5b3060a4314 [diff] [blame] |
aopen/dxplplusu: Add early GPIO settings Required for 2nd COM port to work. Change-Id: Ib211e9c4b487fadec3d3487f9d745f44d8ca4579 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52815 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h index e63327c..c07e581 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.h +++ b/src/southbridge/intel/i82801dx/i82801dx.h
@@ -71,6 +71,7 @@ #define PIRQG_ROUT 0x6A #define PIRQH_ROUT 0x6B #define COM_DEC 0xE0 +#define GEN1_DEC 0xE4 #define LPC_EN 0xE6 #define FUNC_DIS 0xF2