sb/intel/i82801dx: Improve LPC device early init
Make the implementation more similar to i82801gx, enabling
ACPI PM and GPIO register spaces already in bootblock.
Change-Id: I41ad8622801dbbadafdc37359d521eed42256e63
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h
index 7946bd5..ecb9924 100644
--- a/src/southbridge/intel/i82801dx/i82801dx.h
+++ b/src/southbridge/intel/i82801dx/i82801dx.h
@@ -1,26 +1,14 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* the problem: we have 82801dbm support in fb1, and 82801er in fb2.
- * fb1 code is what we want, fb2 structure is needed however.
- * so we need to get fb1 code for 82801dbm into fb2 structure.
- */
-/* What I did: took the 80801er stuff from fb2, verify it against the
- * db stuff in fb1, and made sure it was right.
- */
-
#ifndef I82801DX_H
#define I82801DX_H
#include <acpi/acpi.h>
-
-#if !defined(__ASSEMBLER__)
-
#include <device/device.h>
void i82801dx_enable(struct device *dev);
void i82801dx_early_init(void);
-
-#endif
+void i82801dx_lpc_setup(void);
#define DEBUG_PERIODIC_SMIS 0
@@ -54,8 +42,7 @@
#define PCICMD 0x04
#define PMBASE 0x40
-#define PMBASE_ADDR 0x0400
-#define DEFAULT_PMBASE PMBASE_ADDR
+#define DEFAULT_PMBASE 0x0400
#define ACPI_CNTL 0x44
#define ACPI_EN (1 << 4)
#define BIOS_CNTL 0x4E