Blame - src/southbridge/amd/pi/hudson/pci_devs.h - coreboot

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Angel Pons	182dbde	2020-04-02 23:49:05 +0200	[diff] [blame]	1	/* SPDX-License-Identifier: GPL-2.0-only */
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	2
				3	#ifndef _PI_HUDSON_PCI_DEVS_H_
				4	#define _PI_HUDSON_PCI_DEVS_H_
				5
Elyes HAOUAS	8ccc8fd	2020-10-01 10:59:56 +0200	[diff] [blame]	6	#include <device/pci_def.h>
				7
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	8	/* XHCI */
Marshall Dawson	c1f3233	2017-04-21 13:54:08 -0600	[diff] [blame]	9	#define XHCI_DEV 0x10
				10	#define XHCI_FUNC 0
Elyes HAOUAS	8ccc8fd	2020-10-01 10:59:56 +0200	[diff] [blame]	11	#define XHCI_DEVFN PCI_DEVFN(XHCI_DEV, XHCI_FUNC)
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	12
Marshall Dawson	c1f3233	2017-04-21 13:54:08 -0600	[diff] [blame]	13	#define XHCI2_DEV 0x10
				14	#define XHCI2_FUNC 1
Elyes HAOUAS	8ccc8fd	2020-10-01 10:59:56 +0200	[diff] [blame]	15	#define XHCI2_DEVFN PCI_DEVFN(XHCI2_DEV, XHCI2_FUNC)
Dave Frodin	9cfa742	2015-01-27 07:19:48 -0700	[diff] [blame]	16
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	17	/* SATA */
Marshall Dawson	c1f3233	2017-04-21 13:54:08 -0600	[diff] [blame]	18	#define SATA_DEV 0x11
				19	#define SATA_FUNC 0
				20	#define SATA_IDE_DEVID 0x7800
				21	#define AHCI_DEVID_MS 0x7801
				22	#define AHCI_DEVID_AMD 0x7804
Elyes HAOUAS	8ccc8fd	2020-10-01 10:59:56 +0200	[diff] [blame]	23	#define SATA_DEVFN PCI_DEVFN(SATA_DEV, SATA_FUNC)
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	24
				25	/* OHCI */
Marshall Dawson	c1f3233	2017-04-21 13:54:08 -0600	[diff] [blame]	26	#define OHCI1_DEV 0x12
				27	#define OHCI1_FUNC 0
				28	#define OHCI2_DEV 0x13
				29	#define OHCI2_FUNC 0
				30	#define OHCI3_DEV 0x16
				31	#define OHCI3_FUNC 0
				32	#define OHCI4_DEV 0x14
				33	#define OHCI4_FUNC 5
Elyes HAOUAS	8ccc8fd	2020-10-01 10:59:56 +0200	[diff] [blame]	34	#define OHCI1_DEVFN PCI_DEVFN(OHCI1_DEV, OHCI1_FUNC)
				35	#define OHCI2_DEVFN PCI_DEVFN(OHCI2_DEV, OHCI2_FUNC)
				36	#define OHCI3_DEVFN PCI_DEVFN(OHCI3_DEV, OHCI3_FUNC)
				37	#define OHCI4_DEVFN PCI_DEVFN(OHCI4_DEV, OHCI4_FUNC)
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	38
				39	/* EHCI */
Marshall Dawson	c1f3233	2017-04-21 13:54:08 -0600	[diff] [blame]	40	#define EHCI1_DEV 0x12
				41	#define EHCI1_FUNC 2
				42	#define EHCI2_DEV 0x13
				43	#define EHCI2_FUNC 2
				44	#define EHCI3_DEV 0x16
				45	#define EHCI3_FUNC 2
Elyes HAOUAS	8ccc8fd	2020-10-01 10:59:56 +0200	[diff] [blame]	46	#define EHCI1_DEVFN PCI_DEVFN(EHCI1_DEV, EHCI1_FUNC)
				47	#define EHCI2_DEVFN PCI_DEVFN(EHCI2_DEV, EHCI2_FUNC)
				48	#define EHCI3_DEVFN PCI_DEVFN(EHCI3_DEV, EHCI3_FUNC)
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	49
				50	/* SMBUS */
Marshall Dawson	c1f3233	2017-04-21 13:54:08 -0600	[diff] [blame]	51	#define SMBUS_DEV 0x14
				52	#define SMBUS_FUNC 0
Elyes HAOUAS	8ccc8fd	2020-10-01 10:59:56 +0200	[diff] [blame]	53	#define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC)
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	54
				55	/* HD Audio */
Marshall Dawson	c1f3233	2017-04-21 13:54:08 -0600	[diff] [blame]	56	#define HDA_DEV 0x14
				57	#define HDA_FUNC 2
Elyes HAOUAS	8ccc8fd	2020-10-01 10:59:56 +0200	[diff] [blame]	58	#define HDA_DEVFN PCI_DEVFN(HDA_DEV, HDA_FUNC)
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	59
				60	/* LPC BUS */
Marshall Dawson	c1f3233	2017-04-21 13:54:08 -0600	[diff] [blame]	61	#define PCU_DEV 0x14
Philipp Deppenwiese	3067012	2017-03-01 02:24:33 +0100	[diff] [blame]	62	#define LPC_DEV PCU_DEV
Marshall Dawson	c1f3233	2017-04-21 13:54:08 -0600	[diff] [blame]	63	#define LPC_FUNC 3
Elyes HAOUAS	8ccc8fd	2020-10-01 10:59:56 +0200	[diff] [blame]	64	#define LPC_DEVFN PCI_DEVFN(LPC_DEV, LPC_FUNC)
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	65
				66	/* PCI Ports */
Marshall Dawson	c1f3233	2017-04-21 13:54:08 -0600	[diff] [blame]	67	#define SB_PCI_PORT_DEV 0x14
				68	#define SB_PCI_PORT_FUNC 4
Elyes HAOUAS	8ccc8fd	2020-10-01 10:59:56 +0200	[diff] [blame]	69	#define SB_PCI_PORT_DEVFN PCI_DEVFN(SB_PCI_PORT_DEV, SB_PCI_PORT_FUNC)
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	70
				71	/* SD Controller */
Marshall Dawson	c1f3233	2017-04-21 13:54:08 -0600	[diff] [blame]	72	#define SD_DEV 0x14
				73	#define SD_FUNC 7
Elyes HAOUAS	8ccc8fd	2020-10-01 10:59:56 +0200	[diff] [blame]	74	#define SD_DEVFN PCI_DEVFN(SD_DEV, SD_FUNC)
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	75
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	76	#endif /* _PI_HUDSON_PCI_DEVS_H_ */