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review.coreboot.org / coreboot / bfb11bec3b3fec638adf864a9b9b2cff6671fed8 / . / src / soc / intel / alderlake / vr_config.c
blob: 3467bdd13914fe52f2316635d5942acdcc0af410 [file] [log] [blame]
V Sowmyac6d71662021-07-15 08:11:08 +0530[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
2
3#include <device/pci_ids.h>
4#include <device/pci_ops.h>
5#include <fsp/api.h>
6#include <soc/ramstage.h>
7#include <soc/vr_config.h>
8#include <console/console.h>
9#include <intelblocks/cpulib.h>
10
11/*
12 * VR Configurations for IA and GT domains for ADL-P SKU's.
Curtis Chen150fee62021-12-21 11:51:33 +0800[diff] [blame]13 * Per doc#627345 ADL_P Partial Intel PlatformDesignStudio Rev 2.0.0, update PD
V Sowmyac6d71662021-07-15 08:11:08 +0530[diff] [blame]14 *
15 * +----------------+-----------+-------+-------+---------+-------------+----------+
16 * | SKU | Setting | AC LL | DC LL | ICC MAX | TDC Current | TDC Time |
17 * | | |(mOhms)|(mOhms)| (A) | (A) | (msec) |
18 * +----------------+-----------+-------+-------+---------+-------------+----------+
19 * | ADL-P 682(45W) | IA | 2.3 | 2.3 | 160 | 57 | 28000 |
20 * + +-----------+-------+-------+---------+-------------+----------+
Curtis Chen150fee62021-12-21 11:51:33 +0800[diff] [blame]21 * | | GT | 3.2 | 3.2 | 55 | 57 | 28000 |
V Sowmyac6d71662021-07-15 08:11:08 +0530[diff] [blame]22 * +----------------+-----------+-------+-------+---------+-------------+----------+
Curtis Chen150fee62021-12-21 11:51:33 +0800[diff] [blame]23 * | ADL-P 482(45W) | IA | 2.3 | 2.3 | 120 | 47 | 28000 |
24 * + 442(45W) +-----------+-------+-------+---------+-------------+----------+
25 * | | GT | 3.2 | 3.2 | 55 | 47 | 28000 |
26 * +----------------+-----------+-------+-------+---------+-------------+----------+
27 * | ADL-P 682(28W) | IA | 2.3 | 2.3 | 109 | 40 | 28000 |
V Sowmyac6d71662021-07-15 08:11:08 +0530[diff] [blame]28 * + +-----------+-------+-------+---------+-------------+----------+
Curtis Chen150fee62021-12-21 11:51:33 +0800[diff] [blame]29 * | | GT | 3.2 | 3.2 | 55 | 40 | 28000 |
30 * +----------------+-----------+-------+-------+---------+-------------+----------+
31 * | ADL-P 482(28W) | IA | 2.3 | 2.3 | 85 | 32 | 28000 |
Patrick Rudolph4f37cf02023-03-15 15:32:26 +0100[diff] [blame]32 * + 442(28W) +-----------+-------+-------+---------+-------------+----------+
Curtis Chen150fee62021-12-21 11:51:33 +0800[diff] [blame]33 * | | GT | 3.2 | 3.2 | 55 | 32 | 28000 |
V Sowmyac6d71662021-07-15 08:11:08 +0530[diff] [blame]34 * +----------------+-----------+-------+-------+---------+-------------+----------+
35 * | ADL-P 282(15W) | IA | 2.8 | 2.8 | 80 | 20 | 28000 |
36 * + +-----------+-------+-------+---------+-------------+----------+
37 * | | GT | 3.2 | 3.2 | 40 | 20 | 28000 |
38 * +----------------+-----------+-------+-------+---------+-------------+----------+
39 */
40
V Sowmya7de81d52022-04-05 14:45:36 +0530[diff] [blame]41/*
42 * VR Configurations for IA and GT domains for ADL-N SKU's.
43 * Per doc#646929 ADL N Platform Design Guide -> Power_Map_Rev1p0
44 *
45 * +----------------+-----------+-------+-------+---------+-------------+----------+
46 * | SKU | Setting | AC LL | DC LL | ICC MAX | TDC Current | TDC Time |
47 * | | |(mOhms)|(mOhms)| (A) | (A) | (msec) |
48 * +----------------+-----------+-------+-------+---------+-------------+----------+
49 * | ADL-N 081(15W) | IA | 4.7 | 4.7 | 53 | 22 | 28000 |
50 * + +-----------+-------+-------+---------+-------------+----------+
51 * | | GT | 6.5 | 6.5 | 29 | 22 | 28000 |
52 * +----------------+-----------+-------+-------+---------+-------------+----------+
53 * | ADL-N 081(7W) | IA | 5.0 | 5.0 | 37 | 14 | 28000 |
54 * + +-----------+-------+-------+---------+-------------+----------+
55 * | | GT | 6.5 | 6.5 | 29 | 14 | 28000 |
56 * +----------------+-----------+-------+-------+---------+-------------+----------+
57 * | ADL-N 041(6W) | IA | 5.0 | 5.0 | 37 | 12 | 28000 |
58 * + Pentium +-----------+-------+-------+---------+-------------+----------+
59 * | | GT | 6.5 | 6.5 | 29 | 12 | 28000 |
60 * +----------------+-----------+-------+-------+---------+-------------+----------+
61 * | ADL-N 041(6W) | IA | 5.0 | 5.0 | 37 | 12 | 28000 |
62 * + Celeron +-----------+-------+-------+---------+-------------+----------+
63 * | | GT | 6.5 | 6.5 | 26 | 12 | 28000 |
64 * +----------------+-----------+-------+-------+---------+-------------+----------+
65 * | ADL-N 021(6W) | IA | 5.0 | 5.0 | 27 | 10 | 28000 |
66 * + +-----------+-------+-------+---------+-------------+----------+
67 * | | GT | 6.5 | 6.5 | 23 | 10 | 28000 |
68 * +----------------+-----------+-------+-------+---------+-------------+----------+
69 */
70
Jeremy Compostella1b44c812022-06-17 15:18:02 -0700[diff] [blame]71/*
72 * VR Configurations for IA and GT domains for RPL-P SKU's.
73 * Per doc#686872 RPL UPH PDG - 2022, June 7th edition
74 *
75 * +----------------+-----------+-------+-------+---------+-------------+----------+
76 * | SKU | Setting | AC LL | DC LL | ICC MAX | TDC Current | TDC Time |
77 * | | |(mOhms)|(mOhms)| (A) | (A) | (msec) |
78 * +----------------+-----------+-------+-------+---------+-------------+----------+
79 * | RPL-P 682(45W) | IA | 2.3 | 2.3 | 160 | 86 | 28000 |
80 * + +-----------+-------+-------+---------+-------------+----------+
81 * | | GT | 3.2 | 3.2 | 55 | 86 | 28000 |
82 * +----------------+-----------+-------+-------+---------+-------------+----------+
Jeremy Compostella0973c322023-03-27 11:57:41 -0700[diff] [blame]83 * | RPL-P 482(28W) | IA | 2.3 | 2.3 | 102 | 33 | 28000 |
Jeremy Compostella1b44c812022-06-17 15:18:02 -0700[diff] [blame]84 * + +-----------+-------+-------+---------+-------------+----------+
Jeremy Compostella0973c322023-03-27 11:57:41 -0700[diff] [blame]85 * | | GT | 3.2 | 3.2 | 55 | 33 | 28000 |
Jeremy Compostella1b44c812022-06-17 15:18:02 -0700[diff] [blame]86 * +----------------+-----------+-------+-------+---------+-------------+----------+
Jeremy Compostella0973c322023-03-27 11:57:41 -0700[diff] [blame]87 * | RPL-P 282(15W) | IA | 2.8 | 2.8 | 80 | 22 | 28000 |
Jeremy Compostella1b44c812022-06-17 15:18:02 -0700[diff] [blame]88 * + +-----------+-------+-------+---------+-------------+----------+
Jeremy Compostella0973c322023-03-27 11:57:41 -0700[diff] [blame]89 * | | GT | 3.2 | 3.2 | 40 | 22 | 28000 |
Jeremy Compostella1b44c812022-06-17 15:18:02 -0700[diff] [blame]90 * +----------------+-----------+-------+-------+---------+-------------+----------+
91 */
92
V Sowmyac6d71662021-07-15 08:11:08 +0530[diff] [blame]93struct vr_lookup {
94 uint16_t mchid;
Curtis Chenea1bb5f2021-11-25 13:17:42 +0800[diff] [blame]95 uint8_t tdp;
V Sowmyac6d71662021-07-15 08:11:08 +0530[diff] [blame]96 uint32_t conf[NUM_VR_DOMAINS];
97};
98
99static uint32_t load_table(const struct vr_lookup *tbl, const int tbl_entries, const int domain,
Curtis Chenea1bb5f2021-11-25 13:17:42 +0800[diff] [blame]100 const uint16_t mch_id, uint8_t tdp)
V Sowmyac6d71662021-07-15 08:11:08 +0530[diff] [blame]101{
102 for (size_t i = 0; i < tbl_entries; i++) {
Curtis Chenea1bb5f2021-11-25 13:17:42 +0800[diff] [blame]103 if (tbl[i].mchid != mch_id || tbl[i].tdp != tdp)
V Sowmyac6d71662021-07-15 08:11:08 +0530[diff] [blame]104 continue;
105 return tbl[i].conf[domain];
106 }
107
Julius Wernere9665952022-01-21 17:06:20 -0800[diff] [blame]108 printk(BIOS_ERR, "Unknown MCH (0x%x) in %s\n", mch_id, __func__);
V Sowmyac6d71662021-07-15 08:11:08 +0530[diff] [blame]109 return 0;
110}
111
Curtis Chen1f8563e2021-11-30 14:04:48 +0800[diff] [blame]112/* Per the power map from #613643, update ADL-P 6+8+2 (28W) VR configuration */
V Sowmyac6d71662021-07-15 08:11:08 +0530[diff] [blame]113static const struct vr_lookup vr_config_ll[] = {
Felix Singer43b7f412022-03-07 04:34:52 +0100[diff] [blame]114 { PCI_DID_INTEL_ADL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
115 { PCI_DID_INTEL_ADL_P_ID_3, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
116 { PCI_DID_INTEL_ADL_P_ID_4, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
117 { PCI_DID_INTEL_ADL_P_ID_5, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
Patrick Rudolph4f37cf02023-03-15 15:32:26 +0100[diff] [blame]118 { PCI_DID_INTEL_ADL_P_ID_1, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
Felix Singer43b7f412022-03-07 04:34:52 +0100[diff] [blame]119 { PCI_DID_INTEL_ADL_P_ID_3, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
120 { PCI_DID_INTEL_ADL_P_ID_5, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
121 { PCI_DID_INTEL_ADL_P_ID_7, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
122 { PCI_DID_INTEL_ADL_P_ID_6, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) },
123 { PCI_DID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) },
124 { PCI_DID_INTEL_ADL_P_ID_10, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) },
V Sowmya7de81d52022-04-05 14:45:36 +0530[diff] [blame]125 { PCI_DID_INTEL_ADL_N_ID_1, 15, VR_CFG_ALL_DOMAINS_LOADLINE(4.7, 6.5) },
126 { PCI_DID_INTEL_ADL_N_ID_1, 7, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) },
127 { PCI_DID_INTEL_ADL_N_ID_2, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) },
128 { PCI_DID_INTEL_ADL_N_ID_3, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) },
129 { PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) },
Jeremy Compostella1b44c812022-06-17 15:18:02 -0700[diff] [blame]130 { PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
131 { PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
Tim Crawford198c6292023-06-23 15:08:18 -0600[diff] [blame]132 { PCI_DID_INTEL_RPL_P_ID_2, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
Jeremy Compostella1b44c812022-06-17 15:18:02 -0700[diff] [blame]133 { PCI_DID_INTEL_RPL_P_ID_3, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) },
Lawrence Chang0a5da512022-10-19 14:38:41 +0800[diff] [blame]134 { PCI_DID_INTEL_RPL_P_ID_4, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) },
Marx Wang39ede0a2022-12-20 10:48:33 +0800[diff] [blame]135 { PCI_DID_INTEL_RPL_P_ID_5, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) },
Michał Żygowski4b9508b2022-04-25 15:05:15 +0200[diff] [blame]136 { PCI_DID_INTEL_ADL_S_ID_1, 150, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) },
137 { PCI_DID_INTEL_ADL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) },
138 { PCI_DID_INTEL_ADL_S_ID_1, 65, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) },
139 { PCI_DID_INTEL_ADL_S_ID_1, 35, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) },
140 { PCI_DID_INTEL_ADL_S_ID_3, 125, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) },
141 { PCI_DID_INTEL_ADL_S_ID_3, 65, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) },
142 { PCI_DID_INTEL_ADL_S_ID_3, 35, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) },
143 { PCI_DID_INTEL_ADL_S_ID_8, 125, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) },
144 { PCI_DID_INTEL_ADL_S_ID_10, 65, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) },
145 { PCI_DID_INTEL_ADL_S_ID_10, 35, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) },
146 { PCI_DID_INTEL_ADL_S_ID_11, 60, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) },
147 { PCI_DID_INTEL_ADL_S_ID_11, 58, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) },
148 { PCI_DID_INTEL_ADL_S_ID_11, 35, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) },
149 { PCI_DID_INTEL_ADL_S_ID_12, 46, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) },
150 { PCI_DID_INTEL_ADL_S_ID_12, 35, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) },
Max Fritz573e6de2022-11-19 01:54:44 +0100[diff] [blame]151 { PCI_DID_INTEL_RPL_S_ID_1, 150, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) },
152 { PCI_DID_INTEL_RPL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) },
153 { PCI_DID_INTEL_RPL_S_ID_1, 65, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) },
154 { PCI_DID_INTEL_RPL_S_ID_1, 35, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) },
155 { PCI_DID_INTEL_RPL_S_ID_3, 125, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) },
156 { PCI_DID_INTEL_RPL_S_ID_3, 65, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) },
157 { PCI_DID_INTEL_RPL_S_ID_3, 35, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) },
158 { PCI_DID_INTEL_RPL_S_ID_4, 125, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) },
159 { PCI_DID_INTEL_RPL_S_ID_4, 65, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) },
160 { PCI_DID_INTEL_RPL_S_ID_4, 35, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) },
161 { PCI_DID_INTEL_RPL_S_ID_5, 65, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) },
162 { PCI_DID_INTEL_RPL_S_ID_5, 35, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) },
Tim Crawford53c6eea2023-07-07 09:59:56 -0600[diff] [blame]163 { PCI_DID_INTEL_RPL_HX_ID_1, 55, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) },
164 { PCI_DID_INTEL_RPL_HX_ID_2, 55, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) },
165 { PCI_DID_INTEL_RPL_HX_ID_3, 55, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) },
166 { PCI_DID_INTEL_RPL_HX_ID_4, 55, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) },
167 { PCI_DID_INTEL_RPL_HX_ID_5, 55, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) },
168 { PCI_DID_INTEL_RPL_HX_ID_6, 55, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) },
169 { PCI_DID_INTEL_RPL_HX_ID_7, 55, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) },
170 { PCI_DID_INTEL_RPL_HX_ID_8, 55, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) },
V Sowmyac6d71662021-07-15 08:11:08 +0530[diff] [blame]171};
172
173static const struct vr_lookup vr_config_icc[] = {
Felix Singer43b7f412022-03-07 04:34:52 +0100[diff] [blame]174 { PCI_DID_INTEL_ADL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_ICC(120, 55) },
175 { PCI_DID_INTEL_ADL_P_ID_3, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) },
176 { PCI_DID_INTEL_ADL_P_ID_4, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) },
177 { PCI_DID_INTEL_ADL_P_ID_5, 45, VR_CFG_ALL_DOMAINS_ICC(120, 55) },
Patrick Rudolph4f37cf02023-03-15 15:32:26 +0100[diff] [blame]178 { PCI_DID_INTEL_ADL_P_ID_1, 28, VR_CFG_ALL_DOMAINS_ICC(85, 55) },
Felix Singer43b7f412022-03-07 04:34:52 +0100[diff] [blame]179 { PCI_DID_INTEL_ADL_P_ID_3, 28, VR_CFG_ALL_DOMAINS_ICC(109, 55) },
180 { PCI_DID_INTEL_ADL_P_ID_5, 28, VR_CFG_ALL_DOMAINS_ICC(85, 55) },
181 { PCI_DID_INTEL_ADL_P_ID_7, 28, VR_CFG_ALL_DOMAINS_ICC(85, 55) },
182 { PCI_DID_INTEL_ADL_P_ID_6, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) },
183 { PCI_DID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) },
184 { PCI_DID_INTEL_ADL_P_ID_10, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) },
V Sowmya7de81d52022-04-05 14:45:36 +0530[diff] [blame]185 { PCI_DID_INTEL_ADL_N_ID_1, 15, VR_CFG_ALL_DOMAINS_ICC(53, 29) },
186 { PCI_DID_INTEL_ADL_N_ID_1, 7, VR_CFG_ALL_DOMAINS_ICC(37, 29) },
187 { PCI_DID_INTEL_ADL_N_ID_2, 6, VR_CFG_ALL_DOMAINS_ICC(37, 29) },
188 { PCI_DID_INTEL_ADL_N_ID_3, 6, VR_CFG_ALL_DOMAINS_ICC(37, 26) },
189 { PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_ICC(27, 23) },
Jeremy Compostella1b44c812022-06-17 15:18:02 -0700[diff] [blame]190 { PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) },
191 { PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_ICC(102, 55) },
Tim Crawford198c6292023-06-23 15:08:18 -0600[diff] [blame]192 { PCI_DID_INTEL_RPL_P_ID_2, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) },
Jeremy Compostella7f96c052022-08-03 09:59:16 -0700[diff] [blame]193 { PCI_DID_INTEL_RPL_P_ID_3, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) },
Lawrence Chang0a5da512022-10-19 14:38:41 +0800[diff] [blame]194 { PCI_DID_INTEL_RPL_P_ID_4, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) },
Marx Wang39ede0a2022-12-20 10:48:33 +0800[diff] [blame]195 { PCI_DID_INTEL_RPL_P_ID_5, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) },
Michał Żygowski4b9508b2022-04-25 15:05:15 +0200[diff] [blame]196 { PCI_DID_INTEL_ADL_S_ID_1, 150, VR_CFG_ALL_DOMAINS_ICC(280, 30) },
197 { PCI_DID_INTEL_ADL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_ICC(280, 30) },
198 { PCI_DID_INTEL_ADL_S_ID_1, 65, VR_CFG_ALL_DOMAINS_ICC(240, 30) },
199 { PCI_DID_INTEL_ADL_S_ID_1, 35, VR_CFG_ALL_DOMAINS_ICC(154, 30) },
200 { PCI_DID_INTEL_ADL_S_ID_3, 125, VR_CFG_ALL_DOMAINS_ICC(240, 30) },
201 { PCI_DID_INTEL_ADL_S_ID_3, 65, VR_CFG_ALL_DOMAINS_ICC(220, 30) },
202 { PCI_DID_INTEL_ADL_S_ID_3, 35, VR_CFG_ALL_DOMAINS_ICC(145, 30) },
203 { PCI_DID_INTEL_ADL_S_ID_8, 125, VR_CFG_ALL_DOMAINS_ICC(175, 30) },
204 { PCI_DID_INTEL_ADL_S_ID_10, 65, VR_CFG_ALL_DOMAINS_ICC(151, 30) },
205 { PCI_DID_INTEL_ADL_S_ID_10, 35, VR_CFG_ALL_DOMAINS_ICC(100, 30) },
206 { PCI_DID_INTEL_ADL_S_ID_11, 60, VR_CFG_ALL_DOMAINS_ICC(110, 30) },
207 { PCI_DID_INTEL_ADL_S_ID_11, 58, VR_CFG_ALL_DOMAINS_ICC(110, 30) },
208 { PCI_DID_INTEL_ADL_S_ID_11, 35, VR_CFG_ALL_DOMAINS_ICC(90, 30) },
209 { PCI_DID_INTEL_ADL_S_ID_12, 46, VR_CFG_ALL_DOMAINS_ICC(49, 30) },
210 { PCI_DID_INTEL_ADL_S_ID_12, 35, VR_CFG_ALL_DOMAINS_ICC(37, 30) },
Max Fritz573e6de2022-11-19 01:54:44 +0100[diff] [blame]211 { PCI_DID_INTEL_RPL_S_ID_1, 150, VR_CFG_ALL_DOMAINS_ICC(307, 30) },
212 { PCI_DID_INTEL_RPL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_ICC(307, 30) },
213 { PCI_DID_INTEL_RPL_S_ID_1, 65, VR_CFG_ALL_DOMAINS_ICC(279, 30) },
214 { PCI_DID_INTEL_RPL_S_ID_1, 35, VR_CFG_ALL_DOMAINS_ICC(165, 30) },
215 { PCI_DID_INTEL_RPL_S_ID_3, 125, VR_CFG_ALL_DOMAINS_ICC(307, 30) },
216 { PCI_DID_INTEL_RPL_S_ID_3, 65, VR_CFG_ALL_DOMAINS_ICC(279, 30) },
217 { PCI_DID_INTEL_RPL_S_ID_3, 35, VR_CFG_ALL_DOMAINS_ICC(165, 30) },
218 { PCI_DID_INTEL_RPL_S_ID_4, 125, VR_CFG_ALL_DOMAINS_ICC(200, 30) },
219 { PCI_DID_INTEL_RPL_S_ID_4, 65, VR_CFG_ALL_DOMAINS_ICC(160, 30) },
220 { PCI_DID_INTEL_RPL_S_ID_4, 35, VR_CFG_ALL_DOMAINS_ICC(120, 30) },
221 { PCI_DID_INTEL_RPL_S_ID_5, 65, VR_CFG_ALL_DOMAINS_ICC(140, 30) },
222 { PCI_DID_INTEL_RPL_S_ID_5, 35, VR_CFG_ALL_DOMAINS_ICC(100, 30) },
Tim Crawford53c6eea2023-07-07 09:59:56 -0600[diff] [blame]223 { PCI_DID_INTEL_RPL_HX_ID_1, 55, VR_CFG_ALL_DOMAINS_ICC(215, 30) },
224 { PCI_DID_INTEL_RPL_HX_ID_2, 55, VR_CFG_ALL_DOMAINS_ICC(215, 30) },
225 { PCI_DID_INTEL_RPL_HX_ID_3, 55, VR_CFG_ALL_DOMAINS_ICC(215, 30) },
226 { PCI_DID_INTEL_RPL_HX_ID_4, 55, VR_CFG_ALL_DOMAINS_ICC(160, 30) },
227 { PCI_DID_INTEL_RPL_HX_ID_5, 55, VR_CFG_ALL_DOMAINS_ICC(160, 30) },
228 { PCI_DID_INTEL_RPL_HX_ID_6, 55, VR_CFG_ALL_DOMAINS_ICC(215, 30) },
229 { PCI_DID_INTEL_RPL_HX_ID_7, 55, VR_CFG_ALL_DOMAINS_ICC(160, 30) },
230 { PCI_DID_INTEL_RPL_HX_ID_8, 55, VR_CFG_ALL_DOMAINS_ICC(160, 30) },
V Sowmyac6d71662021-07-15 08:11:08 +0530[diff] [blame]231};
232
233static const struct vr_lookup vr_config_tdc_timewindow[] = {
Felix Singer43b7f412022-03-07 04:34:52 +0100[diff] [blame]234 { PCI_DID_INTEL_ADL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
235 { PCI_DID_INTEL_ADL_P_ID_3, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
236 { PCI_DID_INTEL_ADL_P_ID_4, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
237 { PCI_DID_INTEL_ADL_P_ID_5, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
Patrick Rudolph4f37cf02023-03-15 15:32:26 +0100[diff] [blame]238 { PCI_DID_INTEL_ADL_P_ID_1, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
Felix Singer43b7f412022-03-07 04:34:52 +0100[diff] [blame]239 { PCI_DID_INTEL_ADL_P_ID_3, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
240 { PCI_DID_INTEL_ADL_P_ID_5, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
241 { PCI_DID_INTEL_ADL_P_ID_7, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
242 { PCI_DID_INTEL_ADL_P_ID_6, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
243 { PCI_DID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
244 { PCI_DID_INTEL_ADL_P_ID_10, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
V Sowmya7de81d52022-04-05 14:45:36 +0530[diff] [blame]245 { PCI_DID_INTEL_ADL_N_ID_1, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
246 { PCI_DID_INTEL_ADL_N_ID_1, 7, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
247 { PCI_DID_INTEL_ADL_N_ID_2, 6, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
248 { PCI_DID_INTEL_ADL_N_ID_3, 6, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
249 { PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
Jeremy Compostella1b44c812022-06-17 15:18:02 -0700[diff] [blame]250 { PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
251 { PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
Tim Crawford198c6292023-06-23 15:08:18 -0600[diff] [blame]252 { PCI_DID_INTEL_RPL_P_ID_2, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
Jeremy Compostella1b44c812022-06-17 15:18:02 -0700[diff] [blame]253 { PCI_DID_INTEL_RPL_P_ID_3, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
Lawrence Chang0a5da512022-10-19 14:38:41 +0800[diff] [blame]254 { PCI_DID_INTEL_RPL_P_ID_4, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
Marx Wang39ede0a2022-12-20 10:48:33 +0800[diff] [blame]255 { PCI_DID_INTEL_RPL_P_ID_5, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
Michał Żygowski4b9508b2022-04-25 15:05:15 +0200[diff] [blame]256 { PCI_DID_INTEL_ADL_S_ID_1, 150, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
257 { PCI_DID_INTEL_ADL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
258 { PCI_DID_INTEL_ADL_S_ID_1, 65, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
259 { PCI_DID_INTEL_ADL_S_ID_1, 35, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
260 { PCI_DID_INTEL_ADL_S_ID_3, 125, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
261 { PCI_DID_INTEL_ADL_S_ID_3, 65, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
262 { PCI_DID_INTEL_ADL_S_ID_3, 35, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
263 { PCI_DID_INTEL_ADL_S_ID_8, 125, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
264 { PCI_DID_INTEL_ADL_S_ID_10, 65, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
265 { PCI_DID_INTEL_ADL_S_ID_10, 35, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
266 { PCI_DID_INTEL_ADL_S_ID_11, 60, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
267 { PCI_DID_INTEL_ADL_S_ID_11, 58, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
268 { PCI_DID_INTEL_ADL_S_ID_11, 35, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
269 { PCI_DID_INTEL_ADL_S_ID_12, 46, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
270 { PCI_DID_INTEL_ADL_S_ID_12, 35, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
Max Fritz573e6de2022-11-19 01:54:44 +0100[diff] [blame]271 { PCI_DID_INTEL_RPL_S_ID_1, 150, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
272 { PCI_DID_INTEL_RPL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
273 { PCI_DID_INTEL_RPL_S_ID_1, 65, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
274 { PCI_DID_INTEL_RPL_S_ID_1, 35, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
275 { PCI_DID_INTEL_RPL_S_ID_3, 125, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
276 { PCI_DID_INTEL_RPL_S_ID_3, 65, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
277 { PCI_DID_INTEL_RPL_S_ID_3, 35, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
278 { PCI_DID_INTEL_RPL_S_ID_4, 125, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
279 { PCI_DID_INTEL_RPL_S_ID_4, 65, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
280 { PCI_DID_INTEL_RPL_S_ID_4, 35, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
281 { PCI_DID_INTEL_RPL_S_ID_5, 65, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
282 { PCI_DID_INTEL_RPL_S_ID_5, 35, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
Tim Crawford53c6eea2023-07-07 09:59:56 -0600[diff] [blame]283 { PCI_DID_INTEL_RPL_HX_ID_1, 55, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
284 { PCI_DID_INTEL_RPL_HX_ID_2, 55, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
285 { PCI_DID_INTEL_RPL_HX_ID_3, 55, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
286 { PCI_DID_INTEL_RPL_HX_ID_4, 55, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
287 { PCI_DID_INTEL_RPL_HX_ID_5, 55, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
288 { PCI_DID_INTEL_RPL_HX_ID_6, 55, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
289 { PCI_DID_INTEL_RPL_HX_ID_7, 55, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
290 { PCI_DID_INTEL_RPL_HX_ID_8, 55, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
V Sowmyac6d71662021-07-15 08:11:08 +0530[diff] [blame]291};
292
293static const struct vr_lookup vr_config_tdc_currentlimit[] = {
Felix Singer43b7f412022-03-07 04:34:52 +0100[diff] [blame]294 { PCI_DID_INTEL_ADL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(47, 47) },
295 { PCI_DID_INTEL_ADL_P_ID_3, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(57, 57) },
296 { PCI_DID_INTEL_ADL_P_ID_4, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(57, 57) },
297 { PCI_DID_INTEL_ADL_P_ID_5, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(47, 47) },
Patrick Rudolph4f37cf02023-03-15 15:32:26 +0100[diff] [blame]298 { PCI_DID_INTEL_ADL_P_ID_1, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(40, 40) },
Felix Singer43b7f412022-03-07 04:34:52 +0100[diff] [blame]299 { PCI_DID_INTEL_ADL_P_ID_3, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(40, 40) },
300 { PCI_DID_INTEL_ADL_P_ID_5, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(32, 32) },
301 { PCI_DID_INTEL_ADL_P_ID_7, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(32, 32) },
302 { PCI_DID_INTEL_ADL_P_ID_6, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(20, 20) },
303 { PCI_DID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(20, 20) },
304 { PCI_DID_INTEL_ADL_P_ID_10, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(20, 20) },
V Sowmya7de81d52022-04-05 14:45:36 +0530[diff] [blame]305 { PCI_DID_INTEL_ADL_N_ID_1, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(22, 22) },
306 { PCI_DID_INTEL_ADL_N_ID_1, 7, VR_CFG_ALL_DOMAINS_TDC_CURRENT(14, 14) },
307 { PCI_DID_INTEL_ADL_N_ID_2, 6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 12) },
308 { PCI_DID_INTEL_ADL_N_ID_3, 6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 12) },
309 { PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(10, 10) },
Jeremy Compostella1b44c812022-06-17 15:18:02 -0700[diff] [blame]310 { PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(86, 86) },
Jeremy Compostella0973c322023-03-27 11:57:41 -0700[diff] [blame]311 { PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(33, 33) },
Tim Crawford198c6292023-06-23 15:08:18 -0600[diff] [blame]312 { PCI_DID_INTEL_RPL_P_ID_2, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(86, 86) },
Jeremy Compostella0973c322023-03-27 11:57:41 -0700[diff] [blame]313 { PCI_DID_INTEL_RPL_P_ID_3, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(22, 22) },
314 { PCI_DID_INTEL_RPL_P_ID_4, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(22, 22) },
315 { PCI_DID_INTEL_RPL_P_ID_5, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(22, 22) },
Michał Żygowski2fffb5d2023-02-12 23:01:20 +0100[diff] [blame]316 { PCI_DID_INTEL_ADL_S_ID_1, 150, VR_CFG_ALL_DOMAINS_TDC_CURRENT(132, 22) },
317 { PCI_DID_INTEL_ADL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_TDC_CURRENT(132, 22) },
318 { PCI_DID_INTEL_ADL_S_ID_1, 65, VR_CFG_ALL_DOMAINS_TDC_CURRENT(89, 22) },
319 { PCI_DID_INTEL_ADL_S_ID_1, 35, VR_CFG_ALL_DOMAINS_TDC_CURRENT(56, 20) },
320 { PCI_DID_INTEL_ADL_S_ID_3, 125, VR_CFG_ALL_DOMAINS_TDC_CURRENT(109, 22) },
321 { PCI_DID_INTEL_ADL_S_ID_3, 65, VR_CFG_ALL_DOMAINS_TDC_CURRENT(77, 22) },
322 { PCI_DID_INTEL_ADL_S_ID_3, 35, VR_CFG_ALL_DOMAINS_TDC_CURRENT(49, 20) },
323 { PCI_DID_INTEL_ADL_S_ID_8, 125, VR_CFG_ALL_DOMAINS_TDC_CURRENT(96, 22) },
324 { PCI_DID_INTEL_ADL_S_ID_10, 65, VR_CFG_ALL_DOMAINS_TDC_CURRENT(66, 22) },
325 { PCI_DID_INTEL_ADL_S_ID_10, 35, VR_CFG_ALL_DOMAINS_TDC_CURRENT(44, 20) },
326 { PCI_DID_INTEL_ADL_S_ID_11, 60, VR_CFG_ALL_DOMAINS_TDC_CURRENT(56, 22) },
327 { PCI_DID_INTEL_ADL_S_ID_11, 58, VR_CFG_ALL_DOMAINS_TDC_CURRENT(59, 22) },
328 { PCI_DID_INTEL_ADL_S_ID_11, 35, VR_CFG_ALL_DOMAINS_TDC_CURRENT(40, 20) },
329 { PCI_DID_INTEL_ADL_S_ID_12, 46, VR_CFG_ALL_DOMAINS_TDC_CURRENT(39, 20) },
330 { PCI_DID_INTEL_ADL_S_ID_12, 35, VR_CFG_ALL_DOMAINS_TDC_CURRENT(30, 20) },
Max Fritz573e6de2022-11-19 01:54:44 +0100[diff] [blame]331 { PCI_DID_INTEL_RPL_S_ID_1, 150, VR_CFG_ALL_DOMAINS_TDC_CURRENT(153, 22) },
332 { PCI_DID_INTEL_RPL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_TDC_CURRENT(140, 22) },
333 { PCI_DID_INTEL_RPL_S_ID_1, 65, VR_CFG_ALL_DOMAINS_TDC_CURRENT(94, 22) },
334 { PCI_DID_INTEL_RPL_S_ID_1, 35, VR_CFG_ALL_DOMAINS_TDC_CURRENT(57, 22) },
335 { PCI_DID_INTEL_RPL_S_ID_3, 125, VR_CFG_ALL_DOMAINS_TDC_CURRENT(140, 22) },
336 { PCI_DID_INTEL_RPL_S_ID_3, 65, VR_CFG_ALL_DOMAINS_TDC_CURRENT(94, 22) },
337 { PCI_DID_INTEL_RPL_S_ID_3, 35, VR_CFG_ALL_DOMAINS_TDC_CURRENT(57, 22) },
338 { PCI_DID_INTEL_RPL_S_ID_4, 125, VR_CFG_ALL_DOMAINS_TDC_CURRENT(114, 22) },
339 { PCI_DID_INTEL_RPL_S_ID_4, 65, VR_CFG_ALL_DOMAINS_TDC_CURRENT(78, 22) },
340 { PCI_DID_INTEL_RPL_S_ID_4, 35, VR_CFG_ALL_DOMAINS_TDC_CURRENT(51, 22) },
341 { PCI_DID_INTEL_RPL_S_ID_5, 65, VR_CFG_ALL_DOMAINS_TDC_CURRENT(69, 22) },
342 { PCI_DID_INTEL_RPL_S_ID_5, 35, VR_CFG_ALL_DOMAINS_TDC_CURRENT(44, 22) },
Tim Crawford53c6eea2023-07-07 09:59:56 -0600[diff] [blame]343 { PCI_DID_INTEL_RPL_HX_ID_1, 55, VR_CFG_ALL_DOMAINS_TDC_CURRENT(89, 22) },
344 { PCI_DID_INTEL_RPL_HX_ID_2, 55, VR_CFG_ALL_DOMAINS_TDC_CURRENT(89, 22) },
345 { PCI_DID_INTEL_RPL_HX_ID_3, 55, VR_CFG_ALL_DOMAINS_TDC_CURRENT(89, 22) },
346 { PCI_DID_INTEL_RPL_HX_ID_4, 55, VR_CFG_ALL_DOMAINS_TDC_CURRENT(89, 22) },
347 { PCI_DID_INTEL_RPL_HX_ID_5, 55, VR_CFG_ALL_DOMAINS_TDC_CURRENT(89, 22) },
348 { PCI_DID_INTEL_RPL_HX_ID_6, 55, VR_CFG_ALL_DOMAINS_TDC_CURRENT(89, 22) },
349 { PCI_DID_INTEL_RPL_HX_ID_7, 55, VR_CFG_ALL_DOMAINS_TDC_CURRENT(89, 22) },
350 { PCI_DID_INTEL_RPL_HX_ID_8, 55, VR_CFG_ALL_DOMAINS_TDC_CURRENT(89, 22) },
V Sowmyac6d71662021-07-15 08:11:08 +0530[diff] [blame]351};
352
Jeremy Compostella9159e1c2022-06-02 16:49:48 -0700[diff] [blame]353static void fill_vr_fast_vmode(FSP_S_CONFIG *s_cfg,
354 int domain, const struct vr_config *chip_cfg)
355{
Michał Żygowski01025d32023-07-12 13:22:09 +0200[diff] [blame]356#if CONFIG(SOC_INTEL_RAPTORLAKE) || CONFIG(FSP_USE_REPO)
Jeremy Compostella9159e1c2022-06-02 16:49:48 -0700[diff] [blame]357 s_cfg->EnableFastVmode[domain] = chip_cfg->enable_fast_vmode;
358 if (s_cfg->EnableFastVmode[domain])
359 s_cfg->IccLimit[domain] = chip_cfg->fast_vmode_i_trip;
360#endif
361}
362
V Sowmyac6d71662021-07-15 08:11:08 +0530[diff] [blame]363void fill_vr_domain_config(FSP_S_CONFIG *s_cfg,
364 int domain, const struct vr_config *chip_cfg)
365{
366 const struct vr_config *cfg;
367
368 if (domain < 0 || domain >= NUM_VR_DOMAINS)
369 return;
370
371 /* Use device tree override if requested */
372 if (chip_cfg->vr_config_enable) {
373 cfg = chip_cfg;
374
Bora Guvendikf6f12582021-09-02 13:23:03 -0700[diff] [blame]375 if (cfg->ac_loadline)
376 s_cfg->AcLoadline[domain] = cfg->ac_loadline;
377 if (cfg->dc_loadline)
378 s_cfg->DcLoadline[domain] = cfg->dc_loadline;
379 if (cfg->icc_max)
380 s_cfg->IccMax[domain] = cfg->icc_max;
Gaggery Tsai517c5a82022-09-08 13:42:08 -0700[diff] [blame]381 if (cfg->psi1threshold)
382 s_cfg->Psi1Threshold[domain] = cfg->psi1threshold;
383 if (cfg->psi2threshold)
384 s_cfg->Psi2Threshold[domain] = cfg->psi2threshold;
385 if (cfg->psi3threshold)
386 s_cfg->Psi3Threshold[domain] = cfg->psi3threshold;
V Sowmyac6d71662021-07-15 08:11:08 +0530[diff] [blame]387 s_cfg->TdcTimeWindow[domain] = cfg->tdc_timewindow;
388 s_cfg->TdcCurrentLimit[domain] = cfg->tdc_currentlimit;
V Sowmyac6d71662021-07-15 08:11:08 +0530[diff] [blame]389 } else {
Curtis Chenea1bb5f2021-11-25 13:17:42 +0800[diff] [blame]390 uint8_t tdp = get_cpu_tdp();
Jeremy Compostella14908bf2022-06-07 10:25:43 -0700[diff] [blame]391 struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT);
392 uint16_t mch_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff;
V Sowmyac6d71662021-07-15 08:11:08 +0530[diff] [blame]393
394 s_cfg->AcLoadline[domain] = load_table(vr_config_ll, ARRAY_SIZE(vr_config_ll),
Curtis Chenea1bb5f2021-11-25 13:17:42 +0800[diff] [blame]395 domain, mch_id, tdp);
V Sowmyac6d71662021-07-15 08:11:08 +0530[diff] [blame]396 s_cfg->DcLoadline[domain] = load_table(vr_config_ll, ARRAY_SIZE(vr_config_ll),
Curtis Chenea1bb5f2021-11-25 13:17:42 +0800[diff] [blame]397 domain, mch_id, tdp);
V Sowmyac6d71662021-07-15 08:11:08 +0530[diff] [blame]398 s_cfg->IccMax[domain] = load_table(vr_config_icc, ARRAY_SIZE(vr_config_icc),
Curtis Chenea1bb5f2021-11-25 13:17:42 +0800[diff] [blame]399 domain, mch_id, tdp);
V Sowmyac6d71662021-07-15 08:11:08 +0530[diff] [blame]400 s_cfg->TdcTimeWindow[domain] = load_table(vr_config_tdc_timewindow,
401 ARRAY_SIZE(vr_config_tdc_timewindow),
Curtis Chenea1bb5f2021-11-25 13:17:42 +0800[diff] [blame]402 domain, mch_id, tdp);
V Sowmyac6d71662021-07-15 08:11:08 +0530[diff] [blame]403 s_cfg->TdcCurrentLimit[domain] = load_table(vr_config_tdc_currentlimit,
404 ARRAY_SIZE(vr_config_tdc_currentlimit),
Curtis Chenea1bb5f2021-11-25 13:17:42 +0800[diff] [blame]405 domain, mch_id, tdp);
Ronak Kanabar1f88a712021-07-15 19:02:22 +0530[diff] [blame]406 }
407
Jeremy Compostella9159e1c2022-06-02 16:49:48 -0700[diff] [blame]408 fill_vr_fast_vmode(s_cfg, domain, chip_cfg);
409
Ronak Kanabar1f88a712021-07-15 19:02:22 +0530[diff] [blame]410 /* Check TdcTimeWindow and TdcCurrentLimit,
411 Set TdcEnable and Set VR TDC Input current to root mean square */
412 if (s_cfg->TdcTimeWindow[domain] != 0 && s_cfg->TdcCurrentLimit[domain] != 0) {
413 s_cfg->TdcEnable[domain] = 1;
414 s_cfg->Irms[domain] = 1;
V Sowmyac6d71662021-07-15 08:11:08 +0530[diff] [blame]415 }
416}