V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <device/pci_ids.h> |
| 4 | #include <device/pci_ops.h> |
| 5 | #include <fsp/api.h> |
| 6 | #include <soc/ramstage.h> |
| 7 | #include <soc/vr_config.h> |
| 8 | #include <console/console.h> |
| 9 | #include <intelblocks/cpulib.h> |
| 10 | |
| 11 | /* |
| 12 | * VR Configurations for IA and GT domains for ADL-P SKU's. |
Curtis Chen | 150fee6 | 2021-12-21 11:51:33 +0800 | [diff] [blame] | 13 | * Per doc#627345 ADL_P Partial Intel PlatformDesignStudio Rev 2.0.0, update PD |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 14 | * |
| 15 | * +----------------+-----------+-------+-------+---------+-------------+----------+ |
| 16 | * | SKU | Setting | AC LL | DC LL | ICC MAX | TDC Current | TDC Time | |
| 17 | * | | |(mOhms)|(mOhms)| (A) | (A) | (msec) | |
| 18 | * +----------------+-----------+-------+-------+---------+-------------+----------+ |
| 19 | * | ADL-P 682(45W) | IA | 2.3 | 2.3 | 160 | 57 | 28000 | |
| 20 | * + +-----------+-------+-------+---------+-------------+----------+ |
Curtis Chen | 150fee6 | 2021-12-21 11:51:33 +0800 | [diff] [blame] | 21 | * | | GT | 3.2 | 3.2 | 55 | 57 | 28000 | |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 22 | * +----------------+-----------+-------+-------+---------+-------------+----------+ |
Curtis Chen | 150fee6 | 2021-12-21 11:51:33 +0800 | [diff] [blame] | 23 | * | ADL-P 482(45W) | IA | 2.3 | 2.3 | 120 | 47 | 28000 | |
| 24 | * + 442(45W) +-----------+-------+-------+---------+-------------+----------+ |
| 25 | * | | GT | 3.2 | 3.2 | 55 | 47 | 28000 | |
| 26 | * +----------------+-----------+-------+-------+---------+-------------+----------+ |
| 27 | * | ADL-P 682(28W) | IA | 2.3 | 2.3 | 109 | 40 | 28000 | |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 28 | * + +-----------+-------+-------+---------+-------------+----------+ |
Curtis Chen | 150fee6 | 2021-12-21 11:51:33 +0800 | [diff] [blame] | 29 | * | | GT | 3.2 | 3.2 | 55 | 40 | 28000 | |
| 30 | * +----------------+-----------+-------+-------+---------+-------------+----------+ |
| 31 | * | ADL-P 482(28W) | IA | 2.3 | 2.3 | 85 | 32 | 28000 | |
| 32 | * + +-----------+-------+-------+---------+-------------+----------+ |
| 33 | * | | GT | 3.2 | 3.2 | 55 | 32 | 28000 | |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 34 | * +----------------+-----------+-------+-------+---------+-------------+----------+ |
| 35 | * | ADL-P 282(15W) | IA | 2.8 | 2.8 | 80 | 20 | 28000 | |
| 36 | * + +-----------+-------+-------+---------+-------------+----------+ |
| 37 | * | | GT | 3.2 | 3.2 | 40 | 20 | 28000 | |
| 38 | * +----------------+-----------+-------+-------+---------+-------------+----------+ |
| 39 | */ |
| 40 | |
V Sowmya | 7de81d5 | 2022-04-05 14:45:36 +0530 | [diff] [blame] | 41 | /* |
| 42 | * VR Configurations for IA and GT domains for ADL-N SKU's. |
| 43 | * Per doc#646929 ADL N Platform Design Guide -> Power_Map_Rev1p0 |
| 44 | * |
| 45 | * +----------------+-----------+-------+-------+---------+-------------+----------+ |
| 46 | * | SKU | Setting | AC LL | DC LL | ICC MAX | TDC Current | TDC Time | |
| 47 | * | | |(mOhms)|(mOhms)| (A) | (A) | (msec) | |
| 48 | * +----------------+-----------+-------+-------+---------+-------------+----------+ |
| 49 | * | ADL-N 081(15W) | IA | 4.7 | 4.7 | 53 | 22 | 28000 | |
| 50 | * + +-----------+-------+-------+---------+-------------+----------+ |
| 51 | * | | GT | 6.5 | 6.5 | 29 | 22 | 28000 | |
| 52 | * +----------------+-----------+-------+-------+---------+-------------+----------+ |
| 53 | * | ADL-N 081(7W) | IA | 5.0 | 5.0 | 37 | 14 | 28000 | |
| 54 | * + +-----------+-------+-------+---------+-------------+----------+ |
| 55 | * | | GT | 6.5 | 6.5 | 29 | 14 | 28000 | |
| 56 | * +----------------+-----------+-------+-------+---------+-------------+----------+ |
| 57 | * | ADL-N 041(6W) | IA | 5.0 | 5.0 | 37 | 12 | 28000 | |
| 58 | * + Pentium +-----------+-------+-------+---------+-------------+----------+ |
| 59 | * | | GT | 6.5 | 6.5 | 29 | 12 | 28000 | |
| 60 | * +----------------+-----------+-------+-------+---------+-------------+----------+ |
| 61 | * | ADL-N 041(6W) | IA | 5.0 | 5.0 | 37 | 12 | 28000 | |
| 62 | * + Celeron +-----------+-------+-------+---------+-------------+----------+ |
| 63 | * | | GT | 6.5 | 6.5 | 26 | 12 | 28000 | |
| 64 | * +----------------+-----------+-------+-------+---------+-------------+----------+ |
| 65 | * | ADL-N 021(6W) | IA | 5.0 | 5.0 | 27 | 10 | 28000 | |
| 66 | * + +-----------+-------+-------+---------+-------------+----------+ |
| 67 | * | | GT | 6.5 | 6.5 | 23 | 10 | 28000 | |
| 68 | * +----------------+-----------+-------+-------+---------+-------------+----------+ |
| 69 | */ |
| 70 | |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 71 | struct vr_lookup { |
| 72 | uint16_t mchid; |
Curtis Chen | ea1bb5f | 2021-11-25 13:17:42 +0800 | [diff] [blame] | 73 | uint8_t tdp; |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 74 | uint32_t conf[NUM_VR_DOMAINS]; |
| 75 | }; |
| 76 | |
| 77 | static uint32_t load_table(const struct vr_lookup *tbl, const int tbl_entries, const int domain, |
Curtis Chen | ea1bb5f | 2021-11-25 13:17:42 +0800 | [diff] [blame] | 78 | const uint16_t mch_id, uint8_t tdp) |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 79 | { |
| 80 | for (size_t i = 0; i < tbl_entries; i++) { |
Curtis Chen | ea1bb5f | 2021-11-25 13:17:42 +0800 | [diff] [blame] | 81 | if (tbl[i].mchid != mch_id || tbl[i].tdp != tdp) |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 82 | continue; |
| 83 | return tbl[i].conf[domain]; |
| 84 | } |
| 85 | |
Julius Werner | e966595 | 2022-01-21 17:06:20 -0800 | [diff] [blame] | 86 | printk(BIOS_ERR, "Unknown MCH (0x%x) in %s\n", mch_id, __func__); |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 87 | return 0; |
| 88 | } |
| 89 | |
Curtis Chen | 1f8563e | 2021-11-30 14:04:48 +0800 | [diff] [blame] | 90 | /* Per the power map from #613643, update ADL-P 6+8+2 (28W) VR configuration */ |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 91 | static const struct vr_lookup vr_config_ll[] = { |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 92 | { PCI_DID_INTEL_ADL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, |
| 93 | { PCI_DID_INTEL_ADL_P_ID_3, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, |
| 94 | { PCI_DID_INTEL_ADL_P_ID_4, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, |
| 95 | { PCI_DID_INTEL_ADL_P_ID_5, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, |
| 96 | { PCI_DID_INTEL_ADL_P_ID_3, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, |
| 97 | { PCI_DID_INTEL_ADL_P_ID_5, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, |
| 98 | { PCI_DID_INTEL_ADL_P_ID_7, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, |
| 99 | { PCI_DID_INTEL_ADL_P_ID_6, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) }, |
| 100 | { PCI_DID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) }, |
| 101 | { PCI_DID_INTEL_ADL_P_ID_10, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) }, |
V Sowmya | 7de81d5 | 2022-04-05 14:45:36 +0530 | [diff] [blame] | 102 | { PCI_DID_INTEL_ADL_N_ID_1, 15, VR_CFG_ALL_DOMAINS_LOADLINE(4.7, 6.5) }, |
| 103 | { PCI_DID_INTEL_ADL_N_ID_1, 7, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) }, |
| 104 | { PCI_DID_INTEL_ADL_N_ID_2, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) }, |
| 105 | { PCI_DID_INTEL_ADL_N_ID_3, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) }, |
| 106 | { PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) }, |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 107 | }; |
| 108 | |
| 109 | static const struct vr_lookup vr_config_icc[] = { |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 110 | { PCI_DID_INTEL_ADL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_ICC(120, 55) }, |
| 111 | { PCI_DID_INTEL_ADL_P_ID_3, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) }, |
| 112 | { PCI_DID_INTEL_ADL_P_ID_4, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) }, |
| 113 | { PCI_DID_INTEL_ADL_P_ID_5, 45, VR_CFG_ALL_DOMAINS_ICC(120, 55) }, |
| 114 | { PCI_DID_INTEL_ADL_P_ID_3, 28, VR_CFG_ALL_DOMAINS_ICC(109, 55) }, |
| 115 | { PCI_DID_INTEL_ADL_P_ID_5, 28, VR_CFG_ALL_DOMAINS_ICC(85, 55) }, |
| 116 | { PCI_DID_INTEL_ADL_P_ID_7, 28, VR_CFG_ALL_DOMAINS_ICC(85, 55) }, |
| 117 | { PCI_DID_INTEL_ADL_P_ID_6, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) }, |
| 118 | { PCI_DID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) }, |
| 119 | { PCI_DID_INTEL_ADL_P_ID_10, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) }, |
V Sowmya | 7de81d5 | 2022-04-05 14:45:36 +0530 | [diff] [blame] | 120 | { PCI_DID_INTEL_ADL_N_ID_1, 15, VR_CFG_ALL_DOMAINS_ICC(53, 29) }, |
| 121 | { PCI_DID_INTEL_ADL_N_ID_1, 7, VR_CFG_ALL_DOMAINS_ICC(37, 29) }, |
| 122 | { PCI_DID_INTEL_ADL_N_ID_2, 6, VR_CFG_ALL_DOMAINS_ICC(37, 29) }, |
| 123 | { PCI_DID_INTEL_ADL_N_ID_3, 6, VR_CFG_ALL_DOMAINS_ICC(37, 26) }, |
| 124 | { PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_ICC(27, 23) }, |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 125 | }; |
| 126 | |
| 127 | static const struct vr_lookup vr_config_tdc_timewindow[] = { |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 128 | { PCI_DID_INTEL_ADL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, |
| 129 | { PCI_DID_INTEL_ADL_P_ID_3, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, |
| 130 | { PCI_DID_INTEL_ADL_P_ID_4, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, |
| 131 | { PCI_DID_INTEL_ADL_P_ID_5, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, |
| 132 | { PCI_DID_INTEL_ADL_P_ID_3, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, |
| 133 | { PCI_DID_INTEL_ADL_P_ID_5, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, |
| 134 | { PCI_DID_INTEL_ADL_P_ID_7, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, |
| 135 | { PCI_DID_INTEL_ADL_P_ID_6, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, |
| 136 | { PCI_DID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, |
| 137 | { PCI_DID_INTEL_ADL_P_ID_10, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, |
V Sowmya | 7de81d5 | 2022-04-05 14:45:36 +0530 | [diff] [blame] | 138 | { PCI_DID_INTEL_ADL_N_ID_1, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, |
| 139 | { PCI_DID_INTEL_ADL_N_ID_1, 7, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, |
| 140 | { PCI_DID_INTEL_ADL_N_ID_2, 6, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, |
| 141 | { PCI_DID_INTEL_ADL_N_ID_3, 6, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, |
| 142 | { PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 143 | }; |
| 144 | |
| 145 | static const struct vr_lookup vr_config_tdc_currentlimit[] = { |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 146 | { PCI_DID_INTEL_ADL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(47, 47) }, |
| 147 | { PCI_DID_INTEL_ADL_P_ID_3, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(57, 57) }, |
| 148 | { PCI_DID_INTEL_ADL_P_ID_4, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(57, 57) }, |
| 149 | { PCI_DID_INTEL_ADL_P_ID_5, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(47, 47) }, |
| 150 | { PCI_DID_INTEL_ADL_P_ID_3, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(40, 40) }, |
| 151 | { PCI_DID_INTEL_ADL_P_ID_5, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(32, 32) }, |
| 152 | { PCI_DID_INTEL_ADL_P_ID_7, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(32, 32) }, |
| 153 | { PCI_DID_INTEL_ADL_P_ID_6, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(20, 20) }, |
| 154 | { PCI_DID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(20, 20) }, |
| 155 | { PCI_DID_INTEL_ADL_P_ID_10, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(20, 20) }, |
V Sowmya | 7de81d5 | 2022-04-05 14:45:36 +0530 | [diff] [blame] | 156 | { PCI_DID_INTEL_ADL_N_ID_1, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(22, 22) }, |
| 157 | { PCI_DID_INTEL_ADL_N_ID_1, 7, VR_CFG_ALL_DOMAINS_TDC_CURRENT(14, 14) }, |
| 158 | { PCI_DID_INTEL_ADL_N_ID_2, 6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 12) }, |
| 159 | { PCI_DID_INTEL_ADL_N_ID_3, 6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 12) }, |
| 160 | { PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(10, 10) }, |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 161 | }; |
| 162 | |
| 163 | void fill_vr_domain_config(FSP_S_CONFIG *s_cfg, |
| 164 | int domain, const struct vr_config *chip_cfg) |
| 165 | { |
| 166 | const struct vr_config *cfg; |
| 167 | |
| 168 | if (domain < 0 || domain >= NUM_VR_DOMAINS) |
| 169 | return; |
| 170 | |
| 171 | /* Use device tree override if requested */ |
| 172 | if (chip_cfg->vr_config_enable) { |
| 173 | cfg = chip_cfg; |
| 174 | |
Bora Guvendik | f6f1258 | 2021-09-02 13:23:03 -0700 | [diff] [blame] | 175 | if (cfg->ac_loadline) |
| 176 | s_cfg->AcLoadline[domain] = cfg->ac_loadline; |
| 177 | if (cfg->dc_loadline) |
| 178 | s_cfg->DcLoadline[domain] = cfg->dc_loadline; |
| 179 | if (cfg->icc_max) |
| 180 | s_cfg->IccMax[domain] = cfg->icc_max; |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 181 | s_cfg->TdcTimeWindow[domain] = cfg->tdc_timewindow; |
| 182 | s_cfg->TdcCurrentLimit[domain] = cfg->tdc_currentlimit; |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 183 | } else { |
Curtis Chen | ea1bb5f | 2021-11-25 13:17:42 +0800 | [diff] [blame] | 184 | uint8_t tdp = get_cpu_tdp(); |
Jeremy Compostella | 14908bf | 2022-06-07 10:25:43 -0700 | [diff] [blame^] | 185 | struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); |
| 186 | uint16_t mch_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff; |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 187 | |
| 188 | s_cfg->AcLoadline[domain] = load_table(vr_config_ll, ARRAY_SIZE(vr_config_ll), |
Curtis Chen | ea1bb5f | 2021-11-25 13:17:42 +0800 | [diff] [blame] | 189 | domain, mch_id, tdp); |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 190 | s_cfg->DcLoadline[domain] = load_table(vr_config_ll, ARRAY_SIZE(vr_config_ll), |
Curtis Chen | ea1bb5f | 2021-11-25 13:17:42 +0800 | [diff] [blame] | 191 | domain, mch_id, tdp); |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 192 | s_cfg->IccMax[domain] = load_table(vr_config_icc, ARRAY_SIZE(vr_config_icc), |
Curtis Chen | ea1bb5f | 2021-11-25 13:17:42 +0800 | [diff] [blame] | 193 | domain, mch_id, tdp); |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 194 | s_cfg->TdcTimeWindow[domain] = load_table(vr_config_tdc_timewindow, |
| 195 | ARRAY_SIZE(vr_config_tdc_timewindow), |
Curtis Chen | ea1bb5f | 2021-11-25 13:17:42 +0800 | [diff] [blame] | 196 | domain, mch_id, tdp); |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 197 | s_cfg->TdcCurrentLimit[domain] = load_table(vr_config_tdc_currentlimit, |
| 198 | ARRAY_SIZE(vr_config_tdc_currentlimit), |
Curtis Chen | ea1bb5f | 2021-11-25 13:17:42 +0800 | [diff] [blame] | 199 | domain, mch_id, tdp); |
Ronak Kanabar | 1f88a71 | 2021-07-15 19:02:22 +0530 | [diff] [blame] | 200 | } |
| 201 | |
| 202 | /* Check TdcTimeWindow and TdcCurrentLimit, |
| 203 | Set TdcEnable and Set VR TDC Input current to root mean square */ |
| 204 | if (s_cfg->TdcTimeWindow[domain] != 0 && s_cfg->TdcCurrentLimit[domain] != 0) { |
| 205 | s_cfg->TdcEnable[domain] = 1; |
| 206 | s_cfg->Irms[domain] = 1; |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 207 | } |
| 208 | } |