Patrick Georgi | 16849bb | 2020-05-10 17:52:40 +0200 | [diff] [blame] | 1 | /* Source : APQ8064 LK boot */ |
Patrick Georgi | 7051707 | 2020-05-10 18:47:05 +0200 | [diff] [blame] | 2 | /* SPDX-License-Identifier: BSD-3-Clause */ |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 3 | |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 4 | #include <device/mmio.h> |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 5 | #include <boot/coreboot_tables.h> |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 6 | #include <console/uart.h> |
Julius Werner | 73d1ed6 | 2014-10-20 13:20:49 -0700 | [diff] [blame] | 7 | #include <delay.h> |
Julius Werner | eaa9c45 | 2014-09-24 15:40:49 -0700 | [diff] [blame] | 8 | #include <gpio.h> |
Julius Werner | 73d1ed6 | 2014-10-20 13:20:49 -0700 | [diff] [blame] | 9 | #include <soc/clock.h> |
Julius Werner | 73d1ed6 | 2014-10-20 13:20:49 -0700 | [diff] [blame] | 10 | #include <soc/gsbi.h> |
| 11 | #include <soc/ipq_uart.h> |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 12 | #include <stdint.h> |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 13 | |
| 14 | #define FIFO_DATA_SIZE 4 |
| 15 | |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 16 | typedef struct { |
Vadim Bendebury | b67b715 | 2015-01-13 12:46:57 -0800 | [diff] [blame] | 17 | void *uart_dm_base; |
| 18 | void *uart_gsbi_base; |
Martin Roth | 57e8909 | 2019-10-23 21:45:23 -0600 | [diff] [blame] | 19 | unsigned int uart_gsbi; |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 20 | uart_clk_mnd_t mnd_value; |
| 21 | gpio_func_data_t dbg_uart_gpio[NO_OF_DBG_UART_GPIOS]; |
| 22 | } uart_params_t; |
| 23 | |
| 24 | /* |
| 25 | * All constants lifted from u-boot's |
| 26 | * board/qcom/ipq806x_cdp/ipq806x_board_param.h |
| 27 | */ |
| 28 | static const uart_params_t uart_board_param = { |
Vadim Bendebury | b67b715 | 2015-01-13 12:46:57 -0800 | [diff] [blame] | 29 | .uart_dm_base = (void *)UART4_DM_BASE, |
| 30 | .uart_gsbi_base = (void *)UART_GSBI4_BASE, |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 31 | .uart_gsbi = GSBI_4, |
| 32 | .mnd_value = { 12, 625, 313 }, |
Vadim Bendebury | b67b715 | 2015-01-13 12:46:57 -0800 | [diff] [blame] | 33 | .dbg_uart_gpio = { |
| 34 | { |
| 35 | .gpio = 10, |
| 36 | .func = 1, |
| 37 | .dir = GPIO_OUTPUT, |
| 38 | .pull = GPIO_NO_PULL, |
| 39 | .drvstr = GPIO_12MA, |
| 40 | .enable = GPIO_DISABLE |
| 41 | }, |
| 42 | { |
| 43 | .gpio = 11, |
| 44 | .func = 1, |
| 45 | .dir = GPIO_INPUT, |
| 46 | .pull = GPIO_NO_PULL, |
| 47 | .drvstr = GPIO_12MA, |
| 48 | .enable = GPIO_DISABLE |
| 49 | }, |
| 50 | } |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 51 | }; |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 52 | |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 53 | /** |
| 54 | * msm_boot_uart_dm_init_rx_transfer - Init Rx transfer |
Martin Roth | 4934818 | 2016-07-06 10:17:19 -0600 | [diff] [blame] | 55 | * @param uart_dm_base: UART controller base address |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 56 | */ |
Vadim Bendebury | b67b715 | 2015-01-13 12:46:57 -0800 | [diff] [blame] | 57 | static unsigned int msm_boot_uart_dm_init_rx_transfer(void *uart_dm_base) |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 58 | { |
| 59 | /* Reset receiver */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 60 | write32(MSM_BOOT_UART_DM_CR(uart_dm_base), |
| 61 | MSM_BOOT_UART_DM_CMD_RESET_RX); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 62 | |
| 63 | /* Enable receiver */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 64 | write32(MSM_BOOT_UART_DM_CR(uart_dm_base), |
| 65 | MSM_BOOT_UART_DM_CR_RX_ENABLE); |
| 66 | write32(MSM_BOOT_UART_DM_DMRX(uart_dm_base), |
| 67 | MSM_BOOT_UART_DM_DMRX_DEF_VALUE); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 68 | |
| 69 | /* Clear stale event */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 70 | write32(MSM_BOOT_UART_DM_CR(uart_dm_base), |
| 71 | MSM_BOOT_UART_DM_CMD_RES_STALE_INT); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 72 | |
| 73 | /* Enable stale event */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 74 | write32(MSM_BOOT_UART_DM_CR(uart_dm_base), |
| 75 | MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 76 | |
| 77 | return MSM_BOOT_UART_DM_E_SUCCESS; |
| 78 | } |
| 79 | |
Vadim Bendebury | 7c25640 | 2015-01-13 13:07:48 -0800 | [diff] [blame] | 80 | static unsigned int msm_boot_uart_dm_init(void *uart_dm_base); |
| 81 | |
| 82 | /* Received data is valid or not */ |
| 83 | static int valid_data = 0; |
| 84 | |
| 85 | /* Received data */ |
| 86 | static unsigned int word = 0; |
| 87 | |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 88 | /** |
| 89 | * msm_boot_uart_dm_read - reads a word from the RX FIFO. |
| 90 | * @data: location where the read data is stored |
| 91 | * @count: no of valid data in the FIFO |
| 92 | * @wait: indicates blocking call or not blocking call |
| 93 | * |
| 94 | * Reads a word from the RX FIFO. If no data is available blocks if |
| 95 | * @wait is true, else returns %MSM_BOOT_UART_DM_E_RX_NOT_READY. |
| 96 | */ |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 97 | #if 0 /* Not used yet */ |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 98 | static unsigned int |
| 99 | msm_boot_uart_dm_read(unsigned int *data, int *count, int wait) |
| 100 | { |
| 101 | static int total_rx_data = 0; |
| 102 | static int rx_data_read = 0; |
Vadim Bendebury | b67b715 | 2015-01-13 12:46:57 -0800 | [diff] [blame] | 103 | void *base; |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 104 | uint32_t status_reg; |
| 105 | |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 106 | base = uart_board_param.uart_dm_base; |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 107 | |
| 108 | if (data == NULL) |
| 109 | return MSM_BOOT_UART_DM_E_INVAL; |
| 110 | |
Vadim Bendebury | b67b715 | 2015-01-13 12:46:57 -0800 | [diff] [blame] | 111 | status_reg = readl(MSM_BOOT_UART_DM_MISR(base)); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 112 | |
| 113 | /* Check for DM_RXSTALE for RX transfer to finish */ |
| 114 | while (!(status_reg & MSM_BOOT_UART_DM_RXSTALE)) { |
Vadim Bendebury | b67b715 | 2015-01-13 12:46:57 -0800 | [diff] [blame] | 115 | status_reg = readl(MSM_BOOT_UART_DM_MISR(base)); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 116 | if (!wait) |
| 117 | return MSM_BOOT_UART_DM_E_RX_NOT_READY; |
| 118 | } |
| 119 | |
| 120 | /* Check for Overrun error. We'll just reset Error Status */ |
Vadim Bendebury | b67b715 | 2015-01-13 12:46:57 -0800 | [diff] [blame] | 121 | if (readl(MSM_BOOT_UART_DM_SR(base)) & |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 122 | MSM_BOOT_UART_DM_SR_UART_OVERRUN) { |
Vadim Bendebury | b67b715 | 2015-01-13 12:46:57 -0800 | [diff] [blame] | 123 | writel(MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT, |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 124 | MSM_BOOT_UART_DM_CR(base)); |
| 125 | total_rx_data = rx_data_read = 0; |
| 126 | msm_boot_uart_dm_init(base); |
| 127 | return MSM_BOOT_UART_DM_E_RX_NOT_READY; |
| 128 | } |
| 129 | |
| 130 | /* Read UART_DM_RX_TOTAL_SNAP for actual number of bytes received */ |
| 131 | if (total_rx_data == 0) |
Vadim Bendebury | b67b715 | 2015-01-13 12:46:57 -0800 | [diff] [blame] | 132 | total_rx_data = readl(MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base)); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 133 | |
| 134 | /* Data available in FIFO; read a word. */ |
Vadim Bendebury | b67b715 | 2015-01-13 12:46:57 -0800 | [diff] [blame] | 135 | *data = readl(MSM_BOOT_UART_DM_RF(base, 0)); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 136 | |
| 137 | /* WAR for http://prism/CR/548280 */ |
| 138 | if (*data == 0) { |
| 139 | return MSM_BOOT_UART_DM_E_RX_NOT_READY; |
| 140 | } |
| 141 | |
| 142 | /* increment the total count of chars we've read so far */ |
| 143 | rx_data_read += FIFO_DATA_SIZE; |
| 144 | |
| 145 | /* actual count of valid data in word */ |
| 146 | *count = ((total_rx_data < rx_data_read) ? |
| 147 | (FIFO_DATA_SIZE - (rx_data_read - total_rx_data)) : |
| 148 | FIFO_DATA_SIZE); |
| 149 | |
| 150 | /* If there are still data left in FIFO we'll read them before |
| 151 | * initializing RX Transfer again |
| 152 | */ |
| 153 | if (rx_data_read < total_rx_data) |
| 154 | return MSM_BOOT_UART_DM_E_SUCCESS; |
| 155 | |
| 156 | msm_boot_uart_dm_init_rx_transfer(base); |
| 157 | total_rx_data = rx_data_read = 0; |
| 158 | |
| 159 | return MSM_BOOT_UART_DM_E_SUCCESS; |
| 160 | } |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 161 | #endif |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 162 | |
Felix Held | e3a1247 | 2020-09-11 15:47:09 +0200 | [diff] [blame] | 163 | void uart_tx_byte(unsigned int idx, unsigned char data) |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 164 | { |
Vadim Bendebury | b67b715 | 2015-01-13 12:46:57 -0800 | [diff] [blame] | 165 | int num_of_chars = 1; |
Martin Roth | 57e8909 | 2019-10-23 21:45:23 -0600 | [diff] [blame] | 166 | unsigned int tx_data = 0; |
Vadim Bendebury | b67b715 | 2015-01-13 12:46:57 -0800 | [diff] [blame] | 167 | void *base = uart_board_param.uart_dm_base; |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 168 | |
Vadim Bendebury | 24a53dd | 2014-05-27 18:03:38 -0700 | [diff] [blame] | 169 | /* Wait until transmit FIFO is empty. */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 170 | while (!(read32(MSM_BOOT_UART_DM_SR(base)) & |
Vadim Bendebury | b67b715 | 2015-01-13 12:46:57 -0800 | [diff] [blame] | 171 | MSM_BOOT_UART_DM_SR_TXEMT)) |
| 172 | udelay(1); |
Vadim Bendebury | 24a53dd | 2014-05-27 18:03:38 -0700 | [diff] [blame] | 173 | /* |
| 174 | * TX FIFO is ready to accept new character(s). First write number of |
| 175 | * characters to be transmitted. |
| 176 | */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 177 | write32(MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(base), num_of_chars); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 178 | |
Vadim Bendebury | 24a53dd | 2014-05-27 18:03:38 -0700 | [diff] [blame] | 179 | /* And now write the character(s) */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 180 | write32(MSM_BOOT_UART_DM_TF(base, 0), tx_data); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 181 | } |
| 182 | |
| 183 | /* |
| 184 | * msm_boot_uart_dm_reset - resets UART controller |
| 185 | * @base: UART controller base address |
| 186 | */ |
Vadim Bendebury | b67b715 | 2015-01-13 12:46:57 -0800 | [diff] [blame] | 187 | static unsigned int msm_boot_uart_dm_reset(void *base) |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 188 | { |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 189 | write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RESET_RX); |
| 190 | write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RESET_TX); |
| 191 | write32(MSM_BOOT_UART_DM_CR(base), |
| 192 | MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT); |
| 193 | write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RES_TX_ERR); |
| 194 | write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RES_STALE_INT); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 195 | |
| 196 | return MSM_BOOT_UART_DM_E_SUCCESS; |
| 197 | } |
| 198 | |
| 199 | /* |
| 200 | * msm_boot_uart_dm_init - initilaizes UART controller |
| 201 | * @uart_dm_base: UART controller base address |
| 202 | */ |
Vadim Bendebury | b67b715 | 2015-01-13 12:46:57 -0800 | [diff] [blame] | 203 | static unsigned int msm_boot_uart_dm_init(void *uart_dm_base) |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 204 | { |
| 205 | /* Configure UART mode registers MR1 and MR2 */ |
| 206 | /* Hardware flow control isn't supported */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 207 | write32(MSM_BOOT_UART_DM_MR1(uart_dm_base), 0x0); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 208 | |
| 209 | /* 8-N-1 configuration: 8 data bits - No parity - 1 stop bit */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 210 | write32(MSM_BOOT_UART_DM_MR2(uart_dm_base), |
| 211 | MSM_BOOT_UART_DM_8_N_1_MODE); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 212 | |
| 213 | /* Configure Interrupt Mask register IMR */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 214 | write32(MSM_BOOT_UART_DM_IMR(uart_dm_base), |
| 215 | MSM_BOOT_UART_DM_IMR_ENABLED); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 216 | |
| 217 | /* |
| 218 | * Configure Tx and Rx watermarks configuration registers |
| 219 | * TX watermark value is set to 0 - interrupt is generated when |
| 220 | * FIFO level is less than or equal to 0 |
| 221 | */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 222 | write32(MSM_BOOT_UART_DM_TFWR(uart_dm_base), |
| 223 | MSM_BOOT_UART_DM_TFW_VALUE); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 224 | |
| 225 | /* RX watermark value */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 226 | write32(MSM_BOOT_UART_DM_RFWR(uart_dm_base), |
| 227 | MSM_BOOT_UART_DM_RFW_VALUE); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 228 | |
| 229 | /* Configure Interrupt Programming Register */ |
| 230 | /* Set initial Stale timeout value */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 231 | write32(MSM_BOOT_UART_DM_IPR(uart_dm_base), |
| 232 | MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 233 | |
| 234 | /* Configure IRDA if required */ |
| 235 | /* Disabling IRDA mode */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 236 | write32(MSM_BOOT_UART_DM_IRDA(uart_dm_base), 0x0); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 237 | |
| 238 | /* Configure hunt character value in HCR register */ |
| 239 | /* Keep it in reset state */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 240 | write32(MSM_BOOT_UART_DM_HCR(uart_dm_base), 0x0); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 241 | |
| 242 | /* |
| 243 | * Configure Rx FIFO base address |
| 244 | * Both TX/RX shares same SRAM and default is half-n-half. |
| 245 | * Sticking with default value now. |
| 246 | * As such RAM size is (2^RAM_ADDR_WIDTH, 32-bit entries). |
| 247 | * We have found RAM_ADDR_WIDTH = 0x7f |
| 248 | */ |
| 249 | |
| 250 | /* Issue soft reset command */ |
| 251 | msm_boot_uart_dm_reset(uart_dm_base); |
| 252 | |
| 253 | /* Enable/Disable Rx/Tx DM interfaces */ |
| 254 | /* Data Mover not currently utilized. */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 255 | write32(MSM_BOOT_UART_DM_DMEN(uart_dm_base), 0x0); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 256 | |
| 257 | /* Enable transmitter */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 258 | write32(MSM_BOOT_UART_DM_CR(uart_dm_base), |
| 259 | MSM_BOOT_UART_DM_CR_TX_ENABLE); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 260 | |
| 261 | /* Initialize Receive Path */ |
| 262 | msm_boot_uart_dm_init_rx_transfer(uart_dm_base); |
| 263 | |
| 264 | return 0; |
| 265 | } |
| 266 | |
| 267 | /** |
Vadim Bendebury | 7c25640 | 2015-01-13 13:07:48 -0800 | [diff] [blame] | 268 | * ipq806x_uart_init - initializes UART |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 269 | * |
| 270 | * Initializes clocks, GPIO and UART controller. |
| 271 | */ |
Felix Held | e3a1247 | 2020-09-11 15:47:09 +0200 | [diff] [blame] | 272 | void uart_init(unsigned int idx) |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 273 | { |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 274 | /* Note int idx isn't used in this driver. */ |
Vadim Bendebury | b67b715 | 2015-01-13 12:46:57 -0800 | [diff] [blame] | 275 | void *dm_base; |
| 276 | void *gsbi_base; |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 277 | |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 278 | dm_base = uart_board_param.uart_dm_base; |
Vadim Bendebury | 7c25640 | 2015-01-13 13:07:48 -0800 | [diff] [blame] | 279 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 280 | if (read32(MSM_BOOT_UART_DM_CSR(dm_base)) == UART_DM_CLK_RX_TX_BIT_RATE) |
Vadim Bendebury | 7c25640 | 2015-01-13 13:07:48 -0800 | [diff] [blame] | 281 | return; /* UART must have been already initialized. */ |
| 282 | |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 283 | gsbi_base = uart_board_param.uart_gsbi_base; |
| 284 | ipq_configure_gpio(uart_board_param.dbg_uart_gpio, |
| 285 | NO_OF_DBG_UART_GPIOS); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 286 | |
| 287 | /* Configure the uart clock */ |
Vadim Bendebury | b67b715 | 2015-01-13 12:46:57 -0800 | [diff] [blame] | 288 | uart_clock_config(uart_board_param.uart_gsbi, |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 289 | uart_board_param.mnd_value.m_value, |
| 290 | uart_board_param.mnd_value.n_value, |
| 291 | uart_board_param.mnd_value.d_value, |
| 292 | 0); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 293 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 294 | write32(GSBI_CTRL_REG(gsbi_base), |
| 295 | GSBI_PROTOCOL_CODE_I2C_UART << GSBI_CTRL_REG_PROTOCOL_CODE_S); |
| 296 | write32(MSM_BOOT_UART_DM_CSR(dm_base), UART_DM_CLK_RX_TX_BIT_RATE); |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 297 | |
Elyes HAOUAS | 809aeee | 2018-08-07 12:14:33 +0200 | [diff] [blame] | 298 | /* Initialize UART_DM */ |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 299 | msm_boot_uart_dm_init(dm_base); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 300 | } |
| 301 | |
Vadim Bendebury | 7c25640 | 2015-01-13 13:07:48 -0800 | [diff] [blame] | 302 | /* for the benefit of non-console uart init */ |
| 303 | void ipq806x_uart_init(void) |
| 304 | { |
| 305 | uart_init(0); |
| 306 | } |
| 307 | |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 308 | #if 0 /* Not used yet */ |
| 309 | uint32_t uartmem_getbaseaddr(void) |
| 310 | { |
Vadim Bendebury | b67b715 | 2015-01-13 12:46:57 -0800 | [diff] [blame] | 311 | return (uint32_t)uart_board_param.uart_dm_base; |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 312 | } |
| 313 | #endif |
| 314 | |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 315 | /** |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 316 | * uart_tx_flush - transmits a string of data |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 317 | * @s: string to transmit |
| 318 | */ |
Felix Held | e3a1247 | 2020-09-11 15:47:09 +0200 | [diff] [blame] | 319 | void uart_tx_flush(unsigned int idx) |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 320 | { |
Vadim Bendebury | b67b715 | 2015-01-13 12:46:57 -0800 | [diff] [blame] | 321 | void *base = uart_board_param.uart_dm_base; |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 322 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 323 | while (!(read32(MSM_BOOT_UART_DM_SR(base)) & |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 324 | MSM_BOOT_UART_DM_SR_TXEMT)) |
| 325 | ; |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 326 | } |
| 327 | |
| 328 | /** |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 329 | * uart_can_rx_byte - checks if data available for reading |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 330 | * |
| 331 | * Returns 1 if data available, 0 otherwise |
| 332 | */ |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 333 | #if 0 /* Not used yet */ |
| 334 | int uart_can_rx_byte(void) |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 335 | { |
| 336 | /* Return if data is already read */ |
| 337 | if (valid_data) |
| 338 | return 1; |
| 339 | |
| 340 | /* Read data from the FIFO */ |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 341 | if (msm_boot_uart_dm_read(&word, &valid_data, 0) != |
| 342 | MSM_BOOT_UART_DM_E_SUCCESS) |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 343 | return 0; |
| 344 | |
| 345 | return 1; |
| 346 | } |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 347 | #endif |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 348 | |
| 349 | /** |
| 350 | * ipq806x_serial_getc - reads a character |
| 351 | * |
| 352 | * Returns the character read from serial port. |
| 353 | */ |
Felix Held | e3a1247 | 2020-09-11 15:47:09 +0200 | [diff] [blame] | 354 | uint8_t uart_rx_byte(unsigned int idx) |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 355 | { |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 356 | uint8_t byte; |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 357 | |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 358 | #if 0 /* Not used yet */ |
| 359 | while (!uart_can_rx_byte()) { |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 360 | /* wait for incoming data */ |
| 361 | } |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 362 | #endif |
| 363 | byte = (uint8_t)(word & 0xff); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 364 | word = word >> 8; |
| 365 | valid_data--; |
| 366 | |
| 367 | return byte; |
| 368 | } |
Vadim Bendebury | 7c25640 | 2015-01-13 13:07:48 -0800 | [diff] [blame] | 369 | |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 370 | /* TODO: Implement fuction */ |
| 371 | void uart_fill_lb(void *data) |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 372 | { |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 373 | } |