Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2012 The Linux Foundation. All rights reserved. |
| 3 | * Source : APQ8064 LK boot |
| 4 | * |
| 5 | * Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved. |
| 6 | * |
| 7 | * Redistribution and use in source and binary forms, with or without |
| 8 | * modification, are permitted provided that the following conditions |
| 9 | * are met: |
| 10 | * * Redistributions of source code must retain the above copyright |
| 11 | * notice, this list of conditions and the following disclaimer. |
| 12 | * * Redistributions in binary form must reproduce the above copyright |
| 13 | * notice, this list of conditions and the following disclaimer in |
| 14 | * the documentation and/or other materials provided with the |
| 15 | * distribution. |
| 16 | * * Neither the name of Google, Inc. nor the names of its contributors |
| 17 | * may be used to endorse or promote products derived from this |
| 18 | * software without specific prior written permission. |
| 19 | * |
| 20 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 21 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 22 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
| 23 | * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
| 24 | * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 25 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
| 26 | * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS |
| 27 | * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED |
| 28 | * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| 29 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT |
| 30 | * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 31 | * SUCH DAMAGE. |
| 32 | */ |
| 33 | |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 34 | #include <arch/io.h> |
| 35 | #include <boot/coreboot_tables.h> |
| 36 | #include <console/console.h> |
| 37 | #include <delay.h> |
| 38 | #include <clock.h> |
| 39 | #include <gpio.h> |
| 40 | #include <gsbi.h> |
| 41 | #include <console/uart.h> |
| 42 | #include <ipq_uart.h> |
| 43 | #include <stdint.h> |
| 44 | #include <stdlib.h> |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 45 | |
| 46 | #define FIFO_DATA_SIZE 4 |
| 47 | |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 48 | typedef struct { |
| 49 | unsigned uart_dm_base; |
| 50 | unsigned uart_gsbi_base; |
| 51 | unsigned uart_gsbi; |
| 52 | uart_clk_mnd_t mnd_value; |
| 53 | gpio_func_data_t dbg_uart_gpio[NO_OF_DBG_UART_GPIOS]; |
| 54 | } uart_params_t; |
| 55 | |
| 56 | /* |
| 57 | * All constants lifted from u-boot's |
| 58 | * board/qcom/ipq806x_cdp/ipq806x_board_param.h |
| 59 | */ |
| 60 | static const uart_params_t uart_board_param = { |
| 61 | .uart_dm_base = UART4_DM_BASE, |
| 62 | .uart_gsbi_base = UART_GSBI4_BASE, |
| 63 | .uart_gsbi = GSBI_4, |
| 64 | .mnd_value = { 12, 625, 313 }, |
| 65 | .dbg_uart_gpio = { |
| 66 | { |
| 67 | .gpio = 10, |
| 68 | .func = 1, |
| 69 | .dir = GPIO_OUTPUT, |
| 70 | .pull = GPIO_NO_PULL, |
| 71 | .drvstr = GPIO_12MA, |
| 72 | .enable = GPIO_DISABLE |
| 73 | }, |
| 74 | { |
| 75 | .gpio = 11, |
| 76 | .func = 1, |
| 77 | .dir = GPIO_INPUT, |
| 78 | .pull = GPIO_NO_PULL, |
| 79 | .drvstr = GPIO_12MA, |
| 80 | .enable = GPIO_DISABLE |
| 81 | }, |
| 82 | } |
| 83 | }; |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 84 | |
| 85 | static unsigned int msm_boot_uart_dm_init(unsigned int uart_dm_base); |
| 86 | |
| 87 | /* Received data is valid or not */ |
| 88 | static int valid_data = 0; |
| 89 | |
| 90 | /* Received data */ |
| 91 | static unsigned int word = 0; |
| 92 | |
| 93 | /** |
| 94 | * msm_boot_uart_dm_init_rx_transfer - Init Rx transfer |
| 95 | * @uart_dm_base: UART controller base address |
| 96 | */ |
| 97 | static unsigned int msm_boot_uart_dm_init_rx_transfer(unsigned int uart_dm_base) |
| 98 | { |
| 99 | /* Reset receiver */ |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 100 | writel_i(MSM_BOOT_UART_DM_CMD_RESET_RX, |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 101 | MSM_BOOT_UART_DM_CR(uart_dm_base)); |
| 102 | |
| 103 | /* Enable receiver */ |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 104 | writel_i(MSM_BOOT_UART_DM_CR_RX_ENABLE, |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 105 | MSM_BOOT_UART_DM_CR(uart_dm_base)); |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 106 | writel_i(MSM_BOOT_UART_DM_DMRX_DEF_VALUE, |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 107 | MSM_BOOT_UART_DM_DMRX(uart_dm_base)); |
| 108 | |
| 109 | /* Clear stale event */ |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 110 | writel_i(MSM_BOOT_UART_DM_CMD_RES_STALE_INT, |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 111 | MSM_BOOT_UART_DM_CR(uart_dm_base)); |
| 112 | |
| 113 | /* Enable stale event */ |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 114 | writel_i(MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT, |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 115 | MSM_BOOT_UART_DM_CR(uart_dm_base)); |
| 116 | |
| 117 | return MSM_BOOT_UART_DM_E_SUCCESS; |
| 118 | } |
| 119 | |
| 120 | /** |
| 121 | * msm_boot_uart_dm_read - reads a word from the RX FIFO. |
| 122 | * @data: location where the read data is stored |
| 123 | * @count: no of valid data in the FIFO |
| 124 | * @wait: indicates blocking call or not blocking call |
| 125 | * |
| 126 | * Reads a word from the RX FIFO. If no data is available blocks if |
| 127 | * @wait is true, else returns %MSM_BOOT_UART_DM_E_RX_NOT_READY. |
| 128 | */ |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 129 | #if 0 /* Not used yet */ |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 130 | static unsigned int |
| 131 | msm_boot_uart_dm_read(unsigned int *data, int *count, int wait) |
| 132 | { |
| 133 | static int total_rx_data = 0; |
| 134 | static int rx_data_read = 0; |
| 135 | unsigned int base = 0; |
| 136 | uint32_t status_reg; |
| 137 | |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 138 | base = uart_board_param.uart_dm_base; |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 139 | |
| 140 | if (data == NULL) |
| 141 | return MSM_BOOT_UART_DM_E_INVAL; |
| 142 | |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 143 | status_reg = readl_i(MSM_BOOT_UART_DM_MISR(base)); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 144 | |
| 145 | /* Check for DM_RXSTALE for RX transfer to finish */ |
| 146 | while (!(status_reg & MSM_BOOT_UART_DM_RXSTALE)) { |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 147 | status_reg = readl_i(MSM_BOOT_UART_DM_MISR(base)); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 148 | if (!wait) |
| 149 | return MSM_BOOT_UART_DM_E_RX_NOT_READY; |
| 150 | } |
| 151 | |
| 152 | /* Check for Overrun error. We'll just reset Error Status */ |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 153 | if (readl_i(MSM_BOOT_UART_DM_SR(base)) & |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 154 | MSM_BOOT_UART_DM_SR_UART_OVERRUN) { |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 155 | writel_i(MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT, |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 156 | MSM_BOOT_UART_DM_CR(base)); |
| 157 | total_rx_data = rx_data_read = 0; |
| 158 | msm_boot_uart_dm_init(base); |
| 159 | return MSM_BOOT_UART_DM_E_RX_NOT_READY; |
| 160 | } |
| 161 | |
| 162 | /* Read UART_DM_RX_TOTAL_SNAP for actual number of bytes received */ |
| 163 | if (total_rx_data == 0) |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 164 | total_rx_data = readl_i(MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base)); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 165 | |
| 166 | /* Data available in FIFO; read a word. */ |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 167 | *data = readl_i(MSM_BOOT_UART_DM_RF(base, 0)); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 168 | |
| 169 | /* WAR for http://prism/CR/548280 */ |
| 170 | if (*data == 0) { |
| 171 | return MSM_BOOT_UART_DM_E_RX_NOT_READY; |
| 172 | } |
| 173 | |
| 174 | /* increment the total count of chars we've read so far */ |
| 175 | rx_data_read += FIFO_DATA_SIZE; |
| 176 | |
| 177 | /* actual count of valid data in word */ |
| 178 | *count = ((total_rx_data < rx_data_read) ? |
| 179 | (FIFO_DATA_SIZE - (rx_data_read - total_rx_data)) : |
| 180 | FIFO_DATA_SIZE); |
| 181 | |
| 182 | /* If there are still data left in FIFO we'll read them before |
| 183 | * initializing RX Transfer again |
| 184 | */ |
| 185 | if (rx_data_read < total_rx_data) |
| 186 | return MSM_BOOT_UART_DM_E_SUCCESS; |
| 187 | |
| 188 | msm_boot_uart_dm_init_rx_transfer(base); |
| 189 | total_rx_data = rx_data_read = 0; |
| 190 | |
| 191 | return MSM_BOOT_UART_DM_E_SUCCESS; |
| 192 | } |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 193 | #endif |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 194 | |
Vadim Bendebury | 24a53dd | 2014-05-27 18:03:38 -0700 | [diff] [blame^] | 195 | void uart_tx_byte(int idx, unsigned char data) |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 196 | { |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 197 | unsigned int base = uart_board_param.uart_dm_base; |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 198 | |
Vadim Bendebury | 24a53dd | 2014-05-27 18:03:38 -0700 | [diff] [blame^] | 199 | /* Wait until transmit FIFO is empty. */ |
| 200 | while (!(readl_i(MSM_BOOT_UART_DM_SR(base)) & |
| 201 | MSM_BOOT_UART_DM_SR_TXEMT)) |
| 202 | udelay(1); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 203 | |
Vadim Bendebury | 24a53dd | 2014-05-27 18:03:38 -0700 | [diff] [blame^] | 204 | /* |
| 205 | * TX FIFO is ready to accept new character(s). First write number of |
| 206 | * characters to be transmitted. |
| 207 | */ |
| 208 | writel_i(1, MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(base)); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 209 | |
Vadim Bendebury | 24a53dd | 2014-05-27 18:03:38 -0700 | [diff] [blame^] | 210 | /* And now write the character(s) */ |
| 211 | writel_i(data, MSM_BOOT_UART_DM_TF(base, 0)); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 212 | } |
| 213 | |
| 214 | /* |
| 215 | * msm_boot_uart_dm_reset - resets UART controller |
| 216 | * @base: UART controller base address |
| 217 | */ |
| 218 | static unsigned int msm_boot_uart_dm_reset(unsigned int base) |
| 219 | { |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 220 | writel_i(MSM_BOOT_UART_DM_CMD_RESET_RX, MSM_BOOT_UART_DM_CR(base)); |
| 221 | writel_i(MSM_BOOT_UART_DM_CMD_RESET_TX, MSM_BOOT_UART_DM_CR(base)); |
| 222 | writel_i(MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT, |
| 223 | MSM_BOOT_UART_DM_CR(base)); |
| 224 | writel_i(MSM_BOOT_UART_DM_CMD_RES_TX_ERR, MSM_BOOT_UART_DM_CR(base)); |
| 225 | writel_i(MSM_BOOT_UART_DM_CMD_RES_STALE_INT, MSM_BOOT_UART_DM_CR(base)); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 226 | |
| 227 | return MSM_BOOT_UART_DM_E_SUCCESS; |
| 228 | } |
| 229 | |
| 230 | /* |
| 231 | * msm_boot_uart_dm_init - initilaizes UART controller |
| 232 | * @uart_dm_base: UART controller base address |
| 233 | */ |
| 234 | static unsigned int msm_boot_uart_dm_init(unsigned int uart_dm_base) |
| 235 | { |
| 236 | /* Configure UART mode registers MR1 and MR2 */ |
| 237 | /* Hardware flow control isn't supported */ |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 238 | writel_i(0x0, MSM_BOOT_UART_DM_MR1(uart_dm_base)); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 239 | |
| 240 | /* 8-N-1 configuration: 8 data bits - No parity - 1 stop bit */ |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 241 | writel_i(MSM_BOOT_UART_DM_8_N_1_MODE, |
| 242 | MSM_BOOT_UART_DM_MR2(uart_dm_base)); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 243 | |
| 244 | /* Configure Interrupt Mask register IMR */ |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 245 | writel_i(MSM_BOOT_UART_DM_IMR_ENABLED, |
| 246 | MSM_BOOT_UART_DM_IMR(uart_dm_base)); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 247 | |
| 248 | /* |
| 249 | * Configure Tx and Rx watermarks configuration registers |
| 250 | * TX watermark value is set to 0 - interrupt is generated when |
| 251 | * FIFO level is less than or equal to 0 |
| 252 | */ |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 253 | writel_i(MSM_BOOT_UART_DM_TFW_VALUE, |
| 254 | MSM_BOOT_UART_DM_TFWR(uart_dm_base)); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 255 | |
| 256 | /* RX watermark value */ |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 257 | writel_i(MSM_BOOT_UART_DM_RFW_VALUE, |
| 258 | MSM_BOOT_UART_DM_RFWR(uart_dm_base)); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 259 | |
| 260 | /* Configure Interrupt Programming Register */ |
| 261 | /* Set initial Stale timeout value */ |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 262 | writel_i(MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB, |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 263 | MSM_BOOT_UART_DM_IPR(uart_dm_base)); |
| 264 | |
| 265 | /* Configure IRDA if required */ |
| 266 | /* Disabling IRDA mode */ |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 267 | writel_i(0x0, MSM_BOOT_UART_DM_IRDA(uart_dm_base)); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 268 | |
| 269 | /* Configure hunt character value in HCR register */ |
| 270 | /* Keep it in reset state */ |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 271 | writel_i(0x0, MSM_BOOT_UART_DM_HCR(uart_dm_base)); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 272 | |
| 273 | /* |
| 274 | * Configure Rx FIFO base address |
| 275 | * Both TX/RX shares same SRAM and default is half-n-half. |
| 276 | * Sticking with default value now. |
| 277 | * As such RAM size is (2^RAM_ADDR_WIDTH, 32-bit entries). |
| 278 | * We have found RAM_ADDR_WIDTH = 0x7f |
| 279 | */ |
| 280 | |
| 281 | /* Issue soft reset command */ |
| 282 | msm_boot_uart_dm_reset(uart_dm_base); |
| 283 | |
| 284 | /* Enable/Disable Rx/Tx DM interfaces */ |
| 285 | /* Data Mover not currently utilized. */ |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 286 | writel_i(0x0, MSM_BOOT_UART_DM_DMEN(uart_dm_base)); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 287 | |
| 288 | /* Enable transmitter */ |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 289 | writel_i(MSM_BOOT_UART_DM_CR_TX_ENABLE, |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 290 | MSM_BOOT_UART_DM_CR(uart_dm_base)); |
| 291 | |
| 292 | /* Initialize Receive Path */ |
| 293 | msm_boot_uart_dm_init_rx_transfer(uart_dm_base); |
| 294 | |
| 295 | return 0; |
| 296 | } |
| 297 | |
| 298 | /** |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 299 | * uart_init - initializes UART |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 300 | * |
| 301 | * Initializes clocks, GPIO and UART controller. |
| 302 | */ |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 303 | void uart_init(int idx) |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 304 | { |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 305 | /* Note int idx isn't used in this driver. */ |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 306 | unsigned int dm_base, gsbi_base; |
| 307 | |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 308 | dm_base = uart_board_param.uart_dm_base; |
| 309 | gsbi_base = uart_board_param.uart_gsbi_base; |
| 310 | ipq_configure_gpio(uart_board_param.dbg_uart_gpio, |
| 311 | NO_OF_DBG_UART_GPIOS); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 312 | |
| 313 | /* Configure the uart clock */ |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 314 | uart_clock_config(uart_board_param.uart_gsbi, |
| 315 | uart_board_param.mnd_value.m_value, |
| 316 | uart_board_param.mnd_value.n_value, |
| 317 | uart_board_param.mnd_value.d_value, |
| 318 | 0); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 319 | |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 320 | writel_i(GSBI_PROTOCOL_CODE_I2C_UART << |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 321 | GSBI_CTRL_REG_PROTOCOL_CODE_S, |
| 322 | GSBI_CTRL_REG(gsbi_base)); |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 323 | writel_i(UART_DM_CLK_RX_TX_BIT_RATE, MSM_BOOT_UART_DM_CSR(dm_base)); |
| 324 | |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 325 | /* Intialize UART_DM */ |
| 326 | msm_boot_uart_dm_init(dm_base); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 327 | } |
| 328 | |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 329 | #if 0 /* Not used yet */ |
| 330 | uint32_t uartmem_getbaseaddr(void) |
| 331 | { |
| 332 | return uart_board_param.uart_dm_base; |
| 333 | } |
| 334 | #endif |
| 335 | |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 336 | /** |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 337 | * uart_tx_flush - transmits a string of data |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 338 | * @s: string to transmit |
| 339 | */ |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 340 | void uart_tx_flush(int idx) |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 341 | { |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 342 | unsigned int base = uart_board_param.uart_dm_base; |
| 343 | |
| 344 | while (!(readl_i(MSM_BOOT_UART_DM_SR(base)) & |
| 345 | MSM_BOOT_UART_DM_SR_TXEMT)) |
| 346 | ; |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 347 | } |
| 348 | |
| 349 | /** |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 350 | * uart_can_rx_byte - checks if data available for reading |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 351 | * |
| 352 | * Returns 1 if data available, 0 otherwise |
| 353 | */ |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 354 | #if 0 /* Not used yet */ |
| 355 | int uart_can_rx_byte(void) |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 356 | { |
| 357 | /* Return if data is already read */ |
| 358 | if (valid_data) |
| 359 | return 1; |
| 360 | |
| 361 | /* Read data from the FIFO */ |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 362 | if (msm_boot_uart_dm_read(&word, &valid_data, 0) != |
| 363 | MSM_BOOT_UART_DM_E_SUCCESS) |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 364 | return 0; |
| 365 | |
| 366 | return 1; |
| 367 | } |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 368 | #endif |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 369 | |
| 370 | /** |
| 371 | * ipq806x_serial_getc - reads a character |
| 372 | * |
| 373 | * Returns the character read from serial port. |
| 374 | */ |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 375 | uint8_t uart_rx_byte(int idx) |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 376 | { |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 377 | uint8_t byte; |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 378 | |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 379 | #if 0 /* Not used yet */ |
| 380 | while (!uart_can_rx_byte()) { |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 381 | /* wait for incoming data */ |
| 382 | } |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 383 | #endif |
| 384 | byte = (uint8_t)(word & 0xff); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 385 | word = word >> 8; |
| 386 | valid_data--; |
| 387 | |
| 388 | return byte; |
| 389 | } |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 390 | #ifndef __PRE_RAM__ |
| 391 | /* TODO: Implement fuction */ |
| 392 | void uart_fill_lb(void *data) |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 393 | { |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 394 | } |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 395 | #endif |