| Angel Pons | a2ee761 | 2020-04-04 18:51:15 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| Julius Werner | ec5e5e0 | 2014-08-20 15:29:56 -0700 | [diff] [blame] | 2 | |
| 3 | #include <memlayout.h> |
| Julius Werner | ec5e5e0 | 2014-08-20 15:29:56 -0700 | [diff] [blame] | 4 | |
| 5 | #include <arch/header.ld> |
| 6 | |
| 7 | /* |
| 8 | * Note: The BootROM uses the address range [0x4000_0000:0x4000_E000) itself, |
| 9 | * so the bootblock loading address must be placed after that. After the |
| 10 | * handoff that area may be reclaimed for other uses, e.g. CBFS cache. |
| 11 | */ |
| 12 | |
| 13 | SECTIONS |
| 14 | { |
| 15 | SRAM_START(0x40000000) |
| 16 | TTB(0x40000000, 16K + 32) |
| Philipp Deppenwiese | c9b7d1f | 2018-11-10 00:35:02 +0100 | [diff] [blame] | 17 | PRERAM_CBMEM_CONSOLE(0x40004020, 6K - 32) |
| Julius Werner | cefe89e | 2019-11-06 19:29:44 -0800 | [diff] [blame] | 18 | FMAP_CACHE(0x40005800, 2K) |
| Julius Werner | baf27db | 2019-10-02 17:28:56 -0700 | [diff] [blame^] | 19 | CBFS_MCACHE(0x40006000, 8K) |
| 20 | PRERAM_CBFS_CACHE(0x40008000, 6K) |
| Joel Kitching | 0097f55 | 2019-02-21 12:36:55 +0800 | [diff] [blame] | 21 | VBOOT2_WORK(0x40009800, 12K) |
| Bill XIE | c79e96b | 2019-08-22 20:28:36 +0800 | [diff] [blame] | 22 | TPM_TCPA_LOG(0x4000D800, 2K) |
| Julius Werner | ec5e5e0 | 2014-08-20 15:29:56 -0700 | [diff] [blame] | 23 | STACK(0x4000E000, 8K) |
| Patrick Rudolph | 5ed02e1 | 2018-10-02 13:11:35 +0200 | [diff] [blame] | 24 | BOOTBLOCK(0x40010000, 30K) |
| 25 | VERSTAGE(0x40017800, 72K) |
| 26 | ROMSTAGE(0x40029800, 89K) |
| Julius Werner | f545208 | 2016-02-17 16:12:46 -0800 | [diff] [blame] | 27 | TIMESTAMP(0x4003FC00, 1K) |
| Julius Werner | ec5e5e0 | 2014-08-20 15:29:56 -0700 | [diff] [blame] | 28 | SRAM_END(0x40040000) |
| 29 | |
| 30 | DRAM_START(0x80000000) |
| 31 | POSTRAM_CBFS_CACHE(0x80100000, 1M) |
| 32 | RAMSTAGE(0x80200000, 128K) |
| 33 | DMA_COHERENT(0x90000000, 2M) |
| 34 | } |