blob: 5bab362396168c15dda585bdaf3167ab7a121565 [file] [log] [blame]
Julius Wernerec5e5e02014-08-20 15:29:56 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright 2014 Google Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Julius Wernerec5e5e02014-08-20 15:29:56 -070014 */
15
16#include <memlayout.h>
Julius Wernerec5e5e02014-08-20 15:29:56 -070017
18#include <arch/header.ld>
19
20/*
21 * Note: The BootROM uses the address range [0x4000_0000:0x4000_E000) itself,
22 * so the bootblock loading address must be placed after that. After the
23 * handoff that area may be reclaimed for other uses, e.g. CBFS cache.
24 */
25
26SECTIONS
27{
28 SRAM_START(0x40000000)
29 TTB(0x40000000, 16K + 32)
30 PRERAM_CBMEM_CONSOLE(0x40004020, 8K - 32)
31 PRERAM_CBFS_CACHE(0x40006000, 16K)
32 VBOOT2_WORK(0x4000A000, 16K)
33 STACK(0x4000E000, 8K)
34 BOOTBLOCK(0x40010000, 24K)
35 VERSTAGE(0x40016000, 72K)
Julius Wernerf5452082016-02-17 16:12:46 -080036 ROMSTAGE(0x40028000, 95K)
37 TIMESTAMP(0x4003FC00, 1K)
Julius Wernerec5e5e02014-08-20 15:29:56 -070038 SRAM_END(0x40040000)
39
40 DRAM_START(0x80000000)
41 POSTRAM_CBFS_CACHE(0x80100000, 1M)
42 RAMSTAGE(0x80200000, 128K)
43 DMA_COHERENT(0x90000000, 2M)
44}