| Julius Werner | ec5e5e0 | 2014-08-20 15:29:56 -0700 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2014 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #include <memlayout.h> |
| 21 | #include <vendorcode/google/chromeos/memlayout.h> |
| 22 | |
| 23 | #include <arch/header.ld> |
| 24 | |
| 25 | /* |
| 26 | * Note: The BootROM uses the address range [0x4000_0000:0x4000_E000) itself, |
| 27 | * so the bootblock loading address must be placed after that. After the |
| 28 | * handoff that area may be reclaimed for other uses, e.g. CBFS cache. |
| 29 | */ |
| 30 | |
| 31 | SECTIONS |
| 32 | { |
| 33 | SRAM_START(0x40000000) |
| 34 | TTB(0x40000000, 16K + 32) |
| 35 | PRERAM_CBMEM_CONSOLE(0x40004020, 8K - 32) |
| 36 | PRERAM_CBFS_CACHE(0x40006000, 16K) |
| 37 | VBOOT2_WORK(0x4000A000, 16K) |
| 38 | STACK(0x4000E000, 8K) |
| 39 | BOOTBLOCK(0x40010000, 24K) |
| 40 | VERSTAGE(0x40016000, 72K) |
| 41 | ROMSTAGE(0x40028000, 96K) |
| 42 | SRAM_END(0x40040000) |
| 43 | |
| 44 | DRAM_START(0x80000000) |
| 45 | POSTRAM_CBFS_CACHE(0x80100000, 1M) |
| 46 | RAMSTAGE(0x80200000, 128K) |
| 47 | DMA_COHERENT(0x90000000, 2M) |
| 48 | } |