| Angel Pons | 5f249e6 | 2020-04-04 18:51:01 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| David Hendricks | 8cbd569 | 2017-12-01 20:49:48 -0800 | [diff] [blame] | 2 | |
| 3 | #include <memlayout.h> |
| 4 | #include <soc/addressmap.h> |
| 5 | #include <arch/header.ld> |
| 6 | |
| 7 | SECTIONS |
| 8 | { |
| 9 | DRAM_START(0x00000000) |
| Patrick Rudolph | 5cdaa33 | 2018-04-20 14:43:21 +0200 | [diff] [blame] | 10 | /* Secure region 0 - 1MiB */ |
| Ting Shen | dff29e0 | 2019-01-28 18:15:00 +0800 | [diff] [blame] | 11 | BL31(0, 0xe0000) |
| Patrick Rudolph | 5cdaa33 | 2018-04-20 14:43:21 +0200 | [diff] [blame] | 12 | REGION(sff8104, 0xe0000, 0x20000, 0x1000) |
| David Hendricks | 8cbd569 | 2017-12-01 20:49:48 -0800 | [diff] [blame] | 13 | |
| Patrick Rudolph | 5cdaa33 | 2018-04-20 14:43:21 +0200 | [diff] [blame] | 14 | /* Insecure region 1MiB - TOP OF DRAM */ |
| David Hendricks | 8cbd569 | 2017-12-01 20:49:48 -0800 | [diff] [blame] | 15 | /* bootblock-custom.S does setup CAR from SRAM_START to SRAM_END */ |
| 16 | SRAM_START(BOOTROM_OFFSET) |
| Philipp Deppenwiese | 31a4700c | 2018-08-10 16:07:23 -0700 | [diff] [blame] | 17 | |
| David Hendricks | 8cbd569 | 2017-12-01 20:49:48 -0800 | [diff] [blame] | 18 | STACK(BOOTROM_OFFSET, 16K) |
| 19 | TIMESTAMP(BOOTROM_OFFSET + 0x4000, 4K) |
| Julius Werner | 8245bd2 | 2019-12-04 20:32:15 -0800 | [diff] [blame] | 20 | PRERAM_CBFS_CACHE(BOOTROM_OFFSET + 0x6000, 6K) |
| 21 | FMAP_CACHE(BOOTROM_OFFSET + 0x7800, 2K) |
| David Hendricks | 8cbd569 | 2017-12-01 20:49:48 -0800 | [diff] [blame] | 22 | PRERAM_CBMEM_CONSOLE(BOOTROM_OFFSET + 0x8000, 8K) |
| Julius Werner | baf27db | 2019-10-02 17:28:56 -0700 | [diff] [blame^] | 23 | BOOTBLOCK(BOOTROM_OFFSET + 0x20000, 56K) |
| 24 | CBFS_MCACHE(BOOTROM_OFFSET + 0x2e000, 8K) |
| Philipp Deppenwiese | 31a4700c | 2018-08-10 16:07:23 -0700 | [diff] [blame] | 25 | VBOOT2_WORK(BOOTROM_OFFSET + 0x30000, 12K) |
| Bill XIE | c79e96b | 2019-08-22 20:28:36 +0800 | [diff] [blame] | 26 | TPM_TCPA_LOG(BOOTROM_OFFSET + 0x33000, 2K) |
| Philipp Deppenwiese | c9b7d1f | 2018-11-10 00:35:02 +0100 | [diff] [blame] | 27 | VERSTAGE(BOOTROM_OFFSET + 0x33800, 50K) |
| David Hendricks | 8cbd569 | 2017-12-01 20:49:48 -0800 | [diff] [blame] | 28 | ROMSTAGE(BOOTROM_OFFSET + 0x40000, 256K) |
| Philipp Deppenwiese | 31a4700c | 2018-08-10 16:07:23 -0700 | [diff] [blame] | 29 | |
| David Hendricks | 8cbd569 | 2017-12-01 20:49:48 -0800 | [diff] [blame] | 30 | SRAM_END(BOOTROM_OFFSET + 0x80000) |
| Philipp Deppenwiese | 31a4700c | 2018-08-10 16:07:23 -0700 | [diff] [blame] | 31 | |
| Patrick Rudolph | 06c7d64 | 2018-03-26 15:54:41 +0200 | [diff] [blame] | 32 | TTB(BOOTROM_OFFSET + 0x80000, 512K) |
| 33 | RAMSTAGE(BOOTROM_OFFSET + 0x100000, 512K) |
| Patrick Rudolph | 88f81af | 2018-04-11 11:40:55 +0200 | [diff] [blame] | 34 | /* Stack for secondary CPUs */ |
| 35 | REGION(stack_sec, BOOTROM_OFFSET + 0x180000, |
| 36 | CONFIG_MAX_CPUS * CONFIG_STACK_SIZE, 0x1000) |
| David Hendricks | 8cbd569 | 2017-12-01 20:49:48 -0800 | [diff] [blame] | 37 | |
| 38 | /* Leave some space for the payload */ |
| 39 | POSTRAM_CBFS_CACHE(0x2000000, 16M) |
| 40 | } |