cbfs: Enable CBFS mcache on most chipsets
This patch flips the default of CONFIG_NO_CBFS_MCACHE so the feature is
enabled by default. Some older chipsets with insufficient SRAM/CAR space
still have it explicitly disabled. All others get the new section added
to their memlayout... 8K seems like a sane default to start with.
Change-Id: I0abd1c813aece6e78fb883f292ce6c9319545c44
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
diff --git a/src/soc/cavium/cn81xx/memlayout.ld b/src/soc/cavium/cn81xx/memlayout.ld
index 79673c9..0257b23 100644
--- a/src/soc/cavium/cn81xx/memlayout.ld
+++ b/src/soc/cavium/cn81xx/memlayout.ld
@@ -20,7 +20,8 @@
PRERAM_CBFS_CACHE(BOOTROM_OFFSET + 0x6000, 6K)
FMAP_CACHE(BOOTROM_OFFSET + 0x7800, 2K)
PRERAM_CBMEM_CONSOLE(BOOTROM_OFFSET + 0x8000, 8K)
- BOOTBLOCK(BOOTROM_OFFSET + 0x20000, 64K)
+ BOOTBLOCK(BOOTROM_OFFSET + 0x20000, 56K)
+ CBFS_MCACHE(BOOTROM_OFFSET + 0x2e000, 8K)
VBOOT2_WORK(BOOTROM_OFFSET + 0x30000, 12K)
TPM_TCPA_LOG(BOOTROM_OFFSET + 0x33000, 2K)
VERSTAGE(BOOTROM_OFFSET + 0x33800, 50K)