Gitiles
Code Review Sign In
review.coreboot.org / coreboot / baf27dbaeb1f6791ebfc416f2175507686bd88ac / . / src / soc / amd / common / block / cpu / noncar / memlayout_x86.ld
blob: bf101e33ee2895259a0a6b37d56f3eb0a38cf958 [file] [log] [blame]
Martin Rothc7acf162020-05-28 00:44:50 -0600[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
2
3#include <memlayout.h>
4#include <arch/header.ld>
Martin Roth0c12abe2020-06-26 08:40:56 -0600[diff] [blame]5#include <soc/psp_transfer.h>
Martin Rothc7acf162020-05-28 00:44:50 -0600[diff] [blame]6
7#define EARLY_RESERVED_DRAM_START(addr) SYMBOL(early_reserved_dram, addr)
8#define EARLY_RESERVED_DRAM_END(addr) SYMBOL(eearly_reserved_dram, addr)
9
10#define PSP_SHAREDMEM_DRAM_START(addr) SYMBOL(psp_sharedmem_dram, addr)
11#define PSP_SHAREDMEM_DRAM_END(addr) SYMBOL(epsp_sharedmem_dram, addr)
12
13/*
14 *
15 * +--------------------------------+
16 * | |
17 * | |
18 * | |
19 * | |
20 * | |
21 * | |
22 * | |
23 * reserved_dram_end +--------------------------------+
24 * | |
25 * | verstage (if reqd) |
26 * | (VERSTAGE_SIZE) |
27 * +--------------------------------+ VERSTAGE_ADDR
28 * | |
29 * | FSP-M |
30 * | (FSP_M_SIZE) |
31 * +--------------------------------+ FSP_M_ADDR
32 * | |X86_RESET_VECTOR = ROMSTAGE_ADDR + ROMSTAGE_SIZE - 0x10
33 * | romstage |
34 * | (ROMSTAGE_SIZE) |
35 * +--------------------------------+ ROMSTAGE_ADDR
36 * | bootblock |
37 * | (C_ENV_BOOTBLOCK_SIZE) |
38 * +--------------------------------+ BOOTBLOCK_ADDR
39 * | Unused hole |
40 * +--------------------------------+
41 * | FMAP cache (FMAP_SIZE) |
Julius Wernerbaf27db2019-10-02 17:28:56 -0700[diff] [blame^]42 * +--------------------------------+
43 * | CBFS mcache (CBFS_MCACHE_SIZE) |
Josie Nordrum5ae96aa2020-09-01 16:31:57 -0600[diff] [blame]44 * +--------------------------------+ PSP_SHAREDMEM_BASE + 0x40 + VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200
Martin Rothc7acf162020-05-28 00:44:50 -0600[diff] [blame]45 * | Early Timestamp region (512B) |
Josie Nordrum5ae96aa2020-09-01 16:31:57 -0600[diff] [blame]46 * +--------------------------------+ PSP_SHAREDMEM_BASE + 0x40 + VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE + PRERAM_CBMEM_CONSOLE_SIZE
Martin Rothc7acf162020-05-28 00:44:50 -0600[diff] [blame]47 * | Preram CBMEM console |
48 * | (PRERAM_CBMEM_CONSOLE_SIZE) |
Josie Nordrum5ae96aa2020-09-01 16:31:57 -0600[diff] [blame]49 * +--------------------------------+ PSP_SHAREDMEM_BASE + 0x40 + VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE
Martin Rothc7acf162020-05-28 00:44:50 -0600[diff] [blame]50 * | PSP shared (vboot workbuf) |
Josie Nordrum5ae96aa2020-09-01 16:31:57 -0600[diff] [blame]51 * |(VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE) |
Martin Roth0c12abe2020-06-26 08:40:56 -0600[diff] [blame]52 * +--------------------------------+ PSP_SHAREDMEM_BASE + 0x40
53 * | Transfer Info Structure |
Martin Rothc7acf162020-05-28 00:44:50 -0600[diff] [blame]54 * +--------------------------------+ PSP_SHAREDMEM_BASE
55 * | APOB (64KiB) |
56 * +--------------------------------+ PSP_APOB_DRAM_ADDRESS
57 * | Early BSP stack |
58 * | (EARLYRAM_BSP_STACK_SIZE) |
59 * reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE
60 * | DRAM |
61 * +--------------------------------+ 0x100000
62 * | Option ROM |
63 * +--------------------------------+ 0xc0000
64 * | Legacy VGA |
65 * +--------------------------------+ 0xa0000
66 * | DRAM |
67 * +--------------------------------+ 0x0
68 */
69SECTIONS
70{
71 DRAM_START(0x0)
72
73 EARLY_RESERVED_DRAM_START(CONFIG_EARLY_RESERVED_DRAM_BASE)
74
75 EARLYRAM_STACK(., CONFIG_EARLYRAM_BSP_STACK_SIZE)
76 REGION(apob, CONFIG_PSP_APOB_DRAM_ADDRESS, 64K, 1)
77
78#if CONFIG(VBOOT)
79 PSP_SHAREDMEM_DRAM_START(CONFIG_PSP_SHAREDMEM_BASE)
Martin Rothc7acf162020-05-28 00:44:50 -0600[diff] [blame]80#endif
81
Martin Roth89815c92020-10-23 15:24:30 -0600[diff] [blame]82#include "memlayout_transfer_buffer.inc"
83
Martin Roth0c12abe2020-06-26 08:40:56 -0600[diff] [blame]84#if CONFIG(VBOOT)
Josie Nordrum5ae96aa2020-09-01 16:31:57 -0600[diff] [blame]85 PSP_SHAREDMEM_DRAM_END(CONFIG_PSP_SHAREDMEM_BASE + CONFIG_PSP_SHAREDMEM_SIZE)
Martin Roth0c12abe2020-06-26 08:40:56 -0600[diff] [blame]86#endif
Martin Rothc7acf162020-05-28 00:44:50 -0600[diff] [blame]87 _ = ASSERT((CONFIG_BOOTBLOCK_ADDR + CONFIG_C_ENV_BOOTBLOCK_SIZE - 0x10) == CONFIG_X86_RESET_VECTOR, "Reset vector should be -0x10 from end of bootblock");
88 _ = ASSERT(CONFIG_BOOTBLOCK_ADDR == ((CONFIG_BOOTBLOCK_ADDR + 0xFFFF) & 0xFFFF0000), "Bootblock must be 16 bit aligned");
89 BOOTBLOCK(CONFIG_BOOTBLOCK_ADDR, CONFIG_C_ENV_BOOTBLOCK_SIZE)
90 ROMSTAGE(CONFIG_ROMSTAGE_ADDR, CONFIG_ROMSTAGE_SIZE)
91 REGION(fspm, CONFIG_FSP_M_ADDR, CONFIG_FSP_M_SIZE, 1)
92#if CONFIG(VBOOT_SEPARATE_VERSTAGE)
93 VERSTAGE(CONFIG_VERSTAGE_ADDR, CONFIG_VERSTAGE_SIZE)
94#endif
95
96 EARLY_RESERVED_DRAM_END(.)
97
98 RAMSTAGE(CONFIG_RAMBASE, 8M)
99}
100
101#if ENV_BOOTBLOCK
Furquan Shaikh1eaf64c2020-07-17 14:35:26 -0700[diff] [blame]102
103gdtptr16_offset = gdtptr16 & 0xffff;
104nullidt_offset = nullidt & 0xffff;
105
106SECTIONS {
107 /* Trigger an error if I have an unusable start address */
108 _TOO_LOW = CONFIG_X86_RESET_VECTOR - 0xfff0;
109 _bogus = ASSERT(_start16bit >= _TOO_LOW, "_start16bit too low. Please report.");
110
111 . = CONFIG_X86_RESET_VECTOR;
112 .reset . : {
113 *(.reset);
114 . = 15;
115 BYTE(0x00);
116 }
117}
Martin Rothc7acf162020-05-28 00:44:50 -0600[diff] [blame]118#endif /* ENV_BOOTBLOCK */