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review.coreboot.org / coreboot / 5ae96aa17160d9469783540af1e326ba01b82c3e / . / src / soc / amd / picasso / memlayout_x86.ld
blob: 00cdde6488a1a3cf10be4c0d0b1bd884494ccc18 [file] [log] [blame]
Martin Rothc7acf162020-05-28 00:44:50 -0600[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
2
3#include <memlayout.h>
4#include <arch/header.ld>
Martin Roth0c12abe2020-06-26 08:40:56 -0600[diff] [blame]5#include <soc/psp_transfer.h>
Martin Rothc7acf162020-05-28 00:44:50 -0600[diff] [blame]6
7#define EARLY_RESERVED_DRAM_START(addr) SYMBOL(early_reserved_dram, addr)
8#define EARLY_RESERVED_DRAM_END(addr) SYMBOL(eearly_reserved_dram, addr)
9
10#define PSP_SHAREDMEM_DRAM_START(addr) SYMBOL(psp_sharedmem_dram, addr)
11#define PSP_SHAREDMEM_DRAM_END(addr) SYMBOL(epsp_sharedmem_dram, addr)
12
13/*
14 *
15 * +--------------------------------+
16 * | |
17 * | |
18 * | |
19 * | |
20 * | |
21 * | |
22 * | |
23 * reserved_dram_end +--------------------------------+
24 * | |
25 * | verstage (if reqd) |
26 * | (VERSTAGE_SIZE) |
27 * +--------------------------------+ VERSTAGE_ADDR
28 * | |
29 * | FSP-M |
30 * | (FSP_M_SIZE) |
31 * +--------------------------------+ FSP_M_ADDR
32 * | |X86_RESET_VECTOR = ROMSTAGE_ADDR + ROMSTAGE_SIZE - 0x10
33 * | romstage |
34 * | (ROMSTAGE_SIZE) |
35 * +--------------------------------+ ROMSTAGE_ADDR
36 * | bootblock |
37 * | (C_ENV_BOOTBLOCK_SIZE) |
38 * +--------------------------------+ BOOTBLOCK_ADDR
39 * | Unused hole |
40 * +--------------------------------+
41 * | FMAP cache (FMAP_SIZE) |
Josie Nordrum5ae96aa2020-09-01 16:31:57 -0600[diff] [blame^]42 * +--------------------------------+ PSP_SHAREDMEM_BASE + 0x40 + VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200
Martin Rothc7acf162020-05-28 00:44:50 -0600[diff] [blame]43 * | Early Timestamp region (512B) |
Josie Nordrum5ae96aa2020-09-01 16:31:57 -0600[diff] [blame^]44 * +--------------------------------+ PSP_SHAREDMEM_BASE + 0x40 + VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE + PRERAM_CBMEM_CONSOLE_SIZE
Martin Rothc7acf162020-05-28 00:44:50 -0600[diff] [blame]45 * | Preram CBMEM console |
46 * | (PRERAM_CBMEM_CONSOLE_SIZE) |
Josie Nordrum5ae96aa2020-09-01 16:31:57 -0600[diff] [blame^]47 * +--------------------------------+ PSP_SHAREDMEM_BASE + 0x40 + VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE
Martin Rothc7acf162020-05-28 00:44:50 -0600[diff] [blame]48 * | PSP shared (vboot workbuf) |
Josie Nordrum5ae96aa2020-09-01 16:31:57 -0600[diff] [blame^]49 * |(VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE) |
Martin Roth0c12abe2020-06-26 08:40:56 -0600[diff] [blame]50 * +--------------------------------+ PSP_SHAREDMEM_BASE + 0x40
51 * | Transfer Info Structure |
Martin Rothc7acf162020-05-28 00:44:50 -0600[diff] [blame]52 * +--------------------------------+ PSP_SHAREDMEM_BASE
53 * | APOB (64KiB) |
54 * +--------------------------------+ PSP_APOB_DRAM_ADDRESS
55 * | Early BSP stack |
56 * | (EARLYRAM_BSP_STACK_SIZE) |
57 * reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE
58 * | DRAM |
59 * +--------------------------------+ 0x100000
60 * | Option ROM |
61 * +--------------------------------+ 0xc0000
62 * | Legacy VGA |
63 * +--------------------------------+ 0xa0000
64 * | DRAM |
65 * +--------------------------------+ 0x0
66 */
67SECTIONS
68{
69 DRAM_START(0x0)
70
71 EARLY_RESERVED_DRAM_START(CONFIG_EARLY_RESERVED_DRAM_BASE)
72
73 EARLYRAM_STACK(., CONFIG_EARLYRAM_BSP_STACK_SIZE)
74 REGION(apob, CONFIG_PSP_APOB_DRAM_ADDRESS, 64K, 1)
75
76#if CONFIG(VBOOT)
77 PSP_SHAREDMEM_DRAM_START(CONFIG_PSP_SHAREDMEM_BASE)
Martin Roth0c12abe2020-06-26 08:40:56 -0600[diff] [blame]78 _transfer_buffer = .;
79 REGION(transfer_info, ., TRANSFER_INFO_SIZE, 4)
Martin Rothc7acf162020-05-28 00:44:50 -0600[diff] [blame]80 VBOOT2_WORK(., VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE)
Martin Rothc7acf162020-05-28 00:44:50 -0600[diff] [blame]81#endif
82
83 PRERAM_CBMEM_CONSOLE(., CONFIG_PRERAM_CBMEM_CONSOLE_SIZE)
Martin Roth0c12abe2020-06-26 08:40:56 -0600[diff] [blame]84 TIMESTAMP(., TIMESTAMP_BUFFER_SIZE)
Martin Rothc7acf162020-05-28 00:44:50 -0600[diff] [blame]85 FMAP_CACHE(., FMAP_SIZE)
Martin Roth0c12abe2020-06-26 08:40:56 -0600[diff] [blame]86#if CONFIG(VBOOT)
87 _etransfer_buffer = .;
Josie Nordrum5ae96aa2020-09-01 16:31:57 -0600[diff] [blame^]88 PSP_SHAREDMEM_DRAM_END(CONFIG_PSP_SHAREDMEM_BASE + CONFIG_PSP_SHAREDMEM_SIZE)
Martin Roth0c12abe2020-06-26 08:40:56 -0600[diff] [blame]89#endif
Martin Rothc7acf162020-05-28 00:44:50 -0600[diff] [blame]90 _ = ASSERT((CONFIG_BOOTBLOCK_ADDR + CONFIG_C_ENV_BOOTBLOCK_SIZE - 0x10) == CONFIG_X86_RESET_VECTOR, "Reset vector should be -0x10 from end of bootblock");
91 _ = ASSERT(CONFIG_BOOTBLOCK_ADDR == ((CONFIG_BOOTBLOCK_ADDR + 0xFFFF) & 0xFFFF0000), "Bootblock must be 16 bit aligned");
92 BOOTBLOCK(CONFIG_BOOTBLOCK_ADDR, CONFIG_C_ENV_BOOTBLOCK_SIZE)
93 ROMSTAGE(CONFIG_ROMSTAGE_ADDR, CONFIG_ROMSTAGE_SIZE)
94 REGION(fspm, CONFIG_FSP_M_ADDR, CONFIG_FSP_M_SIZE, 1)
95#if CONFIG(VBOOT_SEPARATE_VERSTAGE)
96 VERSTAGE(CONFIG_VERSTAGE_ADDR, CONFIG_VERSTAGE_SIZE)
97#endif
98
99 EARLY_RESERVED_DRAM_END(.)
100
101 RAMSTAGE(CONFIG_RAMBASE, 8M)
102}
103
104#if ENV_BOOTBLOCK
105/* Bootblock specific scripts which provide more SECTION directives. */
106#include <cpu/x86/16bit/entry16.ld>
107#include <cpu/x86/16bit/reset16.ld>
108#endif /* ENV_BOOTBLOCK */