Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <console/console.h> |
| 17 | #include <console/usb.h> |
| 18 | #include <bootmode.h> |
| 19 | #include <string.h> |
| 20 | #include <arch/io.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 21 | #include <device/pci_ops.h> |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 22 | #include <cbmem.h> |
| 23 | #include <arch/cbfs.h> |
| 24 | #include <cbfs.h> |
| 25 | #include <ip_checksum.h> |
| 26 | #include <pc80/mc146818rtc.h> |
| 27 | #include <device/pci_def.h> |
Kyösti Mälkki | b697c90 | 2019-01-30 08:19:49 +0200 | [diff] [blame] | 28 | #include <lib.h> |
Arthur Heymans | 7539b8c | 2017-12-24 10:42:57 +0100 | [diff] [blame] | 29 | #include <mrc_cache.h> |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 30 | #include <halt.h> |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 31 | #include <timestamp.h> |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 32 | #include "raminit.h" |
| 33 | #include "pei_data.h" |
| 34 | #include "sandybridge.h" |
Philipp Deppenwiese | fea2429 | 2017-10-17 17:02:29 +0200 | [diff] [blame] | 35 | #include <security/vboot/vboot_common.h> |
Patrick Georgi | 27fbbcf | 2019-04-23 12:33:23 +0200 | [diff] [blame] | 36 | #include <southbridge/intel/bd82x6x/pch.h> |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 37 | |
| 38 | /* Management Engine is in the southbridge */ |
Elyes HAOUAS | 21b71ce6 | 2018-06-16 18:43:52 +0200 | [diff] [blame] | 39 | #include <southbridge/intel/bd82x6x/me.h> |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 40 | |
| 41 | /* |
| 42 | * MRC scrambler seed offsets should be reserved in |
| 43 | * mainboard cmos.layout and not covered by checksum. |
| 44 | */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 45 | #if CONFIG(USE_OPTION_TABLE) |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 46 | #include "option_table.h" |
| 47 | #define CMOS_OFFSET_MRC_SEED (CMOS_VSTART_mrc_scrambler_seed >> 3) |
| 48 | #define CMOS_OFFSET_MRC_SEED_S3 (CMOS_VSTART_mrc_scrambler_seed_s3 >> 3) |
| 49 | #define CMOS_OFFSET_MRC_SEED_CHK (CMOS_VSTART_mrc_scrambler_seed_chk >> 3) |
| 50 | #else |
| 51 | #define CMOS_OFFSET_MRC_SEED 152 |
| 52 | #define CMOS_OFFSET_MRC_SEED_S3 156 |
| 53 | #define CMOS_OFFSET_MRC_SEED_CHK 160 |
| 54 | #endif |
| 55 | |
Arthur Heymans | 7539b8c | 2017-12-24 10:42:57 +0100 | [diff] [blame] | 56 | #define MRC_CACHE_VERSION 0 |
| 57 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 58 | void save_mrc_data(struct pei_data *pei_data) |
| 59 | { |
| 60 | u16 c1, c2, checksum; |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 61 | |
| 62 | /* Save the MRC S3 restore data to cbmem */ |
Arthur Heymans | 7539b8c | 2017-12-24 10:42:57 +0100 | [diff] [blame] | 63 | mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, |
| 64 | pei_data->mrc_output, |
| 65 | pei_data->mrc_output_len); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 66 | |
| 67 | /* Save the MRC seed values to CMOS */ |
| 68 | cmos_write32(CMOS_OFFSET_MRC_SEED, pei_data->scrambler_seed); |
| 69 | printk(BIOS_DEBUG, "Save scrambler seed 0x%08x to CMOS 0x%02x\n", |
| 70 | pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED); |
| 71 | |
| 72 | cmos_write32(CMOS_OFFSET_MRC_SEED_S3, pei_data->scrambler_seed_s3); |
| 73 | printk(BIOS_DEBUG, "Save s3 scrambler seed 0x%08x to CMOS 0x%02x\n", |
| 74 | pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3); |
| 75 | |
| 76 | /* Save a simple checksum of the seed values */ |
| 77 | c1 = compute_ip_checksum((u8*)&pei_data->scrambler_seed, |
| 78 | sizeof(u32)); |
| 79 | c2 = compute_ip_checksum((u8*)&pei_data->scrambler_seed_s3, |
| 80 | sizeof(u32)); |
| 81 | checksum = add_ip_checksums(sizeof(u32), c1, c2); |
| 82 | |
| 83 | cmos_write(checksum & 0xff, CMOS_OFFSET_MRC_SEED_CHK); |
| 84 | cmos_write((checksum >> 8) & 0xff, CMOS_OFFSET_MRC_SEED_CHK+1); |
| 85 | } |
| 86 | |
| 87 | static void prepare_mrc_cache(struct pei_data *pei_data) |
| 88 | { |
Arthur Heymans | 7539b8c | 2017-12-24 10:42:57 +0100 | [diff] [blame] | 89 | struct region_device rdev; |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 90 | u16 c1, c2, checksum, seed_checksum; |
| 91 | |
| 92 | // preset just in case there is an error |
| 93 | pei_data->mrc_input = NULL; |
| 94 | pei_data->mrc_input_len = 0; |
| 95 | |
| 96 | /* Read scrambler seeds from CMOS */ |
| 97 | pei_data->scrambler_seed = cmos_read32(CMOS_OFFSET_MRC_SEED); |
| 98 | printk(BIOS_DEBUG, "Read scrambler seed 0x%08x from CMOS 0x%02x\n", |
| 99 | pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED); |
| 100 | |
| 101 | pei_data->scrambler_seed_s3 = cmos_read32(CMOS_OFFSET_MRC_SEED_S3); |
| 102 | printk(BIOS_DEBUG, "Read S3 scrambler seed 0x%08x from CMOS 0x%02x\n", |
| 103 | pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3); |
| 104 | |
| 105 | /* Compute seed checksum and compare */ |
| 106 | c1 = compute_ip_checksum((u8*)&pei_data->scrambler_seed, |
| 107 | sizeof(u32)); |
| 108 | c2 = compute_ip_checksum((u8*)&pei_data->scrambler_seed_s3, |
| 109 | sizeof(u32)); |
| 110 | checksum = add_ip_checksums(sizeof(u32), c1, c2); |
| 111 | |
| 112 | seed_checksum = cmos_read(CMOS_OFFSET_MRC_SEED_CHK); |
| 113 | seed_checksum |= cmos_read(CMOS_OFFSET_MRC_SEED_CHK+1) << 8; |
| 114 | |
| 115 | if (checksum != seed_checksum) { |
| 116 | printk(BIOS_ERR, "%s: invalid seed checksum\n", __func__); |
| 117 | pei_data->scrambler_seed = 0; |
| 118 | pei_data->scrambler_seed_s3 = 0; |
| 119 | return; |
| 120 | } |
| 121 | |
Arthur Heymans | 7539b8c | 2017-12-24 10:42:57 +0100 | [diff] [blame] | 122 | if (mrc_cache_get_current(MRC_TRAINING_DATA, MRC_CACHE_VERSION, |
| 123 | &rdev)) { |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 124 | /* error message printed in find_current_mrc_cache */ |
| 125 | return; |
| 126 | } |
| 127 | |
Arthur Heymans | 7539b8c | 2017-12-24 10:42:57 +0100 | [diff] [blame] | 128 | pei_data->mrc_input = rdev_mmap_full(&rdev); |
| 129 | pei_data->mrc_input_len = region_device_sz(&rdev); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 130 | |
Arthur Heymans | 7539b8c | 2017-12-24 10:42:57 +0100 | [diff] [blame] | 131 | printk(BIOS_DEBUG, "%s: at %p, size %x\n", |
| 132 | __func__, pei_data->mrc_input, pei_data->mrc_input_len); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 133 | } |
| 134 | |
Elyes HAOUAS | 448d9fb | 2018-05-22 12:51:27 +0200 | [diff] [blame] | 135 | static const char *ecc_decoder[] = { |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 136 | "inactive", |
| 137 | "active on IO", |
| 138 | "disabled on IO", |
| 139 | "active" |
| 140 | }; |
| 141 | |
| 142 | /* |
| 143 | * Dump in the log memory controller configuration as read from the memory |
| 144 | * controller registers. |
| 145 | */ |
| 146 | static void report_memory_config(void) |
| 147 | { |
| 148 | u32 addr_decoder_common, addr_decode_ch[2]; |
| 149 | int i; |
| 150 | |
| 151 | addr_decoder_common = MCHBAR32(0x5000); |
| 152 | addr_decode_ch[0] = MCHBAR32(0x5004); |
| 153 | addr_decode_ch[1] = MCHBAR32(0x5008); |
| 154 | |
| 155 | printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", |
| 156 | (MCHBAR32(0x5e04) * 13333 * 2 + 50)/100); |
| 157 | printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", |
| 158 | addr_decoder_common & 3, |
| 159 | (addr_decoder_common >> 2) & 3, |
| 160 | (addr_decoder_common >> 4) & 3); |
| 161 | |
| 162 | for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { |
| 163 | u32 ch_conf = addr_decode_ch[i]; |
| 164 | printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", |
| 165 | i, ch_conf); |
| 166 | printk(BIOS_DEBUG, " ECC %s\n", |
| 167 | ecc_decoder[(ch_conf >> 24) & 3]); |
| 168 | printk(BIOS_DEBUG, " enhanced interleave mode %s\n", |
| 169 | ((ch_conf >> 22) & 1) ? "on" : "off"); |
| 170 | printk(BIOS_DEBUG, " rank interleave %s\n", |
| 171 | ((ch_conf >> 21) & 1) ? "on" : "off"); |
| 172 | printk(BIOS_DEBUG, " DIMMA %d MB width x%d %s rank%s\n", |
| 173 | ((ch_conf >> 0) & 0xff) * 256, |
| 174 | ((ch_conf >> 19) & 1) ? 16 : 8, |
| 175 | ((ch_conf >> 17) & 1) ? "dual" : "single", |
| 176 | ((ch_conf >> 16) & 1) ? "" : ", selected"); |
| 177 | printk(BIOS_DEBUG, " DIMMB %d MB width x%d %s rank%s\n", |
| 178 | ((ch_conf >> 8) & 0xff) * 256, |
| 179 | ((ch_conf >> 20) & 1) ? 16 : 8, |
| 180 | ((ch_conf >> 18) & 1) ? "dual" : "single", |
| 181 | ((ch_conf >> 16) & 1) ? ", selected" : ""); |
| 182 | } |
| 183 | } |
| 184 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 185 | /** |
| 186 | * Find PEI executable in coreboot filesystem and execute it. |
| 187 | * |
| 188 | * @param pei_data: configuration data for UEFI PEI reference code |
| 189 | */ |
| 190 | void sdram_initialize(struct pei_data *pei_data) |
| 191 | { |
| 192 | struct sys_info sysinfo; |
Stefan Reinauer | 6a00113 | 2017-07-13 02:20:27 +0200 | [diff] [blame] | 193 | int (*entry) (struct pei_data *pei_data) __attribute__((regparm(1))); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 194 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 195 | /* Wait for ME to be ready */ |
| 196 | intel_early_me_init(); |
| 197 | intel_early_me_uma_size(); |
| 198 | |
| 199 | printk(BIOS_DEBUG, "Starting UEFI PEI System Agent\n"); |
| 200 | |
| 201 | memset(&sysinfo, 0, sizeof(sysinfo)); |
| 202 | |
| 203 | sysinfo.boot_path = pei_data->boot_mode; |
| 204 | |
| 205 | /* |
| 206 | * Do not pass MRC data in for recovery mode boot, |
| 207 | * Always pass it in for S3 resume. |
| 208 | */ |
Furquan Shaikh | 0325dc6 | 2016-07-25 13:02:36 -0700 | [diff] [blame] | 209 | if (!vboot_recovery_mode_enabled() || pei_data->boot_mode == 2) |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 210 | prepare_mrc_cache(pei_data); |
| 211 | |
| 212 | /* If MRC data is not found we cannot continue S3 resume. */ |
| 213 | if (pei_data->boot_mode == 2 && !pei_data->mrc_input) { |
| 214 | printk(BIOS_DEBUG, "Giving up in sdram_initialize: No MRC data\n"); |
| 215 | outb(0x6, 0xcf9); |
| 216 | halt(); |
| 217 | } |
| 218 | |
| 219 | /* Pass console handler in pei_data */ |
| 220 | pei_data->tx_byte = do_putchar; |
| 221 | |
| 222 | /* Locate and call UEFI System Agent binary. */ |
| 223 | entry = cbfs_boot_map_with_leak("mrc.bin", CBFS_TYPE_MRC, NULL); |
| 224 | if (entry) { |
| 225 | int rv; |
| 226 | rv = entry (pei_data); |
| 227 | if (rv) { |
| 228 | switch (rv) { |
| 229 | case -1: |
| 230 | printk(BIOS_ERR, "PEI version mismatch.\n"); |
| 231 | break; |
| 232 | case -2: |
| 233 | printk(BIOS_ERR, "Invalid memory frequency.\n"); |
| 234 | break; |
| 235 | default: |
| 236 | printk(BIOS_ERR, "MRC returned %x.\n", rv); |
| 237 | } |
| 238 | die("Nonzero MRC return value.\n"); |
| 239 | } |
| 240 | } else { |
| 241 | die("UEFI PEI System Agent not found.\n"); |
| 242 | } |
| 243 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 244 | /* mrc.bin reconfigures USB, so reinit it to have debug */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 245 | if (CONFIG(USBDEBUG_IN_PRE_RAM)) |
Kyösti Mälkki | 63649d2 | 2018-12-29 09:40:40 +0200 | [diff] [blame] | 246 | usbdebug_hw_init(true); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 247 | |
| 248 | /* For reference print the System Agent version |
| 249 | * after executing the UEFI PEI stage. |
| 250 | */ |
| 251 | u32 version = MCHBAR32(0x5034); |
| 252 | printk(BIOS_DEBUG, "System Agent Version %d.%d.%d Build %d\n", |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 253 | version >> 24, (version >> 16) & 0xff, |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 254 | (version >> 8) & 0xff, version & 0xff); |
| 255 | |
| 256 | /* Send ME init done for SandyBridge here. This is done |
| 257 | * inside the SystemAgent binary on IvyBridge. */ |
| 258 | if (BASE_REV_SNB == |
| 259 | (pci_read_config16(PCI_CPU_DEVICE, PCI_DEVICE_ID) & BASE_REV_MASK)) |
| 260 | intel_early_me_init_done(ME_INIT_STATUS_SUCCESS); |
| 261 | else |
| 262 | intel_early_me_status(); |
| 263 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 264 | report_memory_config(); |
| 265 | } |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 266 | |
Kyösti Mälkki | b697c90 | 2019-01-30 08:19:49 +0200 | [diff] [blame] | 267 | /* These are the location and structure of MRC_VAR data in CAR. */ |
| 268 | #define DCACHE_RAM_MRC_VAR_BASE \ |
| 269 | (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE) |
| 270 | |
| 271 | struct mrc_var_data { |
| 272 | u32 acpi_timer_flag; |
| 273 | u32 pool_used; |
| 274 | u32 pool_base; |
| 275 | u32 tx_byte; |
| 276 | u32 reserved[4]; |
| 277 | } __packed; |
| 278 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 279 | void perform_raminit(int s3resume) |
| 280 | { |
| 281 | int cbmem_was_initted; |
| 282 | struct pei_data pei_data; |
Kyösti Mälkki | b697c90 | 2019-01-30 08:19:49 +0200 | [diff] [blame] | 283 | struct mrc_var_data *mrc_var; |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 284 | |
| 285 | /* Prepare USB controller early in S3 resume */ |
| 286 | if (!mainboard_should_reset_usb(s3resume)) |
| 287 | enable_usb_bar(); |
| 288 | |
| 289 | mainboard_fill_pei_data(&pei_data); |
| 290 | |
| 291 | post_code(0x3a); |
| 292 | pei_data.boot_mode = s3resume ? 2 : 0; |
| 293 | timestamp_add_now(TS_BEFORE_INITRAM); |
| 294 | sdram_initialize(&pei_data); |
Kyösti Mälkki | b697c90 | 2019-01-30 08:19:49 +0200 | [diff] [blame] | 295 | |
| 296 | mrc_var = (void *)DCACHE_RAM_MRC_VAR_BASE; |
| 297 | /* Sanity check mrc_var location by verifying a known field. */ |
| 298 | if (mrc_var->tx_byte == (uintptr_t)pei_data.tx_byte) { |
| 299 | printk(BIOS_DEBUG, "MRC_VAR pool occupied [%08x,%08x]\n", |
| 300 | mrc_var->pool_base, |
| 301 | mrc_var->pool_base + mrc_var->pool_used); |
| 302 | } else { |
| 303 | printk(BIOS_ERR, "Could not parse MRC_VAR data\n"); |
| 304 | hexdump32(BIOS_ERR, mrc_var, sizeof(*mrc_var)/sizeof(u32)); |
| 305 | } |
| 306 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 307 | cbmem_was_initted = !cbmem_recovery(s3resume); |
| 308 | if (!s3resume) |
| 309 | save_mrc_data(&pei_data); |
| 310 | |
| 311 | if (s3resume && !cbmem_was_initted) { |
| 312 | /* Failed S3 resume, reset to come up cleanly */ |
| 313 | outb(0x6, 0xcf9); |
| 314 | halt(); |
| 315 | } |
| 316 | } |