Stefan Reinauer | 425b61e | 2015-03-15 04:29:35 +0100 | [diff] [blame] | 1 | ## |
| 2 | ## This file is part of the coreboot project. |
| 3 | ## |
Stefan Reinauer | 425b61e | 2015-03-15 04:29:35 +0100 | [diff] [blame] | 4 | ## This program is free software; you can redistribute it and/or modify |
| 5 | ## it under the terms of the GNU General Public License as published by |
| 6 | ## the Free Software Foundation; version 2 of the License. |
| 7 | ## |
| 8 | ## This program is distributed in the hope that it will be useful, |
| 9 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | ## GNU General Public License for more details. |
| 12 | ## |
| 13 | |
Stefan Reinauer | a48ca84 | 2015-04-04 01:58:28 +0200 | [diff] [blame] | 14 | config ARCH_X86 |
| 15 | bool |
| 16 | default n |
| 17 | select PCI |
Kyösti Mälkki | ec151f0 | 2018-06-03 22:48:51 +0300 | [diff] [blame] | 18 | select RELOCATABLE_MODULES |
Stefan Reinauer | a48ca84 | 2015-04-04 01:58:28 +0200 | [diff] [blame] | 19 | |
Stefan Reinauer | 6867120 | 2015-03-15 04:34:03 +0100 | [diff] [blame] | 20 | # stage selectors for x86 |
| 21 | |
Furquan Shaikh | 99ac98f | 2014-04-23 10:18:48 -0700 | [diff] [blame] | 22 | config ARCH_BOOTBLOCK_X86_32 |
Gabe Black | 5fbfc91 | 2013-07-07 13:52:37 -0700 | [diff] [blame] | 23 | bool |
Furquan Shaikh | 99ac98f | 2014-04-23 10:18:48 -0700 | [diff] [blame] | 24 | default n |
| 25 | select ARCH_X86 |
Arthur Heymans | c05b1a6 | 2019-11-22 21:01:30 +0100 | [diff] [blame] | 26 | select BOOTBLOCK_CUSTOM if ROMCC_BOOTBLOCK |
Furquan Shaikh | 99ac98f | 2014-04-23 10:18:48 -0700 | [diff] [blame] | 27 | |
Stefan Reinauer | 77b1655 | 2015-01-14 19:51:47 +0100 | [diff] [blame] | 28 | config ARCH_VERSTAGE_X86_32 |
| 29 | bool |
| 30 | default n |
| 31 | |
Furquan Shaikh | 99ac98f | 2014-04-23 10:18:48 -0700 | [diff] [blame] | 32 | config ARCH_ROMSTAGE_X86_32 |
| 33 | bool |
| 34 | default n |
| 35 | |
Patrick Georgi | 29eeece | 2018-10-31 14:24:47 +0100 | [diff] [blame] | 36 | config ARCH_POSTCAR_X86_32 |
| 37 | bool |
| 38 | default ARCH_ROMSTAGE_X86_32 && POSTCAR_STAGE |
| 39 | |
Furquan Shaikh | 99ac98f | 2014-04-23 10:18:48 -0700 | [diff] [blame] | 40 | config ARCH_RAMSTAGE_X86_32 |
| 41 | bool |
| 42 | default n |
Gabe Black | 5fbfc91 | 2013-07-07 13:52:37 -0700 | [diff] [blame] | 43 | |
Stefan Reinauer | 6867120 | 2015-03-15 04:34:03 +0100 | [diff] [blame] | 44 | # stage selectors for x64 |
| 45 | |
| 46 | config ARCH_BOOTBLOCK_X86_64 |
| 47 | bool |
| 48 | default n |
| 49 | select ARCH_X86 |
Arthur Heymans | c05b1a6 | 2019-11-22 21:01:30 +0100 | [diff] [blame] | 50 | select BOOTBLOCK_CUSTOM if ROMCC_BOOTBLOCK |
Stefan Reinauer | 6867120 | 2015-03-15 04:34:03 +0100 | [diff] [blame] | 51 | |
| 52 | config ARCH_VERSTAGE_X86_64 |
| 53 | bool |
| 54 | default n |
| 55 | |
| 56 | config ARCH_ROMSTAGE_X86_64 |
| 57 | bool |
| 58 | default n |
| 59 | |
Patrick Georgi | 29eeece | 2018-10-31 14:24:47 +0100 | [diff] [blame] | 60 | config ARCH_POSTCAR_X86_64 |
| 61 | bool |
| 62 | default ARCH_ROMSTAGE_X86_64 && POSTCAR_STAGE |
| 63 | |
Stefan Reinauer | 6867120 | 2015-03-15 04:34:03 +0100 | [diff] [blame] | 64 | config ARCH_RAMSTAGE_X86_64 |
| 65 | bool |
| 66 | default n |
| 67 | |
Patrick Rudolph | b1ef725 | 2019-09-28 17:44:01 +0200 | [diff] [blame] | 68 | config ARCH_X86_64_PGTBL_LOC |
| 69 | hex "x86_64 page table location in CBFS" |
| 70 | depends on ARCH_BOOTBLOCK_X86_64 |
| 71 | default 0xfffea000 |
| 72 | help |
| 73 | The position where to place pagetables. Needs to be known at |
| 74 | compile time. Must not overlap other files in CBFS. |
| 75 | |
Martin Roth | 0cd9ff8 | 2016-02-01 17:33:37 -0700 | [diff] [blame] | 76 | config USE_MARCH_586 |
| 77 | def_bool n |
| 78 | help |
| 79 | Allow a platform or processor to select to be compiled using |
| 80 | the '-march=i586' option instead of the typical '-march=i686' |
| 81 | |
Uwe Hermann | 168b11b | 2009-10-07 16:15:40 +0000 | [diff] [blame] | 82 | # This is an SMP option. It relates to starting up APs. |
| 83 | # It is usually set in mainboard/*/Kconfig. |
| 84 | # TODO: Improve description. |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 85 | config AP_IN_SIPI_WAIT |
| 86 | bool |
| 87 | default n |
Stefan Reinauer | 2a6f390 | 2012-10-15 13:38:09 -0700 | [diff] [blame] | 88 | depends on ARCH_X86 && SMP |
Ronald G. Minnich | 6ed39d9 | 2009-08-29 02:59:35 +0000 | [diff] [blame] | 89 | |
Marshall Dawson | 67910db | 2019-11-01 17:30:05 -0600 | [diff] [blame] | 90 | config X86_RESET_VECTOR |
| 91 | hex |
| 92 | depends on ARCH_X86 |
| 93 | default 0xfffffff0 |
| 94 | help |
| 95 | Specify the location of the x86 reset vector. In traditional devices |
| 96 | this must match the architectural reset vector to produce a bootable |
| 97 | image. Nontraditional designs may use this to position the reset |
| 98 | vector into its desired location. |
| 99 | |
Martin Roth | 8418fd4 | 2019-04-22 16:26:23 -0600 | [diff] [blame] | 100 | config RESET_VECTOR_IN_RAM |
| 101 | bool |
| 102 | depends on ARCH_X86 |
| 103 | help |
| 104 | Select this option if the x86 soc implements custom code to handle the |
| 105 | reset vector in RAM instead of the traditional 0xfffffff0 location. |
| 106 | |
Kyösti Mälkki | f8c7c23 | 2012-04-06 04:03:50 +0300 | [diff] [blame] | 107 | # Aligns 16bit entry code in bootblock so that hyper-threading CPUs |
| 108 | # can boot AP CPUs to enable their shared caches. |
| 109 | config SIPI_VECTOR_IN_ROM |
| 110 | bool |
| 111 | default n |
| 112 | depends on ARCH_X86 |
| 113 | |
Ronald G. Minnich | 83bd46e | 2018-09-16 09:59:54 -0700 | [diff] [blame] | 114 | # Set the rambase for systems that still need it, only 5 chipsets as of |
| 115 | # Sep 2018. This value was 0x100000, chosen to match the entry point |
| 116 | # of Linux 2.2 in 1999. The new value, 14 MiB, makes a lot more sense |
| 117 | # for as long as we need it; with luck, that won't be much longer. |
| 118 | # In the long term, both RAMBASE and RAMTOP should be removed. |
| 119 | # This value leaves more than 1 MiB which is required for fam10 |
| 120 | # and broadwell_de. |
Patrick Georgi | 0588d19 | 2009-08-12 15:00:51 +0000 | [diff] [blame] | 121 | config RAMBASE |
| 122 | hex |
Ronald G. Minnich | 83bd46e | 2018-09-16 09:59:54 -0700 | [diff] [blame] | 123 | default 0xe00000 |
Patrick Georgi | 0588d19 | 2009-08-12 15:00:51 +0000 | [diff] [blame] | 124 | |
Kyösti Mälkki | bec853e | 2016-06-15 02:25:00 +0300 | [diff] [blame] | 125 | config RAMTOP |
| 126 | hex |
Ronald G. Minnich | 83bd46e | 2018-09-16 09:59:54 -0700 | [diff] [blame] | 127 | default 0x1000000 |
Kyösti Mälkki | bec853e | 2016-06-15 02:25:00 +0300 | [diff] [blame] | 128 | depends on ARCH_X86 |
| 129 | |
Alexandru Gagniuc | 6a62231 | 2015-10-27 10:27:30 -0700 | [diff] [blame] | 130 | # Traditionally BIOS region on SPI flash boot media was memory mapped right below |
| 131 | # 4G and it was the last region in the IFD. This way translation between CPU |
| 132 | # address space to flash address was trivial. However some IFDs on newer SoCs |
| 133 | # have BIOS region sandwiched between descriptor and other regions. Turning off |
| 134 | # this option enables soc code to provide custom mmap_boot.c which can be used to |
| 135 | # implement complex translation. |
| 136 | config X86_TOP4G_BOOTMEDIA_MAP |
| 137 | bool |
| 138 | default y |
| 139 | |
Ronald G. Minnich | b5e777c | 2013-07-22 20:17:18 +0200 | [diff] [blame] | 140 | # This is something you almost certainly don't want to mess with. |
| 141 | # How many SIPIs do we send when starting up APs and cores? |
| 142 | # The answer in 2000 or so was '2'. Nowadays, on many systems, |
| 143 | # it is 1. Set a safe default here, and you can override it |
| 144 | # on reasonable platforms. |
| 145 | config NUM_IPI_STARTS |
| 146 | int |
| 147 | default 2 |
| 148 | |
Kyösti Mälkki | a7dd645 | 2017-04-19 07:37:38 +0300 | [diff] [blame] | 149 | config CBMEM_TOP_BACKUP |
| 150 | def_bool n |
| 151 | help |
| 152 | Platform implements non-volatile storage to cache cbmem_top() |
| 153 | over stage transitions and optionally also over S3 suspend. |
| 154 | |
Naresh G Solanki | 04bb480 | 2016-12-13 21:16:46 +0530 | [diff] [blame] | 155 | config PRERAM_CBMEM_CONSOLE_SIZE |
| 156 | hex |
| 157 | default 0xc00 |
| 158 | help |
| 159 | Increase this value if preram cbmem console is getting truncated |
| 160 | |
Stefan Reinauer | 8aedcbc | 2010-12-16 23:37:17 +0000 | [diff] [blame] | 161 | config PC80_SYSTEM |
| 162 | bool |
Furquan Shaikh | 99ac98f | 2014-04-23 10:18:48 -0700 | [diff] [blame] | 163 | default y if ARCH_X86 |
Stefan Reinauer | 8aedcbc | 2010-12-16 23:37:17 +0000 | [diff] [blame] | 164 | |
Lee Leahy | fdc8c8b | 2016-06-07 08:45:17 -0700 | [diff] [blame] | 165 | config BOOTBLOCK_DEBUG_SPINLOOP |
| 166 | bool |
| 167 | default n |
| 168 | help |
| 169 | Add a spin (JMP .) in bootblock_crt0.S during early bootblock to wait |
| 170 | for a JTAG debugger to break into the execution sequence. |
| 171 | |
Kyösti Mälkki | 48e21ec | 2012-11-14 08:08:50 +0200 | [diff] [blame] | 172 | config BOOTBLOCK_MAINBOARD_INIT |
| 173 | string |
| 174 | |
Patrick Georgi | 1bb6828 | 2009-12-31 12:56:53 +0000 | [diff] [blame] | 175 | config BOOTBLOCK_NORTHBRIDGE_INIT |
| 176 | string |
| 177 | |
Lee Leahy | 5f31f49 | 2015-02-09 21:09:49 -0800 | [diff] [blame] | 178 | config BOOTBLOCK_RESETS |
| 179 | string |
| 180 | |
Patrick Georgi | a865b17 | 2011-01-14 07:40:24 +0000 | [diff] [blame] | 181 | config HAVE_CMOS_DEFAULT |
| 182 | def_bool n |
Martin Roth | f76303e | 2016-11-16 15:45:22 -0700 | [diff] [blame] | 183 | depends on HAVE_OPTION_TABLE |
Patrick Georgi | a865b17 | 2011-01-14 07:40:24 +0000 | [diff] [blame] | 184 | |
| 185 | config CMOS_DEFAULT_FILE |
| 186 | string |
Denis 'GNUtoo' Carikli | 29a4355 | 2013-05-28 13:46:12 +0200 | [diff] [blame] | 187 | default "src/mainboard/$(MAINBOARDDIR)/cmos.default" |
Patrick Georgi | a865b17 | 2011-01-14 07:40:24 +0000 | [diff] [blame] | 188 | depends on HAVE_CMOS_DEFAULT |
| 189 | |
Patrick Georgi | 1bb6828 | 2009-12-31 12:56:53 +0000 | [diff] [blame] | 190 | config BOOTBLOCK_SOUTHBRIDGE_INIT |
| 191 | string |
Stefan Reinauer | 1b34226 | 2011-01-05 02:27:53 +0000 | [diff] [blame] | 192 | |
Patrick Georgi | d4d5e4d | 2012-03-16 19:28:15 +0100 | [diff] [blame] | 193 | config IOAPIC_INTERRUPTS_ON_FSB |
| 194 | bool |
| 195 | default y if !IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS |
| 196 | |
| 197 | config IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS |
| 198 | bool |
| 199 | default n |
| 200 | |
Kyösti Mälkki | b433d26 | 2018-05-24 09:56:11 +0300 | [diff] [blame] | 201 | config HPET_ADDRESS_OVERRIDE |
| 202 | def_bool n |
| 203 | |
Patrick Georgi | 9aeb694 | 2012-10-05 21:54:38 +0200 | [diff] [blame] | 204 | config HPET_ADDRESS |
| 205 | hex |
| 206 | default 0xfed00000 if !HPET_ADDRESS_OVERRIDE |
| 207 | |
Stefan Reinauer | 8483344 | 2012-11-13 15:04:12 -0800 | [diff] [blame] | 208 | config ID_SECTION_OFFSET |
| 209 | hex |
| 210 | default 0x80 |
Patrick Georgi | c32a52c | 2015-06-22 21:10:34 +0200 | [diff] [blame] | 211 | |
Arthur Heymans | c05b1a6 | 2019-11-22 21:01:30 +0100 | [diff] [blame] | 212 | # 64KiB default bootblock size |
Aaron Durbin | 65ac3d8 | 2016-02-11 14:36:19 -0600 | [diff] [blame] | 213 | config C_ENV_BOOTBLOCK_SIZE |
| 214 | hex |
| 215 | default 0x10000 |
Andrey Petrov | ccd300b | 2016-02-28 22:04:51 -0800 | [diff] [blame] | 216 | |
| 217 | # Default address romstage is to be linked at |
| 218 | config ROMSTAGE_ADDR |
| 219 | hex |
| 220 | default 0x2000000 |
| 221 | |
| 222 | # Default address verstage is to be linked at |
| 223 | config VERSTAGE_ADDR |
| 224 | hex |
| 225 | default 0x2000000 |
Aaron Durbin | 7f8afe0 | 2016-03-18 12:21:23 -0500 | [diff] [blame] | 226 | |
| 227 | # Use the post CAR infrastructure for tearing down cache-as-ram |
Elyes HAOUAS | 777ea89 | 2016-07-29 07:40:41 +0200 | [diff] [blame] | 228 | # from a program loaded in RAM and subsequently loading ramstage. |
Aaron Durbin | 7f8afe0 | 2016-03-18 12:21:23 -0500 | [diff] [blame] | 229 | config POSTCAR_STAGE |
Kyösti Mälkki | 0f5e01a | 2019-08-09 07:11:07 +0300 | [diff] [blame] | 230 | def_bool y |
| 231 | depends on ARCH_X86 |
Lee Leahy | d131ea3 | 2016-06-08 13:40:08 -0700 | [diff] [blame] | 232 | |
| 233 | config VERSTAGE_DEBUG_SPINLOOP |
| 234 | bool |
| 235 | default n |
| 236 | help |
| 237 | Add a spin (JMP .) in assembly_entry.S during early verstage to wait |
| 238 | for a JTAG debugger to break into the execution sequence. |
| 239 | |
| 240 | config ROMSTAGE_DEBUG_SPINLOOP |
| 241 | bool |
| 242 | default n |
| 243 | help |
| 244 | Add a spin (JMP .) in assembly_entry.S during early romstage to wait |
| 245 | for a JTAG debugger to break into the execution sequence. |
Martin Roth | 408fda7 | 2016-12-15 16:04:55 -0700 | [diff] [blame] | 246 | |
Arthur Heymans | 2f5abf0 | 2019-06-09 14:01:43 +0200 | [diff] [blame] | 247 | # Selecting a cbfs prefix from the bootblock is only implemented with romcc |
Martin Roth | 408fda7 | 2016-12-15 16:04:55 -0700 | [diff] [blame] | 248 | choice |
| 249 | prompt "Bootblock behaviour" |
| 250 | default BOOTBLOCK_SIMPLE |
Arthur Heymans | c05b1a6 | 2019-11-22 21:01:30 +0100 | [diff] [blame] | 251 | depends on ROMCC_BOOTBLOCK |
Martin Roth | 408fda7 | 2016-12-15 16:04:55 -0700 | [diff] [blame] | 252 | |
| 253 | config BOOTBLOCK_SIMPLE |
| 254 | bool "Always load fallback" |
| 255 | |
| 256 | config BOOTBLOCK_NORMAL |
Arthur Heymans | 6f75154 | 2019-06-08 11:28:52 +0200 | [diff] [blame] | 257 | select CONFIGURABLE_CBFS_PREFIX |
Martin Roth | 408fda7 | 2016-12-15 16:04:55 -0700 | [diff] [blame] | 258 | bool "Switch to normal if CMOS says so" |
| 259 | |
| 260 | endchoice |
| 261 | |
| 262 | config BOOTBLOCK_SOURCE |
| 263 | string |
| 264 | default "bootblock_simple.c" if BOOTBLOCK_SIMPLE |
| 265 | default "bootblock_normal.c" if BOOTBLOCK_NORMAL |
| 266 | |
| 267 | config SKIP_MAX_REBOOT_CNT_CLEAR |
| 268 | bool "Do not clear reboot count after successful boot" |
| 269 | depends on BOOTBLOCK_NORMAL |
| 270 | help |
| 271 | Do not clear the reboot count immediately after successful boot. |
| 272 | Set to allow the payload to control normal/fallback image recovery. |
| 273 | Note that it is the responsibility of the payload to reset the |
Paul Menzel | b949902 | 2019-01-08 16:21:31 +0100 | [diff] [blame] | 274 | normal boot bit to 1 after each successful boot. |
Marc Jones | 7a2d4ea | 2017-08-25 18:54:23 -0600 | [diff] [blame] | 275 | |
Nico Huber | 9df72e0 | 2018-11-24 18:25:50 +0100 | [diff] [blame] | 276 | config ACPI_NO_PCAT_8259 |
| 277 | bool |
| 278 | help |
| 279 | Selected by platforms that don't expose a PC/AT 8259 PIC pair. |
| 280 | |
| 281 | config ACPI_HAVE_PCAT_8259 |
| 282 | def_bool y if !ACPI_NO_PCAT_8259 |
| 283 | |
Marc Jones | 7a2d4ea | 2017-08-25 18:54:23 -0600 | [diff] [blame] | 284 | config ACPI_CPU_STRING |
| 285 | string |
| 286 | default "\\_PR.CP%02d" |
| 287 | depends on HAVE_ACPI_TABLES |
| 288 | help |
| 289 | Sets the ACPI name string in the processor scope as written by |
| 290 | the acpigen function. Default is \_PR.CPxx. Note that you need |
| 291 | the \ escape character in the string. |
Aaron Durbin | f49ddb6 | 2018-01-24 17:35:58 -0700 | [diff] [blame] | 292 | |
| 293 | config COLLECT_TIMESTAMPS_NO_TSC |
| 294 | bool |
| 295 | default n |
| 296 | depends on COLLECT_TIMESTAMPS |
| 297 | help |
| 298 | Use a non-TSC platform-dependent source for timestamps. |
| 299 | |
| 300 | config COLLECT_TIMESTAMPS_TSC |
| 301 | bool |
| 302 | default y if !COLLECT_TIMESTAMPS_NO_TSC |
| 303 | default n |
| 304 | depends on COLLECT_TIMESTAMPS |
| 305 | help |
| 306 | Use the TSC as the timestamp source. |
Aaron Durbin | 0f35af8f | 2018-04-18 01:00:27 -0600 | [diff] [blame] | 307 | |
| 308 | config PAGING_IN_CACHE_AS_RAM |
| 309 | bool |
| 310 | default n |
| 311 | depends on ARCH_X86 |
| 312 | help |
| 313 | Chipsets scan select this option to preallocate area in cache-as-ram |
| 314 | for storing paging data structures. PAE paging is currently the |
| 315 | only thing being supported. |
| 316 | |
| 317 | config NUM_CAR_PAGE_TABLE_PAGES |
| 318 | int |
| 319 | default 5 |
| 320 | depends on PAGING_IN_CACHE_AS_RAM |
| 321 | help |
| 322 | The number of 4KiB pages that should be pre-allocated for page tables. |
Aaron Durbin | 4b032e4 | 2018-04-20 01:39:30 -0600 | [diff] [blame] | 323 | |
| 324 | # Provide the interrupt handlers to every stage. Not all |
| 325 | # stages may take advantage. |
| 326 | config IDT_IN_EVERY_STAGE |
| 327 | bool |
| 328 | default n |
| 329 | depends on ARCH_X86 |
Nico Huber | 33fcaf9 | 2018-10-10 22:44:20 +0200 | [diff] [blame] | 330 | |
| 331 | config HAVE_CF9_RESET |
| 332 | bool |
| 333 | |
| 334 | config HAVE_CF9_RESET_PREPARE |
| 335 | bool |
| 336 | depends on HAVE_CF9_RESET |
Kyösti Mälkki | b72b5d9 | 2019-07-04 21:08:17 +0300 | [diff] [blame] | 337 | |
| 338 | config PIRQ_ROUTE |
| 339 | bool |
| 340 | default n |
| 341 | |
| 342 | config MAX_PIRQ_LINKS |
| 343 | int |
| 344 | default 4 |
| 345 | depends on PIRQ_ROUTE |
| 346 | help |
| 347 | This variable specifies the number of PIRQ interrupt links which are |
| 348 | routable. On most chipsets, this is 4, INTA through INTD. Some |
| 349 | chipsets offer more than four links, commonly up to INTH. They may |
| 350 | also have a separate link for ATA or IOAPIC interrupts. When the PIRQ |
| 351 | table specifies links greater than 4, pirq_route_irqs will not |
| 352 | function properly, unless this variable is correctly set. |