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Angel Pons6e5aabd2020-03-23 23:44:42 +01001/* SPDX-License-Identifier: GPL-2.0-only */
Patrick Rudolphfd5fa2a2016-11-11 18:22:33 +01002
3#ifndef RAMINIT_COMMON_H
4#define RAMINIT_COMMON_H
5
Felix Held380c6b22020-01-26 05:06:38 +01006#include <stdint.h>
7
Angel Pons7c49cb82020-03-16 23:17:32 +01008#define BASEFREQ 133
9#define tDLLK 512
Patrick Rudolphfd5fa2a2016-11-11 18:22:33 +010010
Angel Pons7c49cb82020-03-16 23:17:32 +010011#define IS_SANDY_CPU(x) ((x & 0xffff0) == 0x206a0)
12#define IS_SANDY_CPU_C(x) ((x & 0xf) == 4)
Patrick Rudolphfd5fa2a2016-11-11 18:22:33 +010013#define IS_SANDY_CPU_D0(x) ((x & 0xf) == 5)
14#define IS_SANDY_CPU_D1(x) ((x & 0xf) == 6)
15#define IS_SANDY_CPU_D2(x) ((x & 0xf) == 7)
16
Angel Pons7c49cb82020-03-16 23:17:32 +010017#define IS_IVY_CPU(x) ((x & 0xffff0) == 0x306a0)
Patrick Rudolphfd5fa2a2016-11-11 18:22:33 +010018#define IS_IVY_CPU_C(x) ((x & 0xf) == 4)
19#define IS_IVY_CPU_K(x) ((x & 0xf) == 5)
20#define IS_IVY_CPU_D(x) ((x & 0xf) == 6)
21#define IS_IVY_CPU_E(x) ((x & 0xf) >= 8)
22
Angel Pons7c49cb82020-03-16 23:17:32 +010023#define NUM_CHANNELS 2
24#define NUM_SLOTRANKS 4
25#define NUM_SLOTS 2
Patrick Rudolphdd662872017-10-28 18:20:11 +020026#define NUM_LANES 9
Patrick Rudolphfd5fa2a2016-11-11 18:22:33 +010027
Angel Pons6aa7cca2020-05-02 19:38:34 +020028#define IOSAV_MRS (0xf000)
29#define IOSAV_PRE (0xf002)
30#define IOSAV_ZQCS (0xf003)
31#define IOSAV_ACT (0xf006)
32#define IOSAV_RD (0xf105)
33#define IOSAV_NOP_ALT (0xf107)
34#define IOSAV_WR (0xf201)
35#define IOSAV_NOP (0xf207)
Angel Pons69e17142020-03-23 12:26:29 +010036
Patrick Rudolphfd5fa2a2016-11-11 18:22:33 +010037/* FIXME: Vendor BIOS uses 64 but our algorithms are less
38 performant and even 1 seems to be enough in practice. */
Angel Pons7c49cb82020-03-16 23:17:32 +010039#define NUM_PATTERNS 4
Patrick Rudolphfd5fa2a2016-11-11 18:22:33 +010040
Angel Pons5c1baf52020-03-22 12:23:35 +010041/*
42 * WARNING: Do not forget to increase MRC_CACHE_VERSION when the saved data is changed!
43 */
Patrick Rudolphdd662872017-10-28 18:20:11 +020044#define MRC_CACHE_VERSION 5
Angel Pons5c1baf52020-03-22 12:23:35 +010045
Patrick Rudolphfd5fa2a2016-11-11 18:22:33 +010046typedef struct odtmap_st {
47 u16 rttwr;
48 u16 rttnom;
49} odtmap;
50
Angel Pons5c1baf52020-03-22 12:23:35 +010051/* WARNING: Do not forget to increase MRC_CACHE_VERSION when this struct is changed! */
Patrick Rudolphfd5fa2a2016-11-11 18:22:33 +010052typedef struct dimm_info_st {
53 dimm_attr dimm[NUM_CHANNELS][NUM_SLOTS];
54} dimm_info;
55
Angel Pons5c1baf52020-03-22 12:23:35 +010056/* WARNING: Do not forget to increase MRC_CACHE_VERSION when this struct is changed! */
Patrick Rudolphfd5fa2a2016-11-11 18:22:33 +010057struct ram_rank_timings {
Angel Pons7c49cb82020-03-16 23:17:32 +010058 /* ROUNDT_LAT register: One byte per slotrank */
Angel Pons88521882020-01-05 20:21:20 +010059 u8 roundtrip_latency;
60
Angel Pons7c49cb82020-03-16 23:17:32 +010061 /* IO_LATENCY register: One nibble per slotrank */
Felix Heldef4fe3e2019-12-31 14:15:05 +010062 u8 io_latency;
Patrick Rudolphfd5fa2a2016-11-11 18:22:33 +010063
Angel Pons7c49cb82020-03-16 23:17:32 +010064 /* Phase interpolator coding for command and control */
Angel Pons88521882020-01-05 20:21:20 +010065 int pi_coding;
Patrick Rudolphfd5fa2a2016-11-11 18:22:33 +010066
67 struct ram_lane_timings {
Angel Pons7c49cb82020-03-16 23:17:32 +010068 /* Lane register offset 0x10 */
69 u16 timA; /* bits 0 - 5, bits 16 - 18 */
70 u8 rising; /* bits 8 - 14 */
71 u8 falling; /* bits 20 - 26 */
Patrick Rudolphfd5fa2a2016-11-11 18:22:33 +010072
Angel Pons7c49cb82020-03-16 23:17:32 +010073 /* Lane register offset 0x20 */
74 int timC; /* bits 0 - 5, 19 */
75 u16 timB; /* bits 8 - 13, 15 - 17 */
Patrick Rudolphfd5fa2a2016-11-11 18:22:33 +010076 } lanes[NUM_LANES];
77};
78
Angel Pons5c1baf52020-03-22 12:23:35 +010079/* WARNING: Do not forget to increase MRC_CACHE_VERSION when this struct is changed! */
Patrick Rudolphfd5fa2a2016-11-11 18:22:33 +010080typedef struct ramctr_timing_st {
81 u16 spd_crc[NUM_CHANNELS][NUM_SLOTS];
Angel Pons80037f72020-03-21 13:12:37 +010082
83 /* CPUID value */
84 u32 cpu;
Patrick Rudolphfd5fa2a2016-11-11 18:22:33 +010085
Patrick Rudolph77eaba32016-11-11 18:55:54 +010086 /* DDR base_freq = 100 Mhz / 133 Mhz */
87 u8 base_freq;
88
Angel Pons48409b82020-03-23 22:19:29 +010089 /* Frequency index */
90 u32 FRQ;
91
Patrick Rudolphfd5fa2a2016-11-11 18:22:33 +010092 u16 cas_supported;
Angel Pons7c49cb82020-03-16 23:17:32 +010093 /* Latencies are in units of ns, scaled by x256 */
Patrick Rudolphfd5fa2a2016-11-11 18:22:33 +010094 u32 tCK;
95 u32 tAA;
96 u32 tWR;
97 u32 tRCD;
98 u32 tRRD;
99 u32 tRP;
100 u32 tRAS;
101 u32 tRFC;
102 u32 tWTR;
103 u32 tRTP;
104 u32 tFAW;
Dan Elkoubydabebc32018-04-13 18:47:10 +0300105 u32 tCWL;
106 u32 tCMD;
Patrick Rudolphfd5fa2a2016-11-11 18:22:33 +0100107 /* Latencies in terms of clock cycles
Angel Pons7c49cb82020-03-16 23:17:32 +0100108 They are saved separately as they are needed for DRAM MRS commands */
109 u8 CAS; /* CAS read latency */
Patrick Rudolphfd5fa2a2016-11-11 18:22:33 +0100110 u8 CWL; /* CAS write latency */
111
112 u32 tREFI;
113 u32 tMOD;
114 u32 tXSOffset;
115 u32 tWLO;
116 u32 tCKE;
117 u32 tXPDLL;
118 u32 tXP;
119 u32 tAONPD;
120
Angel Pons7c49cb82020-03-16 23:17:32 +0100121 /* Bits [0..11] of PM_DLL_CONFIG: Master DLL wakeup delay timer */
Angel Pons88521882020-01-05 20:21:20 +0100122 u16 mdll_wake_delay;
Patrick Rudolphfd5fa2a2016-11-11 18:22:33 +0100123
124 u8 rankmap[NUM_CHANNELS];
125 int ref_card_offset[NUM_CHANNELS];
126 u32 mad_dimm[NUM_CHANNELS];
127 int channel_size_mb[NUM_CHANNELS];
128 u32 cmd_stretch[NUM_CHANNELS];
129
Angel Pons88521882020-01-05 20:21:20 +0100130 int pi_code_offset;
131 int pi_coding_threshold;
Patrick Rudolphfd5fa2a2016-11-11 18:22:33 +0100132
Patrick Rudolph05d4bf7e2017-10-28 16:36:09 +0200133 bool ecc_supported;
134 bool ecc_forced;
Patrick Rudolphdd662872017-10-28 18:20:11 +0200135 bool ecc_enabled;
136 int lanes; /* active lanes: 8 or 9 */
Patrick Rudolphfd5fa2a2016-11-11 18:22:33 +0100137 int edge_offset[3];
138 int timC_offset[3];
139
140 int extended_temperature_range;
141 int auto_self_refresh;
142
143 int rank_mirror[NUM_CHANNELS][NUM_SLOTRANKS];
144
145 struct ram_rank_timings timings[NUM_CHANNELS][NUM_SLOTRANKS];
146
147 dimm_info info;
148} ramctr_timing;
149
Felix Held87ddea22020-01-26 04:55:27 +0100150#define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0)
151
Patrick Rudolphdd662872017-10-28 18:20:11 +0200152#define FOR_ALL_LANES for (lane = 0; lane < ctrl->lanes; lane++)
Patrick Rudolphfd5fa2a2016-11-11 18:22:33 +0100153#define FOR_ALL_CHANNELS for (channel = 0; channel < NUM_CHANNELS; channel++)
154#define FOR_ALL_POPULATED_RANKS for (slotrank = 0; slotrank < NUM_SLOTRANKS; slotrank++) if (ctrl->rankmap[channel] & (1 << slotrank))
155#define FOR_ALL_POPULATED_CHANNELS for (channel = 0; channel < NUM_CHANNELS; channel++) if (ctrl->rankmap[channel])
156#define MAX_EDGE_TIMING 71
157#define MAX_TIMC 127
158#define MAX_TIMB 511
159#define MAX_TIMA 127
160#define MAX_CAS 18
161#define MIN_CAS 4
162
Angel Pons7c49cb82020-03-16 23:17:32 +0100163#define MAKE_ERR ((channel << 16) | (slotrank << 8) | 1)
164#define GET_ERR_CHANNEL(x) (x >> 16)
Patrick Rudolphfd5fa2a2016-11-11 18:22:33 +0100165
Patrick Rudolphfd5fa2a2016-11-11 18:22:33 +0100166u8 get_CWL(u32 tCK);
Angel Pons88521882020-01-05 20:21:20 +0100167void dram_mrscommands(ramctr_timing *ctrl);
168void program_timings(ramctr_timing *ctrl, int channel);
Patrick Rudolphfd5fa2a2016-11-11 18:22:33 +0100169void dram_find_common_params(ramctr_timing *ctrl);
Angel Pons88521882020-01-05 20:21:20 +0100170void dram_xover(ramctr_timing *ctrl);
171void dram_timing_regs(ramctr_timing *ctrl);
Patrick Rudolphfd5fa2a2016-11-11 18:22:33 +0100172void dram_dimm_mapping(ramctr_timing *ctrl);
Patrick Rudolphdd662872017-10-28 18:20:11 +0200173void dram_dimm_set_mapping(ramctr_timing *ctrl, int training);
Angel Pons88521882020-01-05 20:21:20 +0100174void dram_zones(ramctr_timing *ctrl, int training);
Angel Pons88521882020-01-05 20:21:20 +0100175void dram_memorymap(ramctr_timing *ctrl, int me_uma_size);
176void dram_jedecreset(ramctr_timing *ctrl);
177int read_training(ramctr_timing *ctrl);
178int write_training(ramctr_timing *ctrl);
Patrick Rudolphfd5fa2a2016-11-11 18:22:33 +0100179int command_training(ramctr_timing *ctrl);
180int discover_edges(ramctr_timing *ctrl);
181int discover_edges_write(ramctr_timing *ctrl);
182int discover_timC_write(ramctr_timing *ctrl);
Angel Pons88521882020-01-05 20:21:20 +0100183void normalize_training(ramctr_timing *ctrl);
184void write_controller_mr(ramctr_timing *ctrl);
Patrick Rudolphfd5fa2a2016-11-11 18:22:33 +0100185int channel_test(ramctr_timing *ctrl);
Angel Pons88521882020-01-05 20:21:20 +0100186void set_scrambling_seed(ramctr_timing *ctrl);
Angel Pons89ae6b82020-03-21 13:23:32 +0100187void set_wmm_behavior(const u32 cpu);
Angel Pons88521882020-01-05 20:21:20 +0100188void prepare_training(ramctr_timing *ctrl);
Angel Pons7c49cb82020-03-16 23:17:32 +0100189void set_read_write_timings(ramctr_timing *ctrl);
Angel Pons88521882020-01-05 20:21:20 +0100190void set_normal_operation(ramctr_timing *ctrl);
191void final_registers(ramctr_timing *ctrl);
192void restore_timings(ramctr_timing *ctrl);
Angel Ponsefbed262020-03-23 23:18:03 +0100193int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, int s3resume, int me_uma_size);
Patrick Rudolphfd5fa2a2016-11-11 18:22:33 +0100194
Patrick Rudolphdd662872017-10-28 18:20:11 +0200195void channel_scrub(ramctr_timing *ctrl);
Patrick Rudolph05d4bf7e2017-10-28 16:36:09 +0200196bool get_host_ecc_cap(void);
197bool get_host_ecc_forced(void);
198
Patrick Rudolph305035c2016-11-11 18:38:50 +0100199#endif