Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2015 Intel Corp. |
| 5 | * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.) |
| 6 | * (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.) |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or |
| 11 | * (at your option) any later version. |
Martin Roth | ebabfad | 2016-04-10 11:09:16 -0600 | [diff] [blame] | 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 17 | */ |
| 18 | |
Aaron Durbin | eebe0e0 | 2016-03-18 11:19:38 -0500 | [diff] [blame] | 19 | #include <arch/cpu.h> |
Ravi Sarawadi | 2da008a | 2016-04-27 15:20:14 -0700 | [diff] [blame] | 20 | #include <arch/early_variables.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 21 | #include <device/pci_ops.h> |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 22 | #include <arch/symbols.h> |
Ravi Sarawadi | 2da008a | 2016-04-27 15:20:14 -0700 | [diff] [blame] | 23 | #include <assert.h> |
Furquan Shaikh | bae6383 | 2016-06-17 15:50:24 -0700 | [diff] [blame] | 24 | #include <bootmode.h> |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 25 | #include <cbmem.h> |
Patrick Rudolph | f677d17 | 2018-10-01 19:17:11 +0200 | [diff] [blame] | 26 | #include <cf9_reset.h> |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 27 | #include <console/console.h> |
Andrey Petrov | f748f83 | 2016-04-23 13:15:51 -0700 | [diff] [blame] | 28 | #include <cpu/x86/mtrr.h> |
Aaron Durbin | 5c9df70 | 2018-04-18 01:05:25 -0600 | [diff] [blame] | 29 | #include <cpu/x86/pae.h> |
John Su | 85376bf | 2018-11-06 10:51:43 +0800 | [diff] [blame] | 30 | #include <delay.h> |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 31 | #include <device/pci_def.h> |
Ravi Sarawadi | 2da008a | 2016-04-27 15:20:14 -0700 | [diff] [blame] | 32 | #include <device/resource.h> |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 33 | #include <fsp/api.h> |
Brandon Breitenstein | 135eae9 | 2016-09-30 13:57:12 -0700 | [diff] [blame] | 34 | #include <fsp/memmap.h> |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 35 | #include <fsp/util.h> |
Barnali Sarkar | 66fe0c4 | 2017-05-23 18:17:14 +0530 | [diff] [blame] | 36 | #include <intelblocks/cpulib.h> |
John Su | 85376bf | 2018-11-06 10:51:43 +0800 | [diff] [blame] | 37 | #include <intelblocks/lpc_lib.h> |
| 38 | #include <intelblocks/msr.h> |
| 39 | #include <intelblocks/pmclib.h> |
Subrata Banik | ce90c78 | 2017-08-30 16:53:20 +0530 | [diff] [blame] | 40 | #include <intelblocks/smm.h> |
Subrata Banik | 208587e | 2017-05-19 18:38:24 +0530 | [diff] [blame] | 41 | #include <intelblocks/systemagent.h> |
Aaron Durbin | decd062 | 2017-12-15 12:26:40 -0700 | [diff] [blame] | 42 | #include <mrc_cache.h> |
Shaunak Saha | a012254 | 2016-10-10 12:34:28 -0700 | [diff] [blame] | 43 | #include <soc/cpu.h> |
Ravi Sarawadi | 2da008a | 2016-04-27 15:20:14 -0700 | [diff] [blame] | 44 | #include <soc/iomap.h> |
Aaron Durbin | 5c9df70 | 2018-04-18 01:05:25 -0600 | [diff] [blame] | 45 | #include <soc/meminit.h> |
Ravi Sarawadi | 2da008a | 2016-04-27 15:20:14 -0700 | [diff] [blame] | 46 | #include <soc/pci_devs.h> |
| 47 | #include <soc/pm.h> |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 48 | #include <soc/romstage.h> |
John Su | 85376bf | 2018-11-06 10:51:43 +0800 | [diff] [blame] | 49 | #include <soc/systemagent.h> |
Furquan Shaikh | d6c5559 | 2016-11-21 12:41:20 -0800 | [diff] [blame] | 50 | #include <spi_flash.h> |
Ravi Sarawadi | 2da008a | 2016-04-27 15:20:14 -0700 | [diff] [blame] | 51 | #include <string.h> |
Shaunak Saha | a012254 | 2016-10-10 12:34:28 -0700 | [diff] [blame] | 52 | #include <timer.h> |
John Su | 85376bf | 2018-11-06 10:51:43 +0800 | [diff] [blame] | 53 | #include <timestamp.h> |
Shaunak Saha | a012254 | 2016-10-10 12:34:28 -0700 | [diff] [blame] | 54 | #include "chip.h" |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 55 | |
Andrey Petrov | 96e9ff1 | 2016-11-04 16:18:30 -0700 | [diff] [blame] | 56 | static const uint8_t hob_variable_guid[16] = { |
| 57 | 0x7d, 0x14, 0x34, 0xa0, 0x0c, 0x69, 0x54, 0x41, |
| 58 | 0x8d, 0xe6, 0xc0, 0x44, 0x64, 0x1d, 0xe9, 0x42, |
| 59 | }; |
| 60 | |
| 61 | static uint32_t fsp_version CAR_GLOBAL; |
| 62 | |
Furquan Shaikh | c681409 | 2016-05-04 16:03:36 -0700 | [diff] [blame] | 63 | /* High Performance Event Timer Configuration */ |
| 64 | #define P2SB_HPTC 0x60 |
| 65 | #define P2SB_HPTC_ADDRESS_ENABLE (1 << 7) |
| 66 | /* |
| 67 | * ADDRESS_SELECT ENCODING_RANGE |
| 68 | * 0 0xFED0 0000 - 0xFED0 03FF |
| 69 | * 1 0xFED0 1000 - 0xFED0 13FF |
| 70 | * 2 0xFED0 2000 - 0xFED0 23FF |
| 71 | * 3 0xFED0 3000 - 0xFED0 33FF |
| 72 | */ |
| 73 | #define P2SB_HPTC_ADDRESS_SELECT_0 (0 << 0) |
| 74 | #define P2SB_HPTC_ADDRESS_SELECT_1 (1 << 0) |
| 75 | #define P2SB_HPTC_ADDRESS_SELECT_2 (2 << 0) |
| 76 | #define P2SB_HPTC_ADDRESS_SELECT_3 (3 << 0) |
| 77 | |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 78 | /* |
| 79 | * Enables several BARs and devices which are needed for memory init |
| 80 | * - MCH_BASE_ADDR is needed in order to talk to the memory controller |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 81 | * - HPET is enabled because FSP wants to store a pointer to global data in the |
| 82 | * HPET comparator register |
| 83 | */ |
| 84 | static void soc_early_romstage_init(void) |
| 85 | { |
Subrata Banik | 208587e | 2017-05-19 18:38:24 +0530 | [diff] [blame] | 86 | static const struct sa_mmio_descriptor soc_fixed_pci_resources[] = { |
| 87 | { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, |
| 88 | }; |
| 89 | |
Jonathan Neuschäfer | 5268b76 | 2018-02-12 12:24:25 +0100 | [diff] [blame] | 90 | /* Set Fixed MMIO address into PCI configuration space */ |
Subrata Banik | 208587e | 2017-05-19 18:38:24 +0530 | [diff] [blame] | 91 | sa_set_pci_bar(soc_fixed_pci_resources, |
| 92 | ARRAY_SIZE(soc_fixed_pci_resources)); |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 93 | |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 94 | /* Enable decoding for HPET. Needed for FSP global pointer storage */ |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 95 | pci_write_config8(PCH_DEV_P2SB, P2SB_HPTC, P2SB_HPTC_ADDRESS_SELECT_0 | |
Furquan Shaikh | c681409 | 2016-05-04 16:03:36 -0700 | [diff] [blame] | 96 | P2SB_HPTC_ADDRESS_ENABLE); |
Mario Scheithauer | 9e9cf27 | 2017-05-15 17:24:56 +0200 | [diff] [blame] | 97 | |
Ravi Sarawadi | efa606b | 2017-08-04 16:26:09 -0700 | [diff] [blame] | 98 | if (IS_ENABLED(CONFIG_DRIVERS_UART_8250IO)) |
| 99 | lpc_io_setup_comm_a_b(); |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 100 | } |
| 101 | |
John Su | 85376bf | 2018-11-06 10:51:43 +0800 | [diff] [blame] | 102 | /* Thermal throttle activation offset */ |
| 103 | static void configure_thermal_target(void) |
| 104 | { |
| 105 | const struct device *dev = dev_find_slot(0, SA_DEVFN_ROOT); |
| 106 | if (!dev) { |
| 107 | printk(BIOS_ERR, "Could not find SOC devicetree config\n"); |
| 108 | return; |
| 109 | } |
| 110 | const config_t *conf = dev->chip_info; |
| 111 | if (!dev->chip_info) { |
| 112 | printk(BIOS_ERR, "Could not find chip info\n"); |
| 113 | return; |
| 114 | } |
| 115 | msr_t msr; |
| 116 | |
| 117 | if (!conf->tcc_offset) |
| 118 | return; |
| 119 | |
| 120 | msr = rdmsr(MSR_TEMPERATURE_TARGET); |
| 121 | /* Bits 27:24 */ |
| 122 | msr.lo &= ~(TEMPERATURE_TCC_MASK << TEMPERATURE_TCC_SHIFT); |
| 123 | msr.lo |= (conf->tcc_offset & TEMPERATURE_TCC_MASK) |
| 124 | << TEMPERATURE_TCC_SHIFT; |
| 125 | wrmsr(MSR_TEMPERATURE_TARGET, msr); |
| 126 | } |
| 127 | |
Shaunak Saha | a012254 | 2016-10-10 12:34:28 -0700 | [diff] [blame] | 128 | /* |
| 129 | * Punit Initialization code. This all isn't documented, but |
| 130 | * this is the recipe. |
| 131 | */ |
| 132 | static bool punit_init(void) |
| 133 | { |
| 134 | uint32_t reg; |
| 135 | uint32_t data; |
| 136 | struct stopwatch sw; |
| 137 | |
John Su | 85376bf | 2018-11-06 10:51:43 +0800 | [diff] [blame] | 138 | /* Thermal throttle activation offset */ |
| 139 | configure_thermal_target(); |
| 140 | |
Shaunak Saha | a012254 | 2016-10-10 12:34:28 -0700 | [diff] [blame] | 141 | /* |
| 142 | * Software Core Disable Mask (P_CR_CORE_DISABLE_MASK_0_0_0_MCHBAR). |
| 143 | * Enable all cores here. |
| 144 | */ |
Subrata Banik | 208587e | 2017-05-19 18:38:24 +0530 | [diff] [blame] | 145 | MCHBAR32(CORE_DISABLE_MASK) = 0x0; |
Subrata Banik | d18b53f | 2017-05-19 13:44:14 +0530 | [diff] [blame] | 146 | |
Shaunak Saha | a012254 | 2016-10-10 12:34:28 -0700 | [diff] [blame] | 147 | /* P-Unit bring up */ |
Subrata Banik | 208587e | 2017-05-19 18:38:24 +0530 | [diff] [blame] | 148 | reg = MCHBAR32(BIOS_RESET_CPL); |
Shaunak Saha | a012254 | 2016-10-10 12:34:28 -0700 | [diff] [blame] | 149 | if (reg == 0xffffffff) { |
| 150 | /* P-unit not found */ |
Lee Leahy | a444753 | 2017-03-09 10:45:02 -0800 | [diff] [blame] | 151 | printk(BIOS_DEBUG, "Punit MMIO not available\n"); |
Shaunak Saha | a012254 | 2016-10-10 12:34:28 -0700 | [diff] [blame] | 152 | return false; |
Lee Leahy | a444753 | 2017-03-09 10:45:02 -0800 | [diff] [blame] | 153 | } |
| 154 | /* Set Punit interrupt pin IPIN offset 3D */ |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 155 | pci_write_config8(SA_DEV_PUNIT, PCI_INTERRUPT_PIN, 0x2); |
Shaunak Saha | a012254 | 2016-10-10 12:34:28 -0700 | [diff] [blame] | 156 | |
Lee Leahy | a444753 | 2017-03-09 10:45:02 -0800 | [diff] [blame] | 157 | /* Set PUINT IRQ to 24 and INTPIN LOCK */ |
Subrata Banik | 208587e | 2017-05-19 18:38:24 +0530 | [diff] [blame] | 158 | MCHBAR32(PUNIT_THERMAL_DEVICE_IRQ) = |
| 159 | PUINT_THERMAL_DEVICE_IRQ_VEC_NUMBER | |
| 160 | PUINT_THERMAL_DEVICE_IRQ_LOCK; |
Shaunak Saha | a012254 | 2016-10-10 12:34:28 -0700 | [diff] [blame] | 161 | |
Hannah Williams | 3ff14a0 | 2017-05-05 16:30:22 -0700 | [diff] [blame] | 162 | if (!IS_ENABLED(CONFIG_SOC_INTEL_GLK)) { |
| 163 | data = MCHBAR32(0x7818); |
| 164 | data &= 0xFFFFE01F; |
| 165 | data |= 0x20 | 0x200; |
| 166 | MCHBAR32(0x7818) = data; |
| 167 | } |
Shaunak Saha | a012254 | 2016-10-10 12:34:28 -0700 | [diff] [blame] | 168 | |
Lee Leahy | a444753 | 2017-03-09 10:45:02 -0800 | [diff] [blame] | 169 | /* Stage0 BIOS Reset Complete (RST_CPL) */ |
Subrata Banik | 208587e | 2017-05-19 18:38:24 +0530 | [diff] [blame] | 170 | enable_bios_reset_cpl(); |
Shaunak Saha | a012254 | 2016-10-10 12:34:28 -0700 | [diff] [blame] | 171 | |
Lee Leahy | a444753 | 2017-03-09 10:45:02 -0800 | [diff] [blame] | 172 | /* |
Subrata Banik | 208587e | 2017-05-19 18:38:24 +0530 | [diff] [blame] | 173 | * Poll for bit 8 to check if PCODE has completed its action |
| 174 | * in reponse to BIOS Reset complete. |
Lee Leahy | a444753 | 2017-03-09 10:45:02 -0800 | [diff] [blame] | 175 | * We wait here till 1 ms for the bit to get set. |
| 176 | */ |
| 177 | stopwatch_init_msecs_expire(&sw, 1); |
Subrata Banik | 208587e | 2017-05-19 18:38:24 +0530 | [diff] [blame] | 178 | while (!(MCHBAR32(BIOS_RESET_CPL) & PCODE_INIT_DONE)) { |
Lee Leahy | a444753 | 2017-03-09 10:45:02 -0800 | [diff] [blame] | 179 | if (stopwatch_expired(&sw)) { |
Subrata Banik | 208587e | 2017-05-19 18:38:24 +0530 | [diff] [blame] | 180 | printk(BIOS_DEBUG, "PCODE Init Done Failure\n"); |
Lee Leahy | a444753 | 2017-03-09 10:45:02 -0800 | [diff] [blame] | 181 | return false; |
Shaunak Saha | a012254 | 2016-10-10 12:34:28 -0700 | [diff] [blame] | 182 | } |
Lee Leahy | a444753 | 2017-03-09 10:45:02 -0800 | [diff] [blame] | 183 | udelay(100); |
Shaunak Saha | a012254 | 2016-10-10 12:34:28 -0700 | [diff] [blame] | 184 | } |
Subrata Banik | 208587e | 2017-05-19 18:38:24 +0530 | [diff] [blame] | 185 | |
Shaunak Saha | a012254 | 2016-10-10 12:34:28 -0700 | [diff] [blame] | 186 | return true; |
| 187 | } |
| 188 | |
Barnali Sarkar | 66fe0c4 | 2017-05-23 18:17:14 +0530 | [diff] [blame] | 189 | void set_max_freq(void) |
| 190 | { |
| 191 | if (cpu_get_burst_mode_state() == BURST_MODE_UNAVAILABLE) { |
| 192 | /* Burst Mode has been factory configured as disabled |
| 193 | * and is not available in this physical processor |
| 194 | * package. |
| 195 | */ |
| 196 | printk(BIOS_DEBUG, "Burst Mode is factory disabled\n"); |
| 197 | return; |
| 198 | } |
| 199 | |
| 200 | /* Enable burst mode */ |
| 201 | cpu_enable_burst_mode(); |
| 202 | |
| 203 | /* Enable speed step. */ |
| 204 | cpu_enable_eist(); |
| 205 | |
| 206 | /* Set P-State ratio */ |
| 207 | cpu_set_p_state_to_turbo_ratio(); |
| 208 | } |
| 209 | |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 210 | asmlinkage void car_stage_entry(void) |
| 211 | { |
Aaron Durbin | eebe0e0 | 2016-03-18 11:19:38 -0500 | [diff] [blame] | 212 | struct postcar_frame pcf; |
Andrey Petrov | f748f83 | 2016-04-23 13:15:51 -0700 | [diff] [blame] | 213 | uintptr_t top_of_ram; |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 214 | bool s3wake; |
Patrick Georgi | c6202e8 | 2017-10-25 18:47:27 -0400 | [diff] [blame] | 215 | struct chipset_power_state *ps = pmc_get_power_state(); |
Brandon Breitenstein | 135eae9 | 2016-09-30 13:57:12 -0700 | [diff] [blame] | 216 | void *smm_base; |
Andrey Petrov | 96e9ff1 | 2016-11-04 16:18:30 -0700 | [diff] [blame] | 217 | size_t smm_size, var_size; |
| 218 | const void *new_var_data; |
Brandon Breitenstein | 135eae9 | 2016-09-30 13:57:12 -0700 | [diff] [blame] | 219 | uintptr_t tseg_base; |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 220 | |
Alexandru Gagniuc | eaa0a17 | 2016-05-16 16:56:28 -0700 | [diff] [blame] | 221 | timestamp_add_now(TS_START_ROMSTAGE); |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 222 | |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 223 | soc_early_romstage_init(); |
Aaron Durbin | 108cd0e | 2016-04-11 15:01:58 -0500 | [diff] [blame] | 224 | |
Alexandru Gagniuc | 766ba77 | 2016-05-16 16:52:54 -0700 | [diff] [blame] | 225 | console_init(); |
| 226 | |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 227 | s3wake = pmc_fill_power_state(ps) == ACPI_S3; |
Lee Leahy | 9671faa | 2016-07-24 18:18:52 -0700 | [diff] [blame] | 228 | fsp_memory_init(s3wake); |
Shaunak Saha | a012254 | 2016-10-10 12:34:28 -0700 | [diff] [blame] | 229 | |
| 230 | if (punit_init()) |
| 231 | set_max_freq(); |
| 232 | else |
| 233 | printk(BIOS_DEBUG, "Punit failed to initialize properly\n"); |
| 234 | |
Andrey Petrov | 96e9ff1 | 2016-11-04 16:18:30 -0700 | [diff] [blame] | 235 | /* Stash variable MRC data and let cache system update it later */ |
| 236 | new_var_data = fsp_find_extension_hob_by_guid(hob_variable_guid, |
| 237 | &var_size); |
| 238 | if (new_var_data) |
Aaron Durbin | 31be2c9 | 2016-12-03 22:08:20 -0600 | [diff] [blame] | 239 | mrc_cache_stash_data(MRC_VARIABLE_DATA, |
| 240 | car_get_var(fsp_version), new_var_data, |
| 241 | var_size); |
Andrey Petrov | 96e9ff1 | 2016-11-04 16:18:30 -0700 | [diff] [blame] | 242 | else |
| 243 | printk(BIOS_ERR, "Failed to determine variable data\n"); |
| 244 | |
Aaron Durbin | eebe0e0 | 2016-03-18 11:19:38 -0500 | [diff] [blame] | 245 | if (postcar_frame_init(&pcf, 1*KiB)) |
| 246 | die("Unable to initialize postcar frame.\n"); |
| 247 | |
Ravi Sarawadi | 15f6f3a | 2016-08-18 13:31:29 -0700 | [diff] [blame] | 248 | mainboard_save_dimm_info(); |
| 249 | |
Andrey Petrov | f748f83 | 2016-04-23 13:15:51 -0700 | [diff] [blame] | 250 | /* |
| 251 | * We need to make sure ramstage will be run cached. At this point exact |
| 252 | * location of ramstage in cbmem is not known. Instruct postcar to cache |
| 253 | * 16 megs under cbmem top which is a safe bet to cover ramstage. |
| 254 | */ |
| 255 | top_of_ram = (uintptr_t) cbmem_top(); |
| 256 | /* cbmem_top() needs to be at least 16 MiB aligned */ |
| 257 | assert(ALIGN_DOWN(top_of_ram, 16*MiB) == top_of_ram); |
Lee Leahy | 07441b5 | 2017-03-09 10:59:25 -0800 | [diff] [blame] | 258 | postcar_frame_add_mtrr(&pcf, top_of_ram - 16*MiB, 16*MiB, |
| 259 | MTRR_TYPE_WRBACK); |
Andrey Petrov | f748f83 | 2016-04-23 13:15:51 -0700 | [diff] [blame] | 260 | |
Aaron Durbin | dfe614f | 2016-09-16 11:15:49 -0500 | [diff] [blame] | 261 | /* Cache the memory-mapped boot media. */ |
Nico Huber | 6ea6775 | 2018-05-27 14:37:52 +0200 | [diff] [blame] | 262 | postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); |
Aaron Durbin | dfe614f | 2016-09-16 11:15:49 -0500 | [diff] [blame] | 263 | |
Brandon Breitenstein | 135eae9 | 2016-09-30 13:57:12 -0700 | [diff] [blame] | 264 | /* |
| 265 | * Cache the TSEG region at the top of ram. This region is |
| 266 | * not restricted to SMM mode until SMM has been relocated. |
| 267 | * By setting the region to cacheable it provides faster access |
| 268 | * when relocating the SMM handler as well as using the TSEG |
| 269 | * region for other purposes. |
| 270 | */ |
Subrata Banik | ce90c78 | 2017-08-30 16:53:20 +0530 | [diff] [blame] | 271 | smm_region_info(&smm_base, &smm_size); |
Brandon Breitenstein | 135eae9 | 2016-09-30 13:57:12 -0700 | [diff] [blame] | 272 | tseg_base = (uintptr_t)smm_base; |
| 273 | postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, MTRR_TYPE_WRBACK); |
| 274 | |
Aaron Durbin | eebe0e0 | 2016-03-18 11:19:38 -0500 | [diff] [blame] | 275 | run_postcar_phase(&pcf); |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 276 | } |
| 277 | |
Brandon Breitenstein | c31ba0e | 2016-07-27 17:34:45 -0700 | [diff] [blame] | 278 | static void fill_console_params(FSPM_UPD *mupd) |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 279 | { |
| 280 | if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) { |
Nico Huber | a96e66a | 2018-11-11 02:51:14 +0100 | [diff] [blame] | 281 | if (IS_ENABLED(CONFIG_INTEL_LPSS_UART_FOR_CONSOLE)) { |
Mario Scheithauer | 9e9cf27 | 2017-05-15 17:24:56 +0200 | [diff] [blame] | 282 | mupd->FspmConfig.SerialDebugPortDevice = |
| 283 | CONFIG_UART_FOR_CONSOLE; |
| 284 | /* use MMIO port type */ |
| 285 | mupd->FspmConfig.SerialDebugPortType = 2; |
| 286 | /* use 4 byte register stride */ |
| 287 | mupd->FspmConfig.SerialDebugPortStrideSize = 2; |
| 288 | /* used only for port type set to external */ |
| 289 | mupd->FspmConfig.SerialDebugPortAddress = 0; |
| 290 | } else if (IS_ENABLED(CONFIG_DRIVERS_UART_8250IO)) { |
| 291 | /* use external UART for debug */ |
| 292 | mupd->FspmConfig.SerialDebugPortDevice = 3; |
| 293 | /* use I/O port type */ |
| 294 | mupd->FspmConfig.SerialDebugPortType = 1; |
| 295 | /* use 1 byte register stride */ |
| 296 | mupd->FspmConfig.SerialDebugPortStrideSize = 0; |
| 297 | /* used only for port type set to external */ |
| 298 | mupd->FspmConfig.SerialDebugPortAddress = |
| 299 | CONFIG_TTYS0_BASE; |
| 300 | } |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 301 | } else { |
| 302 | mupd->FspmConfig.SerialDebugPortType = 0; |
| 303 | } |
| 304 | } |
| 305 | |
Aaron Durbin | 9c86aafe | 2017-04-26 15:02:51 -0500 | [diff] [blame] | 306 | static void check_full_retrain(const FSPM_UPD *mupd) |
| 307 | { |
| 308 | struct chipset_power_state *ps; |
| 309 | |
| 310 | if (mupd->FspmArchUpd.BootMode != FSP_BOOT_WITH_FULL_CONFIGURATION) |
| 311 | return; |
| 312 | |
Patrick Georgi | c6202e8 | 2017-10-25 18:47:27 -0400 | [diff] [blame] | 313 | ps = pmc_get_power_state(); |
Aaron Durbin | 9c86aafe | 2017-04-26 15:02:51 -0500 | [diff] [blame] | 314 | |
| 315 | if (ps->gen_pmcon1 & WARM_RESET_STS) { |
| 316 | printk(BIOS_INFO, "Full retrain unsupported on warm reboot.\n"); |
Patrick Rudolph | f677d17 | 2018-10-01 19:17:11 +0200 | [diff] [blame] | 317 | full_reset(); |
Aaron Durbin | 9c86aafe | 2017-04-26 15:02:51 -0500 | [diff] [blame] | 318 | } |
| 319 | } |
| 320 | |
Pratik Prajapati | 4bc6edf | 2017-08-29 14:11:16 -0700 | [diff] [blame] | 321 | static void soc_memory_init_params(FSPM_UPD *mupd) |
| 322 | { |
| 323 | #if IS_ENABLED(CONFIG_SOC_INTEL_GLK) |
| 324 | /* Only for GLK */ |
| 325 | const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC); |
| 326 | assert(dev != NULL); |
| 327 | const config_t *config = dev->chip_info; |
| 328 | FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; |
| 329 | |
| 330 | if (!config) |
| 331 | die("Can not find SoC devicetree\n"); |
| 332 | |
| 333 | m_cfg->PrmrrSize = config->PrmrrSize; |
Shamile Khan | 3d9462a | 2018-03-21 14:43:42 -0700 | [diff] [blame] | 334 | |
Srinidhi N Kaushik | 5af546c | 2018-05-14 23:33:55 -0700 | [diff] [blame] | 335 | /* |
| 336 | * CpuMemoryTest in FSP tests 0 to 1M of the RAM after MRC init. |
| 337 | * With PAGING_IN_CACHE_AS_RAM enabled for GLK, there was no page |
| 338 | * table entry for this range which caused a page fault. Since this |
| 339 | * test is anyway not exhaustive, skipping the memory test in FSP. |
Shamile Khan | 3d9462a | 2018-03-21 14:43:42 -0700 | [diff] [blame] | 340 | */ |
Srinidhi N Kaushik | 5af546c | 2018-05-14 23:33:55 -0700 | [diff] [blame] | 341 | m_cfg->SkipMemoryTestUpd = 1; |
| 342 | |
| 343 | /* |
| 344 | * PCIe power sequence can be done from within FSP when provided |
| 345 | * with the GPIOs used for PERST to FSP. Since this is done in |
| 346 | * coreboot, skipping the PCIe power sequence done by FSP. |
| 347 | */ |
| 348 | m_cfg->SkipPciePowerSequence = 1; |
Pratik Prajapati | 4bc6edf | 2017-08-29 14:11:16 -0700 | [diff] [blame] | 349 | #endif |
| 350 | } |
| 351 | |
Shaunak Saha | 6681cf0 | 2018-03-22 06:29:57 -0700 | [diff] [blame] | 352 | static void parse_devicetree_setting(FSPM_UPD *m_upd) |
| 353 | { |
| 354 | #if IS_ENABLED(CONFIG_SOC_INTEL_GLK) |
| 355 | DEVTREE_CONST struct device *dev = dev_find_slot(0, PCH_DEVFN_NPK); |
| 356 | if (!dev) |
| 357 | return; |
| 358 | |
| 359 | m_upd->FspmConfig.TraceHubEn = dev->enabled; |
| 360 | #endif |
| 361 | } |
| 362 | |
Andrey Petrov | f796c6e | 2016-11-18 14:57:51 -0800 | [diff] [blame] | 363 | void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 364 | { |
Aaron Durbin | 31be2c9 | 2016-12-03 22:08:20 -0600 | [diff] [blame] | 365 | struct region_device rdev; |
Andrey Petrov | 96e9ff1 | 2016-11-04 16:18:30 -0700 | [diff] [blame] | 366 | |
Aaron Durbin | 9c86aafe | 2017-04-26 15:02:51 -0500 | [diff] [blame] | 367 | check_full_retrain(mupd); |
| 368 | |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 369 | fill_console_params(mupd); |
Pratik Prajapati | 4bc6edf | 2017-08-29 14:11:16 -0700 | [diff] [blame] | 370 | |
| 371 | if (IS_ENABLED(CONFIG_SOC_INTEL_GLK)) |
| 372 | soc_memory_init_params(mupd); |
| 373 | |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 374 | mainboard_memory_init_params(mupd); |
| 375 | |
Shaunak Saha | 6681cf0 | 2018-03-22 06:29:57 -0700 | [diff] [blame] | 376 | parse_devicetree_setting(mupd); |
| 377 | |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 378 | /* Do NOT let FSP do any GPIO pad configuration */ |
Bora Guvendik | de4b09f | 2016-05-09 17:18:26 -0700 | [diff] [blame] | 379 | mupd->FspmConfig.PreMemGpioTablePtr = (uintptr_t) NULL; |
Andrey Petrov | 24a594f | 2016-06-28 17:37:09 -0700 | [diff] [blame] | 380 | |
| 381 | /* |
| 382 | * Tell CSE we do not need to use Ring Buffer Protocol (RBP) to fetch |
| 383 | * firmware for us if we are using memory-mapped SPI. This lets CSE |
| 384 | * state machine transition to next boot state, so that it can function |
| 385 | * as designed. |
| 386 | */ |
Aaron Durbin | 16c173f | 2016-08-11 14:04:10 -0500 | [diff] [blame] | 387 | mupd->FspmConfig.SkipCseRbp = |
| 388 | IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED); |
Andrey Petrov | 0910f4e | 2016-10-03 16:05:20 -0700 | [diff] [blame] | 389 | |
| 390 | /* |
| 391 | * Converged Security Engine (CSE) has secure storage functionality. |
| 392 | * HECI2 device can be used to access that functionality. However, part |
| 393 | * of S3 resume flow involves resetting HECI2 which takes 136ms. Since |
| 394 | * coreboot does not use secure storage functionality, instruct FSP to |
| 395 | * skip HECI2 reset. |
| 396 | */ |
| 397 | mupd->FspmConfig.EnableS3Heci2 = 0; |
Andrey Petrov | 96e9ff1 | 2016-11-04 16:18:30 -0700 | [diff] [blame] | 398 | |
| 399 | /* |
| 400 | * Apollolake splits MRC cache into two parts: constant and variable. |
| 401 | * The constant part is not expected to change often and variable is. |
| 402 | * Currently variable part consists of parameters that change on cold |
| 403 | * boots such as scrambler seed and some memory controller registers. |
| 404 | * Scrambler seed is vital for S3 resume case because attempt to use |
| 405 | * wrong/missing key renders DRAM contents useless. |
| 406 | */ |
| 407 | |
Aaron Durbin | 31be2c9 | 2016-12-03 22:08:20 -0600 | [diff] [blame] | 408 | if (mrc_cache_get_current(MRC_VARIABLE_DATA, version, &rdev) == 0) { |
| 409 | /* Assume leaking is ok. */ |
| 410 | assert(IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)); |
| 411 | mupd->FspmConfig.VariableNvsBufferPtr = rdev_mmap_full(&rdev); |
Andrey Petrov | 96e9ff1 | 2016-11-04 16:18:30 -0700 | [diff] [blame] | 412 | } |
| 413 | |
| 414 | car_set_var(fsp_version, version); |
Aaron Durbin | 5c9df70 | 2018-04-18 01:05:25 -0600 | [diff] [blame] | 415 | |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 416 | } |
| 417 | |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 418 | __weak |
Brandon Breitenstein | c31ba0e | 2016-07-27 17:34:45 -0700 | [diff] [blame] | 419 | void mainboard_memory_init_params(FSPM_UPD *mupd) |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 420 | { |
| 421 | printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); |
| 422 | } |
Furquan Shaikh | bae6383 | 2016-06-17 15:50:24 -0700 | [diff] [blame] | 423 | |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 424 | __weak |
Ravi Sarawadi | 15f6f3a | 2016-08-18 13:31:29 -0700 | [diff] [blame] | 425 | void mainboard_save_dimm_info(void) |
| 426 | { |
| 427 | printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); |
| 428 | } |