Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #define __SIMPLE_DEVICE__ |
| 17 | |
Kyösti Mälkki | bfca670 | 2016-07-22 22:48:35 +0300 | [diff] [blame] | 18 | #include <arch/cpu.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 19 | #include <device/pci_ops.h> |
Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 20 | #include <cbmem.h> |
Kyösti Mälkki | b84c833 | 2016-12-01 10:48:43 +0200 | [diff] [blame] | 21 | #include <console/console.h> |
Kyösti Mälkki | a4ffe9d | 2016-06-27 13:24:11 +0300 | [diff] [blame] | 22 | #include <cpu/intel/romstage.h> |
Kyösti Mälkki | f6c2068 | 2019-08-02 06:14:50 +0300 | [diff] [blame] | 23 | #include <cpu/intel/smm/gen1/smi.h> |
Kyösti Mälkki | bfca670 | 2016-07-22 22:48:35 +0300 | [diff] [blame] | 24 | #include <cpu/x86/mtrr.h> |
| 25 | #include <program_loading.h> |
Kyösti Mälkki | f6c2068 | 2019-08-02 06:14:50 +0300 | [diff] [blame] | 26 | #include <stage_cache.h> |
Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 27 | #include "sandybridge.h" |
| 28 | |
Kyösti Mälkki | f1e3c76 | 2014-12-22 12:28:07 +0200 | [diff] [blame] | 29 | static uintptr_t smm_region_start(void) |
Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 30 | { |
| 31 | /* Base of TSEG is top of usable DRAM */ |
Kyösti Mälkki | f1e3c76 | 2014-12-22 12:28:07 +0200 | [diff] [blame] | 32 | uintptr_t tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); |
| 33 | return tom; |
| 34 | } |
| 35 | |
| 36 | void *cbmem_top(void) |
| 37 | { |
| 38 | return (void *) smm_region_start(); |
Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 39 | } |
Kyösti Mälkki | a4ffe9d | 2016-06-27 13:24:11 +0300 | [diff] [blame] | 40 | |
Kyösti Mälkki | f6c2068 | 2019-08-02 06:14:50 +0300 | [diff] [blame] | 41 | u32 northbridge_get_tseg_base(void) |
| 42 | { |
| 43 | return ALIGN_DOWN(smm_region_start(), 1*MiB); |
| 44 | } |
| 45 | |
| 46 | u32 northbridge_get_tseg_size(void) |
| 47 | { |
| 48 | return CONFIG_SMM_TSEG_SIZE; |
| 49 | } |
| 50 | |
| 51 | void stage_cache_external_region(void **base, size_t *size) |
| 52 | { |
| 53 | /* The stage cache lives at the end of TSEG region. |
| 54 | * The top of RAM is defined to be the TSEG base address. */ |
| 55 | *size = CONFIG_SMM_RESERVED_SIZE; |
| 56 | *base = (void *)((uintptr_t)northbridge_get_tseg_base() + northbridge_get_tseg_size() |
| 57 | - CONFIG_IED_REGION_SIZE - CONFIG_SMM_RESERVED_SIZE); |
| 58 | } |
| 59 | |
Arthur Heymans | 6fcd7b8 | 2018-06-03 12:16:24 +0200 | [diff] [blame] | 60 | /* platform_enter_postcar() determines the stack to use after |
| 61 | * cache-as-ram is torn down as well as the MTRR settings to use, |
| 62 | * and continues execution in postcar stage. */ |
| 63 | void platform_enter_postcar(void) |
Kyösti Mälkki | a4ffe9d | 2016-06-27 13:24:11 +0300 | [diff] [blame] | 64 | { |
Kyösti Mälkki | b84c833 | 2016-12-01 10:48:43 +0200 | [diff] [blame] | 65 | struct postcar_frame pcf; |
| 66 | uintptr_t top_of_ram; |
Kyösti Mälkki | bfca670 | 2016-07-22 22:48:35 +0300 | [diff] [blame] | 67 | |
Kyösti Mälkki | 6e2d0c1 | 2019-06-28 10:08:51 +0300 | [diff] [blame] | 68 | if (postcar_frame_init(&pcf, 0)) |
Kyösti Mälkki | b84c833 | 2016-12-01 10:48:43 +0200 | [diff] [blame] | 69 | die("Unable to initialize postcar frame.\n"); |
Kyösti Mälkki | bfca670 | 2016-07-22 22:48:35 +0300 | [diff] [blame] | 70 | |
| 71 | /* Cache the ROM as WP just below 4GiB. */ |
Nico Huber | 089b908 | 2018-05-27 14:37:32 +0200 | [diff] [blame] | 72 | postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); |
Kyösti Mälkki | bfca670 | 2016-07-22 22:48:35 +0300 | [diff] [blame] | 73 | |
| 74 | /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ |
Kyösti Mälkki | b84c833 | 2016-12-01 10:48:43 +0200 | [diff] [blame] | 75 | postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); |
Kyösti Mälkki | bfca670 | 2016-07-22 22:48:35 +0300 | [diff] [blame] | 76 | |
Kyösti Mälkki | b84c833 | 2016-12-01 10:48:43 +0200 | [diff] [blame] | 77 | top_of_ram = (uintptr_t)cbmem_top(); |
Kyösti Mälkki | bfca670 | 2016-07-22 22:48:35 +0300 | [diff] [blame] | 78 | /* Cache 8MiB below the top of ram. On sandybridge systems the top of |
| 79 | * ram under 4GiB is the start of the TSEG region. It is required to |
| 80 | * be 8MiB aligned. Set this area as cacheable so it can be used later |
| 81 | * for ramstage before setting up the entire RAM as cacheable. */ |
Kyösti Mälkki | b84c833 | 2016-12-01 10:48:43 +0200 | [diff] [blame] | 82 | postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); |
Kyösti Mälkki | bfca670 | 2016-07-22 22:48:35 +0300 | [diff] [blame] | 83 | |
| 84 | /* Cache 8MiB at the top of ram. Top of ram on sandybridge systems |
| 85 | * is where the TSEG region resides. However, it is not restricted |
| 86 | * to SMM mode until SMM has been relocated. By setting the region |
| 87 | * to cacheable it provides faster access when relocating the SMM |
| 88 | * handler as well as using the TSEG region for other purposes. */ |
Kyösti Mälkki | b84c833 | 2016-12-01 10:48:43 +0200 | [diff] [blame] | 89 | postcar_frame_add_mtrr(&pcf, top_of_ram, 8*MiB, MTRR_TYPE_WRBACK); |
Kyösti Mälkki | bfca670 | 2016-07-22 22:48:35 +0300 | [diff] [blame] | 90 | |
Arthur Heymans | 6fcd7b8 | 2018-06-03 12:16:24 +0200 | [diff] [blame] | 91 | run_postcar_phase(&pcf); |
| 92 | |
| 93 | /* We do not return here. */ |
Kyösti Mälkki | a4ffe9d | 2016-06-27 13:24:11 +0300 | [diff] [blame] | 94 | } |