Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Google Inc. |
Kyösti Mälkki | bfca670 | 2016-07-22 22:48:35 +0300 | [diff] [blame] | 5 | * Copyright (C) 2012 ChromeOS Authors |
Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #define __SIMPLE_DEVICE__ |
| 18 | |
Kyösti Mälkki | bfca670 | 2016-07-22 22:48:35 +0300 | [diff] [blame] | 19 | #include <arch/cpu.h> |
Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 20 | #include <arch/io.h> |
| 21 | #include <cbmem.h> |
Kyösti Mälkki | b84c833 | 2016-12-01 10:48:43 +0200 | [diff] [blame] | 22 | #include <console/console.h> |
Kyösti Mälkki | a4ffe9d | 2016-06-27 13:24:11 +0300 | [diff] [blame] | 23 | #include <cpu/intel/romstage.h> |
Kyösti Mälkki | bfca670 | 2016-07-22 22:48:35 +0300 | [diff] [blame] | 24 | #include <cpu/x86/mtrr.h> |
| 25 | #include <program_loading.h> |
Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 26 | #include "sandybridge.h" |
| 27 | |
Kyösti Mälkki | bfca670 | 2016-07-22 22:48:35 +0300 | [diff] [blame] | 28 | #if (CONFIG_SMM_TSEG_SIZE < 0x800000) |
| 29 | # error "CONFIG_SMM_TSEG_SIZE must at least be 8MiB" |
| 30 | #endif |
| 31 | #if ((CONFIG_SMM_TSEG_SIZE & (CONFIG_SMM_TSEG_SIZE - 1)) != 0) |
| 32 | # error "CONFIG_SMM_TSEG_SIZE is not a power of 2" |
| 33 | #endif |
| 34 | |
Kyösti Mälkki | f1e3c76 | 2014-12-22 12:28:07 +0200 | [diff] [blame] | 35 | static uintptr_t smm_region_start(void) |
Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 36 | { |
| 37 | /* Base of TSEG is top of usable DRAM */ |
Kyösti Mälkki | f1e3c76 | 2014-12-22 12:28:07 +0200 | [diff] [blame] | 38 | uintptr_t tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); |
| 39 | return tom; |
| 40 | } |
| 41 | |
| 42 | void *cbmem_top(void) |
| 43 | { |
| 44 | return (void *) smm_region_start(); |
Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 45 | } |
Kyösti Mälkki | a4ffe9d | 2016-06-27 13:24:11 +0300 | [diff] [blame] | 46 | |
Kyösti Mälkki | b84c833 | 2016-12-01 10:48:43 +0200 | [diff] [blame] | 47 | #define ROMSTAGE_RAM_STACK_SIZE 0x5000 |
Kyösti Mälkki | bfca670 | 2016-07-22 22:48:35 +0300 | [diff] [blame] | 48 | |
Arthur Heymans | 6fcd7b8 | 2018-06-03 12:16:24 +0200 | [diff] [blame^] | 49 | /* platform_enter_postcar() determines the stack to use after |
| 50 | * cache-as-ram is torn down as well as the MTRR settings to use, |
| 51 | * and continues execution in postcar stage. */ |
| 52 | void platform_enter_postcar(void) |
Kyösti Mälkki | a4ffe9d | 2016-06-27 13:24:11 +0300 | [diff] [blame] | 53 | { |
Kyösti Mälkki | b84c833 | 2016-12-01 10:48:43 +0200 | [diff] [blame] | 54 | struct postcar_frame pcf; |
| 55 | uintptr_t top_of_ram; |
Kyösti Mälkki | bfca670 | 2016-07-22 22:48:35 +0300 | [diff] [blame] | 56 | |
Kyösti Mälkki | b84c833 | 2016-12-01 10:48:43 +0200 | [diff] [blame] | 57 | if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) |
| 58 | die("Unable to initialize postcar frame.\n"); |
Kyösti Mälkki | bfca670 | 2016-07-22 22:48:35 +0300 | [diff] [blame] | 59 | |
| 60 | /* Cache the ROM as WP just below 4GiB. */ |
Nico Huber | 089b908 | 2018-05-27 14:37:32 +0200 | [diff] [blame] | 61 | postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); |
Kyösti Mälkki | bfca670 | 2016-07-22 22:48:35 +0300 | [diff] [blame] | 62 | |
| 63 | /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ |
Kyösti Mälkki | b84c833 | 2016-12-01 10:48:43 +0200 | [diff] [blame] | 64 | postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); |
Kyösti Mälkki | bfca670 | 2016-07-22 22:48:35 +0300 | [diff] [blame] | 65 | |
Kyösti Mälkki | b84c833 | 2016-12-01 10:48:43 +0200 | [diff] [blame] | 66 | top_of_ram = (uintptr_t)cbmem_top(); |
Kyösti Mälkki | bfca670 | 2016-07-22 22:48:35 +0300 | [diff] [blame] | 67 | /* Cache 8MiB below the top of ram. On sandybridge systems the top of |
| 68 | * ram under 4GiB is the start of the TSEG region. It is required to |
| 69 | * be 8MiB aligned. Set this area as cacheable so it can be used later |
| 70 | * for ramstage before setting up the entire RAM as cacheable. */ |
Kyösti Mälkki | b84c833 | 2016-12-01 10:48:43 +0200 | [diff] [blame] | 71 | postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); |
Kyösti Mälkki | bfca670 | 2016-07-22 22:48:35 +0300 | [diff] [blame] | 72 | |
| 73 | /* Cache 8MiB at the top of ram. Top of ram on sandybridge systems |
| 74 | * is where the TSEG region resides. However, it is not restricted |
| 75 | * to SMM mode until SMM has been relocated. By setting the region |
| 76 | * to cacheable it provides faster access when relocating the SMM |
| 77 | * handler as well as using the TSEG region for other purposes. */ |
Kyösti Mälkki | b84c833 | 2016-12-01 10:48:43 +0200 | [diff] [blame] | 78 | postcar_frame_add_mtrr(&pcf, top_of_ram, 8*MiB, MTRR_TYPE_WRBACK); |
Kyösti Mälkki | bfca670 | 2016-07-22 22:48:35 +0300 | [diff] [blame] | 79 | |
Arthur Heymans | 6fcd7b8 | 2018-06-03 12:16:24 +0200 | [diff] [blame^] | 80 | run_postcar_phase(&pcf); |
| 81 | |
| 82 | /* We do not return here. */ |
Kyösti Mälkki | a4ffe9d | 2016-06-27 13:24:11 +0300 | [diff] [blame] | 83 | } |