Martin Roth | 5474eb1 | 2018-05-26 19:22:33 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * converted to C 6/2004 yhlu |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 16 | /* This was originally for the e7500, modified for e7501 |
| 17 | * The primary differences are that 7501 apparently can |
| 18 | * support single channel RAM (i haven't tested), |
| 19 | * CAS1.5 is no longer supported, The ECC scrubber |
| 20 | * now supports a mode to zero RAM and init ECC in one step |
| 21 | * and the undocumented registers at 0x80 require new |
| 22 | * (undocumented) values determined by guesswork and |
| 23 | * comparison w/ OEM BIOS values. |
| 24 | * Steven James 02/06/2003 |
| 25 | */ |
| 26 | |
Kyösti Mälkki | 93b4ed9 | 2012-04-18 21:13:33 +0300 | [diff] [blame] | 27 | #include <stdint.h> |
| 28 | #include <device/pci_def.h> |
| 29 | #include <arch/io.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 30 | #include <device/mmio.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 31 | #include <device/pci_ops.h> |
Alexandru Gagniuc | af4bd59 | 2014-01-12 15:42:58 -0600 | [diff] [blame] | 32 | #include <lib.h> |
Kyösti Mälkki | 717b6e3 | 2018-05-17 14:16:03 +0300 | [diff] [blame] | 33 | #include <commonlib/helpers.h> |
Kyösti Mälkki | 93b4ed9 | 2012-04-18 21:13:33 +0300 | [diff] [blame] | 34 | #include <console/console.h> |
Kyösti Mälkki | 97c064f | 2012-04-18 20:33:35 +0300 | [diff] [blame] | 35 | #include <cpu/x86/mtrr.h> |
| 36 | #include <cpu/x86/cache.h> |
| 37 | #include <cpu/x86/msr.h> |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 38 | #include <assert.h> |
| 39 | #include <spd.h> |
| 40 | #include <sdram_mode.h> |
Kyösti Mälkki | ec55868 | 2019-01-09 13:33:39 +0200 | [diff] [blame] | 41 | #include <timestamp.h> |
Kyösti Mälkki | 9e581ec | 2020-01-07 11:16:35 +0200 | [diff] [blame] | 42 | #include <southbridge/intel/i82801dx/i82801dx.h> |
Kyösti Mälkki | 93b4ed9 | 2012-04-18 21:13:33 +0300 | [diff] [blame] | 43 | |
| 44 | #include "raminit.h" |
Kyösti Mälkki | 0a0d5e8 | 2011-10-31 14:18:33 +0200 | [diff] [blame] | 45 | #include "e7505.h" |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 46 | |
| 47 | /*----------------------------------------------------------------------------- |
| 48 | Definitions: |
| 49 | -----------------------------------------------------------------------------*/ |
| 50 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 51 | #if CONFIG(DEBUG_RAM_SETUP) |
Stefan Reinauer | 65b72ab | 2015-01-05 12:59:54 -0800 | [diff] [blame] | 52 | #define RAM_DEBUG_MESSAGE(x) printk(BIOS_DEBUG, x) |
| 53 | #define RAM_DEBUG_HEX32(x) printk(BIOS_DEBUG, "%08x", x) |
| 54 | #define RAM_DEBUG_HEX8(x) printk(BIOS_DEBUG, "%02x", x) |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 55 | #else |
| 56 | #define RAM_DEBUG_MESSAGE(x) |
| 57 | #define RAM_DEBUG_HEX32(x) |
| 58 | #define RAM_DEBUG_HEX8(x) |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 59 | #endif |
| 60 | |
| 61 | #define E7501_SDRAM_MODE (SDRAM_BURST_INTERLEAVED | SDRAM_BURST_4) |
| 62 | #define SPD_ERROR "Error reading SPD info\n" |
| 63 | |
Kyösti Mälkki | 4c0e277 | 2018-05-17 14:16:03 +0300 | [diff] [blame] | 64 | #define MCHDEV PCI_DEV(0, 0, 0) |
| 65 | #define RASDEV PCI_DEV(0, 0, 1) |
| 66 | #define AGPDEV PCI_DEV(0, 1, 0) |
| 67 | #define D060DEV PCI_DEV(0, 6, 0) |
Kyösti Mälkki | 5bd271b | 2012-04-10 16:11:53 +0300 | [diff] [blame] | 68 | |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 69 | // NOTE: This used to be 0x100000. |
| 70 | // That doesn't work on systems where A20M# is asserted, because |
| 71 | // attempts to access 0x1000NN end up accessing 0x0000NN. |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 72 | #define RCOMP_MMIO ((u8 *)0x200000) |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 73 | |
| 74 | struct dimm_size { |
| 75 | unsigned long side1; |
| 76 | unsigned long side2; |
| 77 | }; |
| 78 | |
| 79 | static const uint32_t refresh_frequency[] = { |
| 80 | /* Relative frequency (array value) of each E7501 Refresh Mode Select |
| 81 | * (RMS) value (array index) |
| 82 | * 0 == least frequent refresh (longest interval between refreshes) |
| 83 | * [0] disabled -> 0 |
| 84 | * [1] 15.6 usec -> 2 |
| 85 | * [2] 7.8 usec -> 3 |
| 86 | * [3] 64 usec -> 1 |
| 87 | * [4] reserved -> 0 |
| 88 | * [5] reserved -> 0 |
| 89 | * [6] reserved -> 0 |
| 90 | * [7] 64 clocks -> 4 |
| 91 | */ |
| 92 | 0, 2, 3, 1, 0, 0, 0, 4 |
| 93 | }; |
| 94 | |
| 95 | static const uint32_t refresh_rate_map[] = { |
| 96 | /* Map the JEDEC spd refresh rates (array index) to E7501 Refresh Mode |
| 97 | * Select values (array value) |
| 98 | * These are all the rates defined by JESD21-C Appendix D, Rev. 1.0 |
| 99 | * The E7501 supports only 15.6 us (1), 7.8 us (2), 64 us (3), and |
| 100 | * 64 clock (481 ns) (7) refresh. |
| 101 | * [0] == 15.625 us -> 15.6 us |
| 102 | * [1] == 3.9 us -> 481 ns |
| 103 | * [2] == 7.8 us -> 7.8 us |
| 104 | * [3] == 31.3 us -> 15.6 us |
| 105 | * [4] == 62.5 us -> 15.6 us |
| 106 | * [5] == 125 us -> 64 us |
| 107 | */ |
| 108 | 1, 7, 2, 1, 1, 3 |
| 109 | }; |
| 110 | |
| 111 | #define MAX_SPD_REFRESH_RATE ((sizeof(refresh_rate_map) / sizeof(uint32_t)) - 1) |
| 112 | |
| 113 | // SPD parameters that must match for dual-channel operation |
| 114 | static const uint8_t dual_channel_parameters[] = { |
| 115 | SPD_MEMORY_TYPE, |
| 116 | SPD_MODULE_VOLTAGE, |
| 117 | SPD_NUM_COLUMNS, |
| 118 | SPD_NUM_ROWS, |
| 119 | SPD_NUM_DIMM_BANKS, |
| 120 | SPD_PRIMARY_SDRAM_WIDTH, |
| 121 | SPD_NUM_BANKS_PER_SDRAM |
| 122 | }; |
| 123 | |
Kyösti Mälkki | 77e4f7d | 2012-04-18 19:47:56 +0300 | [diff] [blame] | 124 | /* Comments here are remains of e7501 or even 855PM. |
| 125 | * They might be partially (in)correct for e7505. |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 126 | */ |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 127 | |
Kyösti Mälkki | 77e4f7d | 2012-04-18 19:47:56 +0300 | [diff] [blame] | 128 | /* (DRAM Read Timing Control, if similar to 855PM?) |
| 129 | * 0x80 - 0x81 documented differently for e7505 |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 130 | * This register has something to do with CAS latencies, |
Martin Roth | 128c104 | 2016-11-18 09:29:03 -0700 | [diff] [blame] | 131 | * possibly this is the real chipset control. |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 132 | * At 0x00 CAS latency 1.5 works. |
| 133 | * At 0x06 CAS latency 2.5 works. |
| 134 | * At 0x01 CAS latency 2.0 works. |
Kyösti Mälkki | 77e4f7d | 2012-04-18 19:47:56 +0300 | [diff] [blame] | 135 | * |
| 136 | * This is still undocumented in e7501, but with different values |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 137 | * CAS 2.0 values taken from Intel BIOS settings, others are a guess |
| 138 | * and may be terribly wrong. Old values preserved as comments until I |
| 139 | * figure this out for sure. |
| 140 | * e7501 docs claim that CAS1.5 is unsupported, so it may or may not |
| 141 | * work at all. |
| 142 | * Steven James 02/06/2003 |
Kyösti Mälkki | 77e4f7d | 2012-04-18 19:47:56 +0300 | [diff] [blame] | 143 | * |
| 144 | * NOTE: values now configured in configure_e7501_cas_latency() based |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 145 | * on SPD info and total number of DIMMs (per Intel) |
| 146 | */ |
| 147 | |
Kyösti Mälkki | 77e4f7d | 2012-04-18 19:47:56 +0300 | [diff] [blame] | 148 | /* FDHC - Fixed DRAM Hole Control ??? |
| 149 | * 0x58 undocumented for e7505, memory hole in southbridge configuration? |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 150 | * [7:7] Hole_Enable |
| 151 | * 0 == No memory Hole |
| 152 | * 1 == Memory Hole from 15MB to 16MB |
| 153 | * [6:0] Reserved |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 154 | */ |
| 155 | |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 156 | /* Another Intel undocumented register |
| 157 | * 0x88 - 0x8B |
| 158 | * [31:31] Purpose unknown |
| 159 | * [26:26] Master DLL Reset? |
| 160 | * 0 == Normal operation? |
| 161 | * 1 == Reset? |
| 162 | * [07:07] Periodic memory recalibration? |
| 163 | * 0 == Disabled? |
| 164 | * 1 == Enabled? |
| 165 | * [04:04] Receive FIFO RE-Sync? |
| 166 | * 0 == Normal operation? |
| 167 | * 1 == Reset? |
| 168 | */ |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 169 | |
Kyösti Mälkki | 77e4f7d | 2012-04-18 19:47:56 +0300 | [diff] [blame] | 170 | /* DDR RECOMP tables */ |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 171 | // Slew table for 2x drive? |
Kyösti Mälkki | 5bd271b | 2012-04-10 16:11:53 +0300 | [diff] [blame] | 172 | static const uint32_t slew_2x[] = { |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 173 | 0x00000000, 0x76543210, 0xffffeca8, 0xffffffff, |
| 174 | 0x21000000, 0xa8765432, 0xffffffec, 0xffffffff, |
| 175 | }; |
| 176 | |
| 177 | // Pull Up / Pull Down offset table, if analogous to IXP2800? |
Kyösti Mälkki | 5bd271b | 2012-04-10 16:11:53 +0300 | [diff] [blame] | 178 | static const uint32_t pull_updown_offset_table[] = { |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 179 | 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, |
| 180 | 0x88888888, 0x88888888, 0x88888888, 0x88888888, |
| 181 | }; |
| 182 | |
| 183 | /*----------------------------------------------------------------------------- |
| 184 | Delay functions: |
| 185 | -----------------------------------------------------------------------------*/ |
| 186 | |
Kyösti Mälkki | 5c1ff92 | 2012-04-10 19:55:19 +0300 | [diff] [blame] | 187 | /* Estimate that SLOW_DOWN_IO takes about 1 us */ |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 188 | #define SLOW_DOWN_IO inb(0x80) |
Kyösti Mälkki | 77e4f7d | 2012-04-18 19:47:56 +0300 | [diff] [blame] | 189 | static void local_udelay(int i) |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 190 | { |
Kyösti Mälkki | 5c1ff92 | 2012-04-10 19:55:19 +0300 | [diff] [blame] | 191 | while (i--) { |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 192 | SLOW_DOWN_IO; |
| 193 | } |
| 194 | } |
| 195 | |
Kyösti Mälkki | 5c1ff92 | 2012-04-10 19:55:19 +0300 | [diff] [blame] | 196 | /* delay for 200us */ |
| 197 | #define DO_DELAY local_udelay(200) |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 198 | #define EXTRA_DELAY DO_DELAY |
| 199 | |
Kyösti Mälkki | 0a0d5e8 | 2011-10-31 14:18:33 +0200 | [diff] [blame] | 200 | /*----------------------------------------------------------------------------- |
Kyösti Mälkki | 26c7b86 | 2012-04-12 22:46:23 +0300 | [diff] [blame] | 201 | Handle (undocumented) control bits MCHTST and PCI_DEV(0,6,0) |
Kyösti Mälkki | 0a0d5e8 | 2011-10-31 14:18:33 +0200 | [diff] [blame] | 202 | -----------------------------------------------------------------------------*/ |
Kyösti Mälkki | 26c7b86 | 2012-04-12 22:46:23 +0300 | [diff] [blame] | 203 | typedef enum { |
| 204 | MCHTST_CMD_0, |
| 205 | D060_ENABLE, |
| 206 | D060_DISABLE, |
| 207 | RCOMP_BAR_ENABLE, |
| 208 | RCOMP_BAR_DISABLE, |
| 209 | } mchtst_cc; |
| 210 | |
| 211 | typedef enum { |
| 212 | D060_CMD_0, |
| 213 | D060_CMD_1, |
| 214 | } d060_cc; |
| 215 | |
| 216 | typedef enum { |
| 217 | RCOMP_HOLD, |
| 218 | RCOMP_RELEASE, |
| 219 | RCOMP_SMR_00, |
| 220 | RCOMP_SMR_01, |
| 221 | } rcomp_smr_cc; |
| 222 | |
| 223 | /** |
| 224 | * MCHTST - 0xF4 - 0xF7 -- Based on similarity to 855PM |
| 225 | * |
| 226 | * [31:31] Purpose unknown |
| 227 | * [30:30] Purpose unknown |
| 228 | * [29:23] Unknown - not used? |
| 229 | * [22:22] System Memory MMR Enable |
| 230 | * 0 == Disable: mem space and BAR at 0x14 are not accessible |
| 231 | * 1 == Enable: mem space and BAR at 0x14 are accessible |
| 232 | * [21:20] Purpose unknown |
| 233 | * [19:02] Unknown - not used? |
| 234 | * [01:01] D6EN (Device #6 enable) |
| 235 | * 0 == Disable |
| 236 | * 1 == Enable |
| 237 | * [00:00] Unknown - not used? |
| 238 | */ |
Kyösti Mälkki | 77e4f7d | 2012-04-18 19:47:56 +0300 | [diff] [blame] | 239 | static void mchtest_control(mchtst_cc cmd) |
Kyösti Mälkki | 26c7b86 | 2012-04-12 22:46:23 +0300 | [diff] [blame] | 240 | { |
| 241 | uint32_t dword = pci_read_config32(MCHDEV, MCHTST); |
| 242 | switch (cmd) { |
| 243 | case MCHTST_CMD_0: |
| 244 | dword &= ~(3 << 30); |
| 245 | break; |
| 246 | case RCOMP_BAR_ENABLE: |
| 247 | dword |= (1 << 22); |
| 248 | break; |
| 249 | case RCOMP_BAR_DISABLE: |
| 250 | dword &= ~(1 << 22); |
| 251 | break; |
| 252 | case D060_ENABLE: |
| 253 | dword |= (1 << 1); |
| 254 | break; |
| 255 | case D060_DISABLE: |
| 256 | dword &= ~(1 << 1); |
| 257 | break; |
| 258 | }; |
| 259 | pci_write_config32(MCHDEV, MCHTST, dword); |
| 260 | } |
| 261 | |
Kyösti Mälkki | 0a0d5e8 | 2011-10-31 14:18:33 +0200 | [diff] [blame] | 262 | |
| 263 | /** |
| 264 | * |
| 265 | */ |
Kyösti Mälkki | 77e4f7d | 2012-04-18 19:47:56 +0300 | [diff] [blame] | 266 | static void d060_control(d060_cc cmd) |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 267 | { |
Kyösti Mälkki | 26c7b86 | 2012-04-12 22:46:23 +0300 | [diff] [blame] | 268 | mchtest_control(D060_ENABLE); |
| 269 | uint32_t dword = pci_read_config32(D060DEV, 0xf0); |
| 270 | switch (cmd) { |
| 271 | case D060_CMD_0: |
| 272 | dword |= (1 << 2); |
| 273 | break; |
| 274 | case D060_CMD_1: |
| 275 | dword |= (3 << 27); |
| 276 | break; |
| 277 | } |
Kyösti Mälkki | 5bd271b | 2012-04-10 16:11:53 +0300 | [diff] [blame] | 278 | pci_write_config32(D060DEV, 0xf0, dword); |
Kyösti Mälkki | 26c7b86 | 2012-04-12 22:46:23 +0300 | [diff] [blame] | 279 | mchtest_control(D060_DISABLE); |
Kyösti Mälkki | 0a0d5e8 | 2011-10-31 14:18:33 +0200 | [diff] [blame] | 280 | } |
| 281 | |
| 282 | /** |
| 283 | * |
| 284 | */ |
Kyösti Mälkki | 77e4f7d | 2012-04-18 19:47:56 +0300 | [diff] [blame] | 285 | static void rcomp_smr_control(rcomp_smr_cc cmd) |
Kyösti Mälkki | 0a0d5e8 | 2011-10-31 14:18:33 +0200 | [diff] [blame] | 286 | { |
Kyösti Mälkki | 26c7b86 | 2012-04-12 22:46:23 +0300 | [diff] [blame] | 287 | uint32_t dword = read32(RCOMP_MMIO + SMRCTL); |
| 288 | switch (cmd) { |
| 289 | case RCOMP_HOLD: |
| 290 | dword |= (1 << 9); |
| 291 | break; |
| 292 | case RCOMP_RELEASE: |
| 293 | dword &= ~((1 << 9) | (3 << 0)); |
| 294 | dword |= (1 << 10) | (1 << 0); |
| 295 | break; |
| 296 | case RCOMP_SMR_00: |
| 297 | dword &= ~(1 << 8); |
| 298 | break; |
| 299 | case RCOMP_SMR_01: |
| 300 | dword |= (1 << 10) | (1 << 8); |
| 301 | break; |
Kyösti Mälkki | 0a0d5e8 | 2011-10-31 14:18:33 +0200 | [diff] [blame] | 302 | } |
Kyösti Mälkki | 26c7b86 | 2012-04-12 22:46:23 +0300 | [diff] [blame] | 303 | write32(RCOMP_MMIO + SMRCTL, dword); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 304 | } |
| 305 | |
| 306 | /*----------------------------------------------------------------------------- |
| 307 | Serial presence detect (SPD) functions: |
| 308 | -----------------------------------------------------------------------------*/ |
| 309 | |
Kyösti Mälkki | 0a0d5e8 | 2011-10-31 14:18:33 +0200 | [diff] [blame] | 310 | static void die_on_spd_error(int spd_return_value) |
| 311 | { |
| 312 | if (spd_return_value < 0) |
| 313 | die("Error reading SPD info\n"); |
| 314 | } |
| 315 | |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 316 | /** |
| 317 | * Calculate the page size for each physical bank of the DIMM: |
| 318 | * log2(page size) = (# columns) + log2(data width) |
| 319 | * |
| 320 | * NOTE: Page size is the total number of data bits in a row. |
| 321 | * |
| 322 | * @param dimm_socket_address SMBus address of DIMM socket to interrogate. |
| 323 | * @return log2(page size) for each side of the DIMM. |
| 324 | */ |
| 325 | static struct dimm_size sdram_spd_get_page_size(uint16_t dimm_socket_address) |
| 326 | { |
| 327 | uint16_t module_data_width; |
| 328 | int value; |
| 329 | struct dimm_size pgsz; |
| 330 | |
| 331 | pgsz.side1 = 0; |
| 332 | pgsz.side2 = 0; |
| 333 | |
| 334 | // Side 1 |
Kyösti Mälkki | 9e581ec | 2020-01-07 11:16:35 +0200 | [diff] [blame] | 335 | value = smbus_read_byte(dimm_socket_address, SPD_NUM_COLUMNS); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 336 | if (value < 0) |
| 337 | goto hw_err; |
| 338 | pgsz.side1 = value & 0xf; // # columns in bank 1 |
| 339 | |
| 340 | /* Get the module data width and convert it to a power of two */ |
Kyösti Mälkki | 9e581ec | 2020-01-07 11:16:35 +0200 | [diff] [blame] | 341 | value = smbus_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_MSB); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 342 | if (value < 0) |
| 343 | goto hw_err; |
| 344 | module_data_width = (value & 0xff) << 8; |
| 345 | |
Kyösti Mälkki | 9e581ec | 2020-01-07 11:16:35 +0200 | [diff] [blame] | 346 | value = smbus_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_LSB); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 347 | if (value < 0) |
| 348 | goto hw_err; |
| 349 | module_data_width |= (value & 0xff); |
| 350 | |
| 351 | pgsz.side1 += log2(module_data_width); |
| 352 | |
| 353 | /* side two */ |
Kyösti Mälkki | 9e581ec | 2020-01-07 11:16:35 +0200 | [diff] [blame] | 354 | value = smbus_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 355 | if (value < 0) |
| 356 | goto hw_err; |
| 357 | if (value > 2) |
| 358 | die("Bad SPD value\n"); |
| 359 | if (value == 2) { |
| 360 | |
| 361 | pgsz.side2 = pgsz.side1; // Assume symmetric banks until we know differently |
Kyösti Mälkki | 9e581ec | 2020-01-07 11:16:35 +0200 | [diff] [blame] | 362 | value = smbus_read_byte(dimm_socket_address, SPD_NUM_COLUMNS); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 363 | if (value < 0) |
| 364 | goto hw_err; |
| 365 | if ((value & 0xf0) != 0) { |
| 366 | // Asymmetric banks |
| 367 | pgsz.side2 -= value & 0xf; /* Subtract out columns on side 1 */ |
| 368 | pgsz.side2 += (value >> 4) & 0xf; /* Add in columns on side 2 */ |
| 369 | } |
| 370 | } |
| 371 | |
| 372 | return pgsz; |
| 373 | |
| 374 | hw_err: |
| 375 | die(SPD_ERROR); |
| 376 | return pgsz; // Never reached |
| 377 | } |
| 378 | |
| 379 | /** |
| 380 | * Read the width in bits of each DIMM side's DRAMs via SPD (i.e. 4, 8, 16). |
| 381 | * |
| 382 | * @param dimm_socket_address SMBus address of DIMM socket to interrogate. |
| 383 | * @return Width in bits of each DIMM side's DRAMs. |
| 384 | */ |
| 385 | static struct dimm_size sdram_spd_get_width(uint16_t dimm_socket_address) |
| 386 | { |
| 387 | int value; |
| 388 | struct dimm_size width; |
| 389 | |
| 390 | width.side1 = 0; |
| 391 | width.side2 = 0; |
| 392 | |
Kyösti Mälkki | 9e581ec | 2020-01-07 11:16:35 +0200 | [diff] [blame] | 393 | value = smbus_read_byte(dimm_socket_address, SPD_PRIMARY_SDRAM_WIDTH); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 394 | die_on_spd_error(value); |
| 395 | |
| 396 | width.side1 = value & 0x7f; // Mask off bank 2 flag |
| 397 | |
| 398 | if (value & 0x80) { |
| 399 | width.side2 = width.side1 << 1; // Bank 2 exists and is double-width |
| 400 | } else { |
| 401 | // If bank 2 exists, it's the same width as bank 1 |
Kyösti Mälkki | 9e581ec | 2020-01-07 11:16:35 +0200 | [diff] [blame] | 402 | value = smbus_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 403 | die_on_spd_error(value); |
| 404 | |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 405 | if (value == 2) |
| 406 | width.side2 = width.side1; |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 407 | } |
| 408 | |
| 409 | return width; |
| 410 | } |
| 411 | |
| 412 | /** |
| 413 | * Calculate the log base 2 size in bits of both DIMM sides. |
| 414 | * |
| 415 | * log2(# bits) = (# columns) + log2(data width) + |
| 416 | * (# rows) + log2(banks per SDRAM) |
| 417 | * |
| 418 | * Note that it might be easier to use SPD byte 31 here, it has the DIMM size |
| 419 | * as a multiple of 4MB. The way we do it now we can size both sides of an |
| 420 | * asymmetric DIMM. |
| 421 | * |
| 422 | * @param dimm_socket_address SMBus address of DIMM socket to interrogate. |
| 423 | * @return log2(number of bits) for each side of the DIMM. |
| 424 | */ |
Martin Roth | 468d02c | 2019-10-23 21:44:42 -0600 | [diff] [blame] | 425 | static struct dimm_size spd_get_dimm_size(unsigned int dimm_socket_address) |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 426 | { |
| 427 | int value; |
| 428 | |
| 429 | // Start with log2(page size) |
| 430 | struct dimm_size sz = sdram_spd_get_page_size(dimm_socket_address); |
| 431 | |
| 432 | if (sz.side1 > 0) { |
| 433 | |
Kyösti Mälkki | 9e581ec | 2020-01-07 11:16:35 +0200 | [diff] [blame] | 434 | value = smbus_read_byte(dimm_socket_address, SPD_NUM_ROWS); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 435 | die_on_spd_error(value); |
| 436 | |
| 437 | sz.side1 += value & 0xf; |
| 438 | |
| 439 | if (sz.side2 > 0) { |
| 440 | |
| 441 | // Double-sided DIMM |
| 442 | if (value & 0xF0) |
| 443 | sz.side2 += value >> 4; // Asymmetric |
| 444 | else |
| 445 | sz.side2 += value; // Symmetric |
| 446 | } |
| 447 | |
Kyösti Mälkki | 9e581ec | 2020-01-07 11:16:35 +0200 | [diff] [blame] | 448 | value = smbus_read_byte(dimm_socket_address, |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 449 | SPD_NUM_BANKS_PER_SDRAM); |
| 450 | die_on_spd_error(value); |
| 451 | |
| 452 | value = log2(value); |
| 453 | sz.side1 += value; |
| 454 | if (sz.side2 > 0) |
| 455 | sz.side2 += value; |
| 456 | } |
| 457 | |
| 458 | return sz; |
| 459 | } |
| 460 | |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 461 | /** |
| 462 | * Determine whether two DIMMs have the same value for an SPD parameter. |
| 463 | * |
| 464 | * @param spd_byte_number The SPD byte number to compare in both DIMMs. |
| 465 | * @param dimm0_address SMBus address of the 1st DIMM socket to interrogate. |
| 466 | * @param dimm1_address SMBus address of the 2nd DIMM socket to interrogate. |
| 467 | * @return 1 if both DIMM sockets report the same value for the specified |
| 468 | * SPD parameter, 0 if the values differed or an error occurred. |
| 469 | */ |
| 470 | static uint8_t are_spd_values_equal(uint8_t spd_byte_number, |
| 471 | uint16_t dimm0_address, |
| 472 | uint16_t dimm1_address) |
| 473 | { |
| 474 | uint8_t bEqual = 0; |
Kyösti Mälkki | 9e581ec | 2020-01-07 11:16:35 +0200 | [diff] [blame] | 475 | int dimm0_value = smbus_read_byte(dimm0_address, spd_byte_number); |
| 476 | int dimm1_value = smbus_read_byte(dimm1_address, spd_byte_number); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 477 | |
| 478 | if ((dimm0_value >= 0) && (dimm1_value >= 0) |
| 479 | && (dimm0_value == dimm1_value)) |
| 480 | bEqual = 1; |
| 481 | |
| 482 | return bEqual; |
| 483 | } |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 484 | |
| 485 | /** |
| 486 | * Scan for compatible DIMMs. |
| 487 | * |
| 488 | * The code in this module only supports dual-channel operation, so we test |
| 489 | * that compatible DIMMs are paired. |
| 490 | * |
| 491 | * @param ctrl PCI addresses of memory controller functions, and SMBus |
| 492 | * addresses of DIMM slots on the mainboard. |
| 493 | * @return A bitmask indicating which of the possible sockets for each channel |
| 494 | * was found to contain a compatible DIMM. |
| 495 | * Bit 0 corresponds to the closest socket for channel 0 |
| 496 | * Bit 1 to the next socket for channel 0 |
| 497 | * ... |
| 498 | * Bit MAX_DIMM_SOCKETS_PER_CHANNEL-1 to the last socket for channel 0 |
| 499 | * Bit MAX_DIMM_SOCKETS_PER_CHANNEL is the closest socket for channel 1 |
| 500 | * ... |
| 501 | * Bit 2*MAX_DIMM_SOCKETS_PER_CHANNEL-1 is the last socket for channel 1 |
| 502 | */ |
| 503 | static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl) |
| 504 | { |
| 505 | int i; |
| 506 | uint8_t dimm_mask = 0; |
| 507 | |
| 508 | // Have to increase size of dimm_mask if this assertion is violated |
| 509 | ASSERT(MAX_DIMM_SOCKETS_PER_CHANNEL <= 4); |
| 510 | |
| 511 | // Find DIMMs we can support on channel 0. |
| 512 | // Then see if the corresponding channel 1 DIMM has the same parameters, |
| 513 | // since we only support dual-channel. |
| 514 | |
| 515 | for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) { |
| 516 | |
| 517 | uint16_t channel0_dimm = ctrl->channel0[i]; |
| 518 | uint16_t channel1_dimm = ctrl->channel1[i]; |
| 519 | uint8_t bDualChannel = 1; |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 520 | struct dimm_size page_size; |
| 521 | struct dimm_size sdram_width; |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 522 | int spd_value; |
| 523 | |
| 524 | if (channel0_dimm == 0) |
| 525 | continue; // No such socket on this mainboard |
| 526 | |
Kyösti Mälkki | 9e581ec | 2020-01-07 11:16:35 +0200 | [diff] [blame] | 527 | if (smbus_read_byte(channel0_dimm, SPD_MEMORY_TYPE) != |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 528 | SPD_MEMORY_TYPE_SDRAM_DDR) |
| 529 | continue; |
| 530 | |
Kyösti Mälkki | 9e581ec | 2020-01-07 11:16:35 +0200 | [diff] [blame] | 531 | if (smbus_read_byte(channel0_dimm, SPD_MODULE_VOLTAGE) != |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 532 | SPD_VOLTAGE_SSTL2) |
| 533 | continue; // Unsupported voltage |
| 534 | |
| 535 | // E7501 does not support unregistered DIMMs |
Kyösti Mälkki | 9e581ec | 2020-01-07 11:16:35 +0200 | [diff] [blame] | 536 | spd_value = smbus_read_byte(channel0_dimm, SPD_MODULE_ATTRIBUTES); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 537 | if (!(spd_value & MODULE_REGISTERED) || (spd_value < 0)) |
| 538 | continue; |
| 539 | |
| 540 | // Must support burst = 4 for dual-channel operation on E7501 |
| 541 | // NOTE: for single-channel, burst = 8 is required |
Kyösti Mälkki | 9e581ec | 2020-01-07 11:16:35 +0200 | [diff] [blame] | 542 | spd_value = smbus_read_byte(channel0_dimm, |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 543 | SPD_SUPPORTED_BURST_LENGTHS); |
| 544 | if (!(spd_value & SPD_BURST_LENGTH_4) || (spd_value < 0)) |
| 545 | continue; |
| 546 | |
| 547 | page_size = sdram_spd_get_page_size(channel0_dimm); |
| 548 | sdram_width = sdram_spd_get_width(channel0_dimm); |
| 549 | |
| 550 | // Validate DIMM page size |
| 551 | // The E7501 only supports page sizes of 4, 8, 16, or 32 KB per channel |
| 552 | // NOTE: 4 KB = 32 Kb = 2^15 |
| 553 | // 32 KB = 262 Kb = 2^18 |
| 554 | |
| 555 | if ((page_size.side1 < 15) || (page_size.side1 > 18)) |
| 556 | continue; |
| 557 | |
| 558 | // If DIMM is double-sided, verify side2 page size |
| 559 | if (page_size.side2 != 0) { |
| 560 | if ((page_size.side2 < 15) |
| 561 | || (page_size.side2 > 18)) |
| 562 | continue; |
| 563 | } |
| 564 | // Validate SDRAM width |
| 565 | // The E7501 only supports x4 and x8 devices |
| 566 | |
| 567 | if ((sdram_width.side1 != 4) && (sdram_width.side1 != 8)) |
| 568 | continue; |
| 569 | |
| 570 | // If DIMM is double-sided, verify side2 width |
| 571 | if (sdram_width.side2 != 0) { |
| 572 | if ((sdram_width.side2 != 4) |
| 573 | && (sdram_width.side2 != 8)) |
| 574 | continue; |
| 575 | } |
Kyösti Mälkki | b71fb52 | 2020-01-07 11:16:35 +0200 | [diff] [blame] | 576 | |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 577 | // Channel 0 DIMM looks compatible. |
| 578 | // Now see if it is paired with the proper DIMM on channel 1. |
| 579 | |
| 580 | ASSERT(channel1_dimm != 0); // No such socket on this mainboard?? |
| 581 | |
| 582 | // NOTE: unpopulated DIMMs cause read to fail |
Kyösti Mälkki | 9e581ec | 2020-01-07 11:16:35 +0200 | [diff] [blame] | 583 | spd_value = smbus_read_byte(channel1_dimm, SPD_MODULE_ATTRIBUTES); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 584 | if (!(spd_value & MODULE_REGISTERED) || (spd_value < 0)) { |
| 585 | |
Stefan Reinauer | 65b72ab | 2015-01-05 12:59:54 -0800 | [diff] [blame] | 586 | printk(BIOS_DEBUG, "Skipping un-matched DIMMs - only dual-channel operation supported\n"); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 587 | continue; |
| 588 | } |
Kyösti Mälkki | b71fb52 | 2020-01-07 11:16:35 +0200 | [diff] [blame] | 589 | |
Kyösti Mälkki | 9e581ec | 2020-01-07 11:16:35 +0200 | [diff] [blame] | 590 | spd_value = smbus_read_byte(channel1_dimm, |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 591 | SPD_SUPPORTED_BURST_LENGTHS); |
| 592 | if (!(spd_value & SPD_BURST_LENGTH_4) || (spd_value < 0)) |
| 593 | continue; |
| 594 | |
| 595 | int j; |
| 596 | for (j = 0; j < sizeof(dual_channel_parameters); ++j) { |
| 597 | if (!are_spd_values_equal |
| 598 | (dual_channel_parameters[j], channel0_dimm, |
| 599 | channel1_dimm)) { |
| 600 | |
| 601 | bDualChannel = 0; |
| 602 | break; |
| 603 | } |
| 604 | } |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 605 | |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 606 | if (bDualChannel) { |
Kyösti Mälkki | 58d6ff1 | 2018-06-02 18:38:04 +0300 | [diff] [blame] | 607 | // This DIMM pair is usable |
| 608 | dimm_mask |= 1 << i; |
| 609 | dimm_mask |= 1 << (MAX_DIMM_SOCKETS_PER_CHANNEL + i); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 610 | } else |
Stefan Reinauer | 65b72ab | 2015-01-05 12:59:54 -0800 | [diff] [blame] | 611 | printk(BIOS_DEBUG, "Skipping un-matched DIMMs - only dual-channel operation supported\n"); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 612 | } |
| 613 | |
| 614 | return dimm_mask; |
| 615 | } |
| 616 | |
| 617 | /*----------------------------------------------------------------------------- |
| 618 | SDRAM configuration functions: |
| 619 | -----------------------------------------------------------------------------*/ |
| 620 | |
| 621 | /** |
| 622 | * Send the specified command to all DIMMs. |
| 623 | * |
| 624 | * @param command Specifies the command to be sent to the DIMMs. |
| 625 | * @param jedec_mode_bits For the MRS & EMRS commands, bits 0-12 contain the |
| 626 | * register value in JEDEC format. |
| 627 | */ |
| 628 | static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits) |
| 629 | { |
Kyösti Mälkki | 0a0d5e8 | 2011-10-31 14:18:33 +0200 | [diff] [blame] | 630 | uint8_t dimm_start_64M_multiple; |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 631 | uintptr_t dimm_start_address; |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 632 | uint32_t dram_controller_mode; |
Kyösti Mälkki | 0a0d5e8 | 2011-10-31 14:18:33 +0200 | [diff] [blame] | 633 | uint8_t i; |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 634 | |
| 635 | // Configure the RAM command |
Kyösti Mälkki | 5bd271b | 2012-04-10 16:11:53 +0300 | [diff] [blame] | 636 | dram_controller_mode = pci_read_config32(MCHDEV, DRC); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 637 | dram_controller_mode &= 0xFFFFFF8F; |
| 638 | dram_controller_mode |= command; |
Kyösti Mälkki | 5bd271b | 2012-04-10 16:11:53 +0300 | [diff] [blame] | 639 | pci_write_config32(MCHDEV, DRC, dram_controller_mode); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 640 | |
| 641 | // RAM_COMMAND_NORMAL is an exception. |
| 642 | // It affects only the memory controller and does not need to be "sent" to the DIMMs. |
Kyösti Mälkki | 5c1ff92 | 2012-04-10 19:55:19 +0300 | [diff] [blame] | 643 | if (command == RAM_COMMAND_NORMAL) { |
| 644 | EXTRA_DELAY; |
Kyösti Mälkki | 0a0d5e8 | 2011-10-31 14:18:33 +0200 | [diff] [blame] | 645 | return; |
Kyösti Mälkki | 5c1ff92 | 2012-04-10 19:55:19 +0300 | [diff] [blame] | 646 | } |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 647 | |
Kyösti Mälkki | 0a0d5e8 | 2011-10-31 14:18:33 +0200 | [diff] [blame] | 648 | // NOTE: for mode select commands, some of the location address bits are part of the command |
| 649 | // Map JEDEC mode bits to E7505 |
| 650 | if (command == RAM_COMMAND_MRS) { |
| 651 | // Host address lines [25:18] map to DIMM address lines [7:0] |
| 652 | // Host address lines [17:16] map to DIMM address lines [9:8] |
| 653 | // Host address lines [15:4] map to DIMM address lines [11:0] |
| 654 | dimm_start_address = (jedec_mode_bits & 0x00ff) << 18; |
| 655 | dimm_start_address |= (jedec_mode_bits & 0x0300) << 8; |
| 656 | dimm_start_address |= (jedec_mode_bits & 0x0fff) << 4; |
| 657 | } else if (command == RAM_COMMAND_EMRS) { |
| 658 | // Host address lines [15:4] map to DIMM address lines [11:0] |
| 659 | dimm_start_address = (jedec_mode_bits << 4); |
| 660 | } else { |
| 661 | ASSERT(jedec_mode_bits == 0); |
| 662 | dimm_start_address = 0; |
| 663 | } |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 664 | |
Kyösti Mälkki | 0a0d5e8 | 2011-10-31 14:18:33 +0200 | [diff] [blame] | 665 | // Send the command to all DIMMs by accessing a memory location within each |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 666 | |
Kyösti Mälkki | 0a0d5e8 | 2011-10-31 14:18:33 +0200 | [diff] [blame] | 667 | dimm_start_64M_multiple = 0; |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 668 | |
Kyösti Mälkki | 77e4f7d | 2012-04-18 19:47:56 +0300 | [diff] [blame] | 669 | /* FIXME: Only address the number of rows present in the system? |
| 670 | * Seems like rows 4-7 overlap with 0-3. |
| 671 | */ |
Kyösti Mälkki | 0a0d5e8 | 2011-10-31 14:18:33 +0200 | [diff] [blame] | 672 | for (i = 0; i < (MAX_NUM_CHANNELS * MAX_DIMM_SOCKETS_PER_CHANNEL); ++i) { |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 673 | |
Kyösti Mälkki | 5bd271b | 2012-04-10 16:11:53 +0300 | [diff] [blame] | 674 | uint8_t dimm_end_64M_multiple = pci_read_config8(MCHDEV, DRB_ROW_0 + i); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 675 | |
Kyösti Mälkki | 0a0d5e8 | 2011-10-31 14:18:33 +0200 | [diff] [blame] | 676 | if (dimm_end_64M_multiple > dimm_start_64M_multiple) { |
| 677 | dimm_start_address &= 0x3ffffff; |
| 678 | dimm_start_address |= dimm_start_64M_multiple << 26; |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 679 | read32((void *)dimm_start_address); |
Kyösti Mälkki | 77e4f7d | 2012-04-18 19:47:56 +0300 | [diff] [blame] | 680 | // Set the start of the next DIMM |
Kyösti Mälkki | 0a0d5e8 | 2011-10-31 14:18:33 +0200 | [diff] [blame] | 681 | dimm_start_64M_multiple = dimm_end_64M_multiple; |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 682 | } |
| 683 | } |
Kyösti Mälkki | 5c1ff92 | 2012-04-10 19:55:19 +0300 | [diff] [blame] | 684 | EXTRA_DELAY; |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 685 | } |
| 686 | |
| 687 | /** |
| 688 | * Set the mode register of all DIMMs. |
| 689 | * |
| 690 | * The proper CAS# latency setting is added to the mode bits specified |
| 691 | * by the caller. |
| 692 | * |
| 693 | * @param jedec_mode_bits For the MRS & EMRS commands, bits 0-12 contain the |
| 694 | * register value in JEDEC format. |
| 695 | */ |
| 696 | static void set_ram_mode(uint16_t jedec_mode_bits) |
| 697 | { |
| 698 | ASSERT(!(jedec_mode_bits & SDRAM_CAS_MASK)); |
| 699 | |
| 700 | uint32_t dram_cas_latency = |
Kyösti Mälkki | 5bd271b | 2012-04-10 16:11:53 +0300 | [diff] [blame] | 701 | pci_read_config32(MCHDEV, DRT) & DRT_CAS_MASK; |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 702 | |
| 703 | switch (dram_cas_latency) { |
| 704 | case DRT_CAS_2_5: |
| 705 | jedec_mode_bits |= SDRAM_CAS_2_5; |
| 706 | break; |
| 707 | |
| 708 | case DRT_CAS_2_0: |
| 709 | jedec_mode_bits |= SDRAM_CAS_2_0; |
| 710 | break; |
| 711 | |
| 712 | default: |
| 713 | BUG(); |
| 714 | break; |
| 715 | } |
| 716 | |
| 717 | do_ram_command(RAM_COMMAND_MRS, jedec_mode_bits); |
| 718 | } |
| 719 | |
| 720 | /*----------------------------------------------------------------------------- |
Martin Roth | 128c104 | 2016-11-18 09:29:03 -0700 | [diff] [blame] | 721 | DIMM-independent configuration functions: |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 722 | -----------------------------------------------------------------------------*/ |
| 723 | |
| 724 | /** |
| 725 | * Configure the E7501's DRAM Row Boundary (DRB) registers for the memory |
| 726 | * present in the specified DIMM. |
| 727 | * |
| 728 | * @param dimm_log2_num_bits Specifies log2(number of bits) for each side of |
| 729 | * the DIMM. |
| 730 | * @param total_dram_64M_multiple Total DRAM in the system (as a multiple of |
| 731 | * 64 MB) for DIMMs < dimm_index. |
| 732 | * @param dimm_index Which DIMM pair is being processed |
| 733 | * (0..MAX_DIMM_SOCKETS_PER_CHANNEL). |
| 734 | * @return New multiple of 64 MB total DRAM in the system. |
| 735 | */ |
Martin Roth | 468d02c | 2019-10-23 21:44:42 -0600 | [diff] [blame] | 736 | static uint8_t configure_dimm_row_boundaries(struct dimm_size dimm_log2_num_bits, uint8_t total_dram_64M_multiple, unsigned int dimm_index) |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 737 | { |
| 738 | int i; |
| 739 | |
| 740 | ASSERT(dimm_index < MAX_DIMM_SOCKETS_PER_CHANNEL); |
| 741 | |
| 742 | // DIMM sides must be at least 32 MB |
| 743 | ASSERT(dimm_log2_num_bits.side1 >= 28); |
| 744 | ASSERT((dimm_log2_num_bits.side2 == 0) |
| 745 | || (dimm_log2_num_bits.side2 >= 28)); |
| 746 | |
| 747 | // In dual-channel mode, we are called only once for each pair of DIMMs. |
| 748 | // Each time we process twice the capacity of a single DIMM. |
| 749 | |
| 750 | // Convert single DIMM capacity to paired DIMM capacity |
| 751 | // (multiply by two ==> add 1 to log2) |
| 752 | dimm_log2_num_bits.side1++; |
| 753 | if (dimm_log2_num_bits.side2 > 0) |
| 754 | dimm_log2_num_bits.side2++; |
| 755 | |
| 756 | // Add the capacity of side 1 this DIMM pair (as a multiple of 64 MB) |
| 757 | // to the total capacity of the system |
| 758 | // NOTE: 64 MB == 512 Mb, and log2(512 Mb) == 29 |
| 759 | |
| 760 | total_dram_64M_multiple += (1 << (dimm_log2_num_bits.side1 - 29)); |
| 761 | |
| 762 | // Configure the boundary address for the row on side 1 |
Kyösti Mälkki | 5bd271b | 2012-04-10 16:11:53 +0300 | [diff] [blame] | 763 | pci_write_config8(MCHDEV, DRB_ROW_0 + (dimm_index << 1), |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 764 | total_dram_64M_multiple); |
| 765 | |
| 766 | // If the DIMMs are double-sided, add the capacity of side 2 this DIMM pair |
| 767 | // (as a multiple of 64 MB) to the total capacity of the system |
| 768 | if (dimm_log2_num_bits.side2 >= 29) |
| 769 | total_dram_64M_multiple += |
| 770 | (1 << (dimm_log2_num_bits.side2 - 29)); |
| 771 | |
| 772 | // Configure the boundary address for the row (if any) on side 2 |
Kyösti Mälkki | 5bd271b | 2012-04-10 16:11:53 +0300 | [diff] [blame] | 773 | pci_write_config8(MCHDEV, DRB_ROW_1 + (dimm_index << 1), |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 774 | total_dram_64M_multiple); |
| 775 | |
| 776 | // Update boundaries for rows subsequent to these. |
| 777 | // These settings will be overridden by a subsequent call if a populated physical slot exists |
| 778 | |
| 779 | for (i = dimm_index + 1; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) { |
Kyösti Mälkki | 5bd271b | 2012-04-10 16:11:53 +0300 | [diff] [blame] | 780 | pci_write_config8(MCHDEV, DRB_ROW_0 + (i << 1), |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 781 | total_dram_64M_multiple); |
Kyösti Mälkki | 5bd271b | 2012-04-10 16:11:53 +0300 | [diff] [blame] | 782 | pci_write_config8(MCHDEV, DRB_ROW_1 + (i << 1), |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 783 | total_dram_64M_multiple); |
| 784 | } |
| 785 | |
| 786 | return total_dram_64M_multiple; |
| 787 | } |
| 788 | |
| 789 | /** |
| 790 | * Set the E7501's DRAM row boundary addresses & its Top Of Low Memory (TOLM). |
| 791 | * |
| 792 | * If necessary, set up a remap window so we don't waste DRAM that ordinarily |
| 793 | * would lie behind addresses reserved for memory-mapped I/O. |
| 794 | * |
| 795 | * @param ctrl PCI addresses of memory controller functions, and SMBus |
| 796 | * addresses of DIMM slots on the mainboard. |
| 797 | * @param dimm_mask Bitmask of populated DIMMs, see spd_get_supported_dimms(). |
| 798 | */ |
| 799 | static void configure_e7501_ram_addresses(const struct mem_controller |
| 800 | *ctrl, uint8_t dimm_mask) |
| 801 | { |
| 802 | int i; |
| 803 | uint8_t total_dram_64M_multiple = 0; |
Kyösti Mälkki | 717b6e3 | 2018-05-17 14:16:03 +0300 | [diff] [blame] | 804 | uint64_t tolm, tom; |
| 805 | uint16_t reg; |
| 806 | |
Kyösti Mälkki | 4c0e277 | 2018-05-17 14:16:03 +0300 | [diff] [blame] | 807 | /* FIXME: Is there standard presence detect bit somewhere. */ |
| 808 | const int agp_slot_disabled = 1; |
| 809 | |
Kyösti Mälkki | 717b6e3 | 2018-05-17 14:16:03 +0300 | [diff] [blame] | 810 | /* Start with disabled remap range. */ |
| 811 | uint16_t remapbase_r = 0x3ff; |
| 812 | uint16_t remaplimit_r = 0; |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 813 | |
| 814 | // Configure the E7501's DRAM row boundaries |
| 815 | // Start by zeroing out the temporary initial configuration |
Kyösti Mälkki | 5bd271b | 2012-04-10 16:11:53 +0300 | [diff] [blame] | 816 | pci_write_config32(MCHDEV, DRB_ROW_0, 0); |
| 817 | pci_write_config32(MCHDEV, DRB_ROW_4, 0); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 818 | |
| 819 | for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) { |
| 820 | |
| 821 | uint16_t dimm_socket_address = ctrl->channel0[i]; |
| 822 | struct dimm_size sz; |
| 823 | |
| 824 | if (!(dimm_mask & (1 << i))) |
| 825 | continue; // This DIMM not present |
| 826 | |
| 827 | sz = spd_get_dimm_size(dimm_socket_address); |
| 828 | |
| 829 | RAM_DEBUG_MESSAGE("dimm size ="); |
| 830 | RAM_DEBUG_HEX32((u32)sz.side1); |
| 831 | RAM_DEBUG_MESSAGE(" "); |
| 832 | RAM_DEBUG_HEX32((u32)sz.side2); |
| 833 | RAM_DEBUG_MESSAGE("\n"); |
| 834 | |
| 835 | if (sz.side1 == 0) |
| 836 | die("Bad SPD value\n"); |
| 837 | |
| 838 | total_dram_64M_multiple = |
| 839 | configure_dimm_row_boundaries(sz, total_dram_64M_multiple, i); |
| 840 | } |
| 841 | |
Kyösti Mälkki | 717b6e3 | 2018-05-17 14:16:03 +0300 | [diff] [blame] | 842 | tom = total_dram_64M_multiple * 64ULL * MiB; |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 843 | |
Kyösti Mälkki | 717b6e3 | 2018-05-17 14:16:03 +0300 | [diff] [blame] | 844 | /* Reserve MMIO space. */ |
Kyösti Mälkki | 4c0e277 | 2018-05-17 14:16:03 +0300 | [diff] [blame] | 845 | tolm = 4ULL * GiB - 512 * MiB; |
| 846 | if (agp_slot_disabled) { |
| 847 | /* Reduce apertures to 2 x 4 MiB. */ |
| 848 | pci_write_config8(MCHDEV, APSIZE, 0x3F); |
| 849 | pci_write_config16(AGPDEV, APSIZE1, 0x3F); |
| 850 | } else { |
| 851 | /* Add MMIO reserve for 2 x 256 MiB apertures. */ |
| 852 | tolm -= 512 * MiB; |
| 853 | } |
Kyösti Mälkki | 717b6e3 | 2018-05-17 14:16:03 +0300 | [diff] [blame] | 854 | tolm = MIN(tolm, tom); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 855 | |
Kyösti Mälkki | 717b6e3 | 2018-05-17 14:16:03 +0300 | [diff] [blame] | 856 | /* The PCI memory hole overlaps memory setup the remap window. */ |
| 857 | if (tolm < tom) { |
| 858 | uint64_t remapbase = MAX(tom, 4ULL * GiB); |
| 859 | uint64_t remaplimit = remapbase + (4ULL * GiB - tolm); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 860 | |
Kyösti Mälkki | 717b6e3 | 2018-05-17 14:16:03 +0300 | [diff] [blame] | 861 | remapbase_r = remapbase / (64 * MiB); |
| 862 | remaplimit_r = remaplimit / (64 * MiB); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 863 | |
Kyösti Mälkki | 717b6e3 | 2018-05-17 14:16:03 +0300 | [diff] [blame] | 864 | /* Limit register is inclusive. */ |
| 865 | remaplimit_r -= 1; |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 866 | } |
Kyösti Mälkki | 717b6e3 | 2018-05-17 14:16:03 +0300 | [diff] [blame] | 867 | |
| 868 | /* Write the RAM configuration registers, |
| 869 | preserving the reserved bits. */ |
| 870 | reg = pci_read_config16(MCHDEV, TOLM) & 0x7ff; |
| 871 | reg |= (tolm / (128 * MiB)) << 11; |
| 872 | pci_write_config16(MCHDEV, TOLM, reg); |
| 873 | |
| 874 | reg = pci_read_config16(MCHDEV, REMAPBASE) & 0xfc00; |
| 875 | reg |= remapbase_r; |
| 876 | pci_write_config16(MCHDEV, REMAPBASE, reg); |
| 877 | |
| 878 | reg = pci_read_config16(MCHDEV, REMAPLIMIT) & 0xfc00; |
| 879 | reg |= remaplimit_r; |
| 880 | pci_write_config16(MCHDEV, REMAPLIMIT, reg); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 881 | } |
| 882 | |
| 883 | /** |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 884 | * Program the DRAM Timing register (DRT) of the E7501 (except for CAS# |
| 885 | * latency, which is assumed to have been programmed already), based on the |
| 886 | * parameters of the various installed DIMMs. |
| 887 | * |
| 888 | * @param ctrl PCI addresses of memory controller functions, and SMBus |
| 889 | * addresses of DIMM slots on the mainboard. |
| 890 | * @param dimm_mask Bitmask of populated DIMMs, see spd_get_supported_dimms(). |
| 891 | */ |
| 892 | static void configure_e7501_dram_timing(const struct mem_controller *ctrl, |
| 893 | uint8_t dimm_mask) |
| 894 | { |
| 895 | int i; |
| 896 | uint32_t dram_timing; |
| 897 | int value; |
| 898 | uint8_t slowest_row_precharge = 0; |
| 899 | uint8_t slowest_ras_cas_delay = 0; |
| 900 | uint8_t slowest_active_to_precharge_delay = 0; |
| 901 | uint32_t current_cas_latency = |
Kyösti Mälkki | 5bd271b | 2012-04-10 16:11:53 +0300 | [diff] [blame] | 902 | pci_read_config32(MCHDEV, DRT) & DRT_CAS_MASK; |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 903 | |
| 904 | // CAS# latency must be programmed beforehand |
| 905 | ASSERT((current_cas_latency == DRT_CAS_2_0) |
| 906 | || (current_cas_latency == DRT_CAS_2_5)); |
| 907 | |
| 908 | // Each timing parameter is determined by the slowest DIMM |
| 909 | |
| 910 | for (i = 0; i < MAX_DIMM_SOCKETS; i++) { |
| 911 | uint16_t dimm_socket_address; |
| 912 | |
| 913 | if (!(dimm_mask & (1 << i))) |
| 914 | continue; // This DIMM not present |
| 915 | |
| 916 | if (i < MAX_DIMM_SOCKETS_PER_CHANNEL) |
| 917 | dimm_socket_address = ctrl->channel0[i]; |
| 918 | else |
| 919 | dimm_socket_address = |
| 920 | ctrl->channel1[i - MAX_DIMM_SOCKETS_PER_CHANNEL]; |
| 921 | |
Kyösti Mälkki | 9e581ec | 2020-01-07 11:16:35 +0200 | [diff] [blame] | 922 | value = smbus_read_byte(dimm_socket_address, |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 923 | SPD_MIN_ROW_PRECHARGE_TIME); |
| 924 | if (value < 0) |
| 925 | goto hw_err; |
| 926 | if (value > slowest_row_precharge) |
| 927 | slowest_row_precharge = value; |
| 928 | |
Kyösti Mälkki | 9e581ec | 2020-01-07 11:16:35 +0200 | [diff] [blame] | 929 | value = smbus_read_byte(dimm_socket_address, |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 930 | SPD_MIN_RAS_TO_CAS_DELAY); |
| 931 | if (value < 0) |
| 932 | goto hw_err; |
| 933 | if (value > slowest_ras_cas_delay) |
| 934 | slowest_ras_cas_delay = value; |
| 935 | |
Kyösti Mälkki | 9e581ec | 2020-01-07 11:16:35 +0200 | [diff] [blame] | 936 | value = smbus_read_byte(dimm_socket_address, |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 937 | SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY); |
| 938 | if (value < 0) |
| 939 | goto hw_err; |
| 940 | if (value > slowest_active_to_precharge_delay) |
| 941 | slowest_active_to_precharge_delay = value; |
| 942 | } |
| 943 | |
| 944 | // NOTE for timing parameters: |
| 945 | // At 133 MHz, 1 clock == 7.52 ns |
| 946 | |
| 947 | /* Read the initial state */ |
Kyösti Mälkki | 5bd271b | 2012-04-10 16:11:53 +0300 | [diff] [blame] | 948 | dram_timing = pci_read_config32(MCHDEV, DRT); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 949 | |
| 950 | /* Trp */ |
| 951 | |
| 952 | // E7501 supports only 2 or 3 clocks for tRP |
| 953 | if (slowest_row_precharge > ((22 << 2) | (2 << 0))) |
| 954 | die("unsupported DIMM tRP"); // > 22.5 ns: 4 or more clocks |
| 955 | else if (slowest_row_precharge > (15 << 2)) |
| 956 | dram_timing &= ~(1 << 0); // > 15.0 ns: 3 clocks |
| 957 | else |
| 958 | dram_timing |= (1 << 0); // <= 15.0 ns: 2 clocks |
| 959 | |
| 960 | /* Trcd */ |
| 961 | |
| 962 | // E7501 supports only 2 or 3 clocks for tRCD |
| 963 | // Use the same value for both read & write |
| 964 | dram_timing &= ~((1 << 3) | (3 << 1)); |
| 965 | if (slowest_ras_cas_delay > ((22 << 2) | (2 << 0))) |
| 966 | die("unsupported DIMM tRCD"); // > 22.5 ns: 4 or more clocks |
| 967 | else if (slowest_ras_cas_delay > (15 << 2)) |
| 968 | dram_timing |= (2 << 1); // > 15.0 ns: 3 clocks |
| 969 | else |
| 970 | dram_timing |= ((1 << 3) | (3 << 1)); // <= 15.0 ns: 2 clocks |
| 971 | |
| 972 | /* Tras */ |
| 973 | |
| 974 | // E7501 supports only 5, 6, or 7 clocks for tRAS |
| 975 | // 5 clocks ~= 37.6 ns, 6 clocks ~= 45.1 ns, 7 clocks ~= 52.6 ns |
| 976 | dram_timing &= ~(3 << 9); |
| 977 | |
| 978 | if (slowest_active_to_precharge_delay > 52) |
| 979 | die("unsupported DIMM tRAS"); // > 52 ns: 8 or more clocks |
| 980 | else if (slowest_active_to_precharge_delay > 45) |
| 981 | dram_timing |= (0 << 9); // 46-52 ns: 7 clocks |
| 982 | else if (slowest_active_to_precharge_delay > 37) |
| 983 | dram_timing |= (1 << 9); // 38-45 ns: 6 clocks |
| 984 | else |
| 985 | dram_timing |= (2 << 9); // < 38 ns: 5 clocks |
| 986 | |
| 987 | /* Trd */ |
| 988 | |
Elyes HAOUAS | 0f92f63 | 2014-07-27 19:37:31 +0200 | [diff] [blame] | 989 | /* Set to a 7 clock read delay. This is for 133MHz |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 990 | * with a CAS latency of 2.5 if 2.0 a 6 clock |
| 991 | * delay is good */ |
| 992 | |
| 993 | dram_timing &= ~(7 << 24); // 7 clocks |
| 994 | if (current_cas_latency == DRT_CAS_2_0) |
| 995 | dram_timing |= (1 << 24); // 6 clocks |
| 996 | |
| 997 | /* |
| 998 | * Back to Back Read-Write Turn Around |
| 999 | */ |
| 1000 | /* Set to a 5 clock back to back read to write turn around. |
| 1001 | * 4 is a good delay if the CAS latency is 2.0 */ |
| 1002 | |
| 1003 | dram_timing &= ~(1 << 28); // 5 clocks |
| 1004 | if (current_cas_latency == DRT_CAS_2_0) |
| 1005 | dram_timing |= (1 << 28); // 4 clocks |
| 1006 | |
Kyösti Mälkki | 5bd271b | 2012-04-10 16:11:53 +0300 | [diff] [blame] | 1007 | pci_write_config32(MCHDEV, DRT, dram_timing); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1008 | |
| 1009 | return; |
| 1010 | |
| 1011 | hw_err: |
| 1012 | die(SPD_ERROR); |
| 1013 | } |
| 1014 | |
| 1015 | /** |
| 1016 | * Determine the shortest CAS# latency that the E7501 and all DIMMs have in |
| 1017 | * common, and program the E7501 to use it. |
| 1018 | * |
| 1019 | * @param ctrl PCI addresses of memory controller functions, and SMBus |
| 1020 | * addresses of DIMM slots on the mainboard. |
| 1021 | * @param dimm_mask Bitmask of populated DIMMs, spd_get_supported_dimms(). |
| 1022 | */ |
| 1023 | static void configure_e7501_cas_latency(const struct mem_controller *ctrl, |
| 1024 | uint8_t dimm_mask) |
| 1025 | { |
| 1026 | int i; |
| 1027 | int value; |
| 1028 | uint32_t dram_timing; |
Kyösti Mälkki | 5bd271b | 2012-04-10 16:11:53 +0300 | [diff] [blame] | 1029 | uint16_t dram_read_timing; |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1030 | uint32_t dword; |
| 1031 | |
| 1032 | // CAS# latency bitmasks in SPD_ACCEPTABLE_CAS_LATENCIES format |
| 1033 | // NOTE: E7501 supports only 2.0 and 2.5 |
| 1034 | uint32_t system_compatible_cas_latencies = |
| 1035 | SPD_CAS_LATENCY_2_0 | SPD_CAS_LATENCY_2_5; |
| 1036 | uint32_t current_cas_latency; |
| 1037 | uint32_t dimm_compatible_cas_latencies; |
| 1038 | |
| 1039 | for (i = 0; i < MAX_DIMM_SOCKETS; i++) { |
| 1040 | |
| 1041 | uint16_t dimm_socket_address; |
| 1042 | |
| 1043 | if (!(dimm_mask & (1 << i))) |
| 1044 | continue; // This DIMM not usable |
| 1045 | |
| 1046 | if (i < MAX_DIMM_SOCKETS_PER_CHANNEL) |
| 1047 | dimm_socket_address = ctrl->channel0[i]; |
| 1048 | else |
| 1049 | dimm_socket_address = |
| 1050 | ctrl->channel1[i - MAX_DIMM_SOCKETS_PER_CHANNEL]; |
| 1051 | |
Kyösti Mälkki | 9e581ec | 2020-01-07 11:16:35 +0200 | [diff] [blame] | 1052 | value = smbus_read_byte(dimm_socket_address, |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1053 | SPD_ACCEPTABLE_CAS_LATENCIES); |
| 1054 | if (value < 0) |
| 1055 | goto hw_err; |
| 1056 | |
| 1057 | dimm_compatible_cas_latencies = value & 0x7f; // Start with all supported by DIMM |
| 1058 | current_cas_latency = 1 << log2(dimm_compatible_cas_latencies); // Max supported by DIMM |
| 1059 | |
| 1060 | // Can we support the highest CAS# latency? |
| 1061 | |
Kyösti Mälkki | 9e581ec | 2020-01-07 11:16:35 +0200 | [diff] [blame] | 1062 | value = smbus_read_byte(dimm_socket_address, |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1063 | SPD_MIN_CYCLE_TIME_AT_CAS_MAX); |
| 1064 | if (value < 0) |
| 1065 | goto hw_err; |
| 1066 | |
| 1067 | // NOTE: At 133 MHz, 1 clock == 7.52 ns |
| 1068 | if (value > 0x75) { |
| 1069 | // Our bus is too fast for this CAS# latency |
| 1070 | // Remove it from the bitmask of those supported by the DIMM that are compatible |
| 1071 | dimm_compatible_cas_latencies &= ~current_cas_latency; |
| 1072 | } |
| 1073 | // Can we support the next-highest CAS# latency (max - 0.5)? |
| 1074 | |
| 1075 | current_cas_latency >>= 1; |
| 1076 | if (current_cas_latency != 0) { |
Kyösti Mälkki | 9e581ec | 2020-01-07 11:16:35 +0200 | [diff] [blame] | 1077 | value = smbus_read_byte(dimm_socket_address, |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1078 | SPD_SDRAM_CYCLE_TIME_2ND); |
| 1079 | if (value < 0) |
| 1080 | goto hw_err; |
| 1081 | if (value > 0x75) |
| 1082 | dimm_compatible_cas_latencies &= |
| 1083 | ~current_cas_latency; |
| 1084 | } |
| 1085 | // Can we support the next-highest CAS# latency (max - 1.0)? |
| 1086 | current_cas_latency >>= 1; |
| 1087 | if (current_cas_latency != 0) { |
Kyösti Mälkki | 9e581ec | 2020-01-07 11:16:35 +0200 | [diff] [blame] | 1088 | value = smbus_read_byte(dimm_socket_address, |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1089 | SPD_SDRAM_CYCLE_TIME_3RD); |
| 1090 | if (value < 0) |
| 1091 | goto hw_err; |
| 1092 | if (value > 0x75) |
| 1093 | dimm_compatible_cas_latencies &= |
| 1094 | ~current_cas_latency; |
| 1095 | } |
| 1096 | // Restrict the system to CAS# latencies compatible with this DIMM |
| 1097 | system_compatible_cas_latencies &= |
| 1098 | dimm_compatible_cas_latencies; |
| 1099 | |
| 1100 | /* go to the next DIMM */ |
| 1101 | } |
| 1102 | |
| 1103 | /* After all of the arduous calculation setup with the fastest |
| 1104 | * cas latency I can use. |
| 1105 | */ |
| 1106 | |
Kyösti Mälkki | 5bd271b | 2012-04-10 16:11:53 +0300 | [diff] [blame] | 1107 | dram_timing = pci_read_config32(MCHDEV, DRT); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1108 | dram_timing &= ~(DRT_CAS_MASK); |
| 1109 | |
Kyösti Mälkki | 5bd271b | 2012-04-10 16:11:53 +0300 | [diff] [blame] | 1110 | dram_read_timing = |
| 1111 | pci_read_config16(MCHDEV, DRDCTL); |
| 1112 | dram_read_timing &= 0xF000; |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1113 | |
| 1114 | if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_0) { |
| 1115 | dram_timing |= DRT_CAS_2_0; |
Kyösti Mälkki | 5bd271b | 2012-04-10 16:11:53 +0300 | [diff] [blame] | 1116 | dram_read_timing |= 0x0222; |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1117 | } else if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_5) { |
| 1118 | |
| 1119 | uint32_t dram_row_attributes = |
Kyösti Mälkki | 5bd271b | 2012-04-10 16:11:53 +0300 | [diff] [blame] | 1120 | pci_read_config32(MCHDEV, DRA); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1121 | |
| 1122 | dram_timing |= DRT_CAS_2_5; |
| 1123 | |
| 1124 | // At CAS# 2.5, DRAM Read Timing (if that's what it its) appears to need a slightly |
| 1125 | // different value if all DIMM slots are populated |
| 1126 | |
| 1127 | if ((dram_row_attributes & 0xff) |
| 1128 | && (dram_row_attributes & 0xff00) |
| 1129 | && (dram_row_attributes & 0xff0000) |
| 1130 | && (dram_row_attributes & 0xff000000)) { |
| 1131 | |
| 1132 | // All slots populated |
Kyösti Mälkki | 5bd271b | 2012-04-10 16:11:53 +0300 | [diff] [blame] | 1133 | dram_read_timing |= 0x0882; |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1134 | } else { |
| 1135 | // Some unpopulated slots |
Kyösti Mälkki | 5bd271b | 2012-04-10 16:11:53 +0300 | [diff] [blame] | 1136 | dram_read_timing |= 0x0662; |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1137 | } |
| 1138 | } else |
| 1139 | die("No CAS# latencies compatible with all DIMMs!!\n"); |
| 1140 | |
Kyösti Mälkki | 5bd271b | 2012-04-10 16:11:53 +0300 | [diff] [blame] | 1141 | pci_write_config32(MCHDEV, DRT, dram_timing); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1142 | |
| 1143 | /* set master DLL reset */ |
Kyösti Mälkki | 5bd271b | 2012-04-10 16:11:53 +0300 | [diff] [blame] | 1144 | dword = pci_read_config32(MCHDEV, 0x88); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1145 | dword |= (1 << 26); |
Kyösti Mälkki | 5bd271b | 2012-04-10 16:11:53 +0300 | [diff] [blame] | 1146 | pci_write_config32(MCHDEV, 0x88, dword); |
Kyösti Mälkki | 0a0d5e8 | 2011-10-31 14:18:33 +0200 | [diff] [blame] | 1147 | /* patch try register 88 is undocumented tnz */ |
| 1148 | dword &= 0x0ca17fff; |
| 1149 | dword |= 0xd14a5000; |
Kyösti Mälkki | 5bd271b | 2012-04-10 16:11:53 +0300 | [diff] [blame] | 1150 | pci_write_config32(MCHDEV, 0x88, dword); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1151 | |
Kyösti Mälkki | 5bd271b | 2012-04-10 16:11:53 +0300 | [diff] [blame] | 1152 | pci_write_config16(MCHDEV, DRDCTL, |
| 1153 | dram_read_timing); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1154 | |
Kyösti Mälkki | 0a0d5e8 | 2011-10-31 14:18:33 +0200 | [diff] [blame] | 1155 | /* clear master DLL reset */ |
Kyösti Mälkki | 5bd271b | 2012-04-10 16:11:53 +0300 | [diff] [blame] | 1156 | dword = pci_read_config32(MCHDEV, 0x88); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1157 | dword &= ~(1 << 26); |
Kyösti Mälkki | 5bd271b | 2012-04-10 16:11:53 +0300 | [diff] [blame] | 1158 | pci_write_config32(MCHDEV, 0x88, dword); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1159 | |
| 1160 | return; |
| 1161 | |
Kyösti Mälkki | 0a0d5e8 | 2011-10-31 14:18:33 +0200 | [diff] [blame] | 1162 | hw_err: |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1163 | die(SPD_ERROR); |
| 1164 | } |
| 1165 | |
| 1166 | /** |
| 1167 | * Configure the refresh interval so that we refresh no more often than |
| 1168 | * required by the "most needy" DIMM. Also disable ECC if any of the DIMMs |
| 1169 | * don't support it. |
| 1170 | * |
| 1171 | * @param ctrl PCI addresses of memory controller functions, and SMBus |
| 1172 | * addresses of DIMM slots on the mainboard. |
| 1173 | * @param dimm_mask Bitmask of populated DIMMs, spd_get_supported_dimms(). |
| 1174 | */ |
| 1175 | static void configure_e7501_dram_controller_mode(const struct |
| 1176 | mem_controller *ctrl, |
| 1177 | uint8_t dimm_mask) |
| 1178 | { |
| 1179 | int i; |
| 1180 | |
| 1181 | // Initial settings |
| 1182 | uint32_t controller_mode = |
Kyösti Mälkki | 5bd271b | 2012-04-10 16:11:53 +0300 | [diff] [blame] | 1183 | pci_read_config32(MCHDEV, DRC); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1184 | uint32_t system_refresh_mode = (controller_mode >> 8) & 7; |
| 1185 | |
| 1186 | // Code below assumes that most aggressive settings are in |
| 1187 | // force when we are called, either via E7501 reset defaults |
| 1188 | // or by sdram_set_registers(): |
| 1189 | // - ECC enabled |
| 1190 | // - No refresh |
| 1191 | |
| 1192 | ASSERT((controller_mode & (3 << 20)) == (2 << 20)); // ECC |
| 1193 | ASSERT(!(controller_mode & (7 << 8))); // Refresh |
| 1194 | |
| 1195 | /* Walk through _all_ dimms and find the least-common denominator for: |
| 1196 | * - ECC support |
| 1197 | * - refresh rates |
| 1198 | */ |
| 1199 | |
| 1200 | for (i = 0; i < MAX_DIMM_SOCKETS; i++) { |
| 1201 | |
| 1202 | uint32_t dimm_refresh_mode; |
| 1203 | int value; |
| 1204 | uint16_t dimm_socket_address; |
| 1205 | |
| 1206 | if (!(dimm_mask & (1 << i))) { |
| 1207 | continue; // This DIMM not usable |
| 1208 | } |
| 1209 | |
| 1210 | if (i < MAX_DIMM_SOCKETS_PER_CHANNEL) |
| 1211 | dimm_socket_address = ctrl->channel0[i]; |
| 1212 | else |
| 1213 | dimm_socket_address = |
| 1214 | ctrl->channel1[i - |
| 1215 | MAX_DIMM_SOCKETS_PER_CHANNEL]; |
| 1216 | |
| 1217 | // Disable ECC mode if any one of the DIMMs does not support ECC |
| 1218 | // SJM: Should we just die here? E7501 datasheet says non-ECC DIMMs aren't supported. |
| 1219 | |
Kyösti Mälkki | 9e581ec | 2020-01-07 11:16:35 +0200 | [diff] [blame] | 1220 | value = smbus_read_byte(dimm_socket_address, |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1221 | SPD_DIMM_CONFIG_TYPE); |
| 1222 | die_on_spd_error(value); |
| 1223 | if (value != ERROR_SCHEME_ECC) { |
| 1224 | controller_mode &= ~(3 << 20); |
| 1225 | } |
| 1226 | |
Kyösti Mälkki | 9e581ec | 2020-01-07 11:16:35 +0200 | [diff] [blame] | 1227 | value = smbus_read_byte(dimm_socket_address, SPD_REFRESH); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1228 | die_on_spd_error(value); |
| 1229 | value &= 0x7f; // Mask off self-refresh bit |
| 1230 | if (value > MAX_SPD_REFRESH_RATE) { |
Stefan Reinauer | 65b72ab | 2015-01-05 12:59:54 -0800 | [diff] [blame] | 1231 | printk(BIOS_ERR, "unsupported refresh rate\n"); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1232 | continue; |
| 1233 | } |
| 1234 | // Get the appropriate E7501 refresh mode for this DIMM |
| 1235 | dimm_refresh_mode = refresh_rate_map[value]; |
| 1236 | if (dimm_refresh_mode > 7) { |
Stefan Reinauer | 65b72ab | 2015-01-05 12:59:54 -0800 | [diff] [blame] | 1237 | printk(BIOS_ERR, "unsupported refresh rate\n"); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1238 | continue; |
| 1239 | } |
| 1240 | // If this DIMM requires more frequent refresh than others, |
| 1241 | // update the system setting |
| 1242 | if (refresh_frequency[dimm_refresh_mode] > |
| 1243 | refresh_frequency[system_refresh_mode]) |
| 1244 | system_refresh_mode = dimm_refresh_mode; |
| 1245 | |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1246 | /* go to the next DIMM */ |
| 1247 | } |
| 1248 | |
| 1249 | controller_mode |= (system_refresh_mode << 8); |
| 1250 | |
| 1251 | // Configure the E7501 |
Kyösti Mälkki | 5bd271b | 2012-04-10 16:11:53 +0300 | [diff] [blame] | 1252 | pci_write_config32(MCHDEV, DRC, controller_mode); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1253 | } |
| 1254 | |
| 1255 | /** |
| 1256 | * Configure the E7501's DRAM Row Attributes (DRA) registers based on DIMM |
| 1257 | * parameters read via SPD. This tells the controller the width of the SDRAM |
| 1258 | * chips on each DIMM side (x4 or x8) and the page size of each DIMM side |
| 1259 | * (4, 8, 16, or 32 KB). |
| 1260 | * |
| 1261 | * @param ctrl PCI addresses of memory controller functions, and SMBus |
| 1262 | * addresses of DIMM slots on the mainboard. |
| 1263 | * @param dimm_mask Bitmask of populated DIMMs, spd_get_supported_dimms(). |
| 1264 | */ |
| 1265 | static void configure_e7501_row_attributes(const struct mem_controller |
| 1266 | *ctrl, uint8_t dimm_mask) |
| 1267 | { |
| 1268 | int i; |
| 1269 | uint32_t row_attributes = 0; |
| 1270 | |
| 1271 | for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) { |
| 1272 | |
| 1273 | uint16_t dimm_socket_address = ctrl->channel0[i]; |
| 1274 | struct dimm_size page_size; |
| 1275 | struct dimm_size sdram_width; |
| 1276 | |
| 1277 | if (!(dimm_mask & (1 << i))) |
| 1278 | continue; // This DIMM not usable |
| 1279 | |
| 1280 | // Get the relevant parameters via SPD |
| 1281 | page_size = sdram_spd_get_page_size(dimm_socket_address); |
| 1282 | sdram_width = sdram_spd_get_width(dimm_socket_address); |
| 1283 | |
| 1284 | // Update the DRAM Row Attributes. |
| 1285 | // Page size is encoded as log2(page size in bits) - log2(8 Kb) |
| 1286 | // NOTE: 8 Kb = 2^13 |
| 1287 | row_attributes |= (page_size.side1 - 13) << (i << 3); // Side 1 of each DIMM is an EVEN row |
| 1288 | |
| 1289 | if (sdram_width.side2 > 0) |
| 1290 | row_attributes |= (page_size.side2 - 13) << ((i << 3) + 4); // Side 2 is ODD |
| 1291 | |
| 1292 | // Set x4 flags if appropriate |
| 1293 | if (sdram_width.side1 == 4) { |
| 1294 | row_attributes |= 0x08 << (i << 3); |
| 1295 | } |
| 1296 | |
| 1297 | if (sdram_width.side2 == 4) { |
| 1298 | row_attributes |= 0x08 << ((i << 3) + 4); |
| 1299 | } |
| 1300 | |
| 1301 | /* go to the next DIMM */ |
| 1302 | } |
| 1303 | |
| 1304 | /* Write the new row attributes register */ |
Kyösti Mälkki | 5bd271b | 2012-04-10 16:11:53 +0300 | [diff] [blame] | 1305 | pci_write_config32(MCHDEV, DRA, row_attributes); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1306 | } |
| 1307 | |
| 1308 | /* |
| 1309 | * Enable clock signals for populated DIMM sockets and disable them for |
| 1310 | * unpopulated sockets (to reduce EMI). |
| 1311 | * |
| 1312 | * @param dimm_mask Bitmask of populated DIMMs, see spd_get_supported_dimms(). |
| 1313 | */ |
| 1314 | static void enable_e7501_clocks(uint8_t dimm_mask) |
| 1315 | { |
| 1316 | int i; |
Kyösti Mälkki | 5bd271b | 2012-04-10 16:11:53 +0300 | [diff] [blame] | 1317 | uint8_t clock_disable = pci_read_config8(MCHDEV, CKDIS); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1318 | |
Kyösti Mälkki | 5bd271b | 2012-04-10 16:11:53 +0300 | [diff] [blame] | 1319 | pci_write_config8(MCHDEV, 0x8e, 0xb0); |
Kyösti Mälkki | 0a0d5e8 | 2011-10-31 14:18:33 +0200 | [diff] [blame] | 1320 | |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1321 | for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) { |
| 1322 | |
| 1323 | uint8_t socket_mask = 1 << i; |
| 1324 | |
| 1325 | if (dimm_mask & socket_mask) |
| 1326 | clock_disable &= ~socket_mask; // DIMM present, enable clock |
| 1327 | else |
| 1328 | clock_disable |= socket_mask; // DIMM absent, disable clock |
| 1329 | } |
| 1330 | |
Kyösti Mälkki | 5bd271b | 2012-04-10 16:11:53 +0300 | [diff] [blame] | 1331 | pci_write_config8(MCHDEV, CKDIS, clock_disable); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1332 | } |
| 1333 | |
Martin Roth | 128c104 | 2016-11-18 09:29:03 -0700 | [diff] [blame] | 1334 | /* DIMM-dependent configuration functions */ |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1335 | |
| 1336 | /** |
| 1337 | * DDR Receive FIFO RE-Sync (?) |
| 1338 | */ |
| 1339 | static void RAM_RESET_DDR_PTR(void) |
| 1340 | { |
| 1341 | uint8_t byte; |
Kyösti Mälkki | 5bd271b | 2012-04-10 16:11:53 +0300 | [diff] [blame] | 1342 | byte = pci_read_config8(MCHDEV, 0x88); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1343 | byte |= (1 << 4); |
Kyösti Mälkki | 5bd271b | 2012-04-10 16:11:53 +0300 | [diff] [blame] | 1344 | pci_write_config8(MCHDEV, 0x88, byte); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1345 | |
Kyösti Mälkki | 5bd271b | 2012-04-10 16:11:53 +0300 | [diff] [blame] | 1346 | byte = pci_read_config8(MCHDEV, 0x88); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1347 | byte &= ~(1 << 4); |
Kyösti Mälkki | 5bd271b | 2012-04-10 16:11:53 +0300 | [diff] [blame] | 1348 | pci_write_config8(MCHDEV, 0x88, byte); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1349 | } |
| 1350 | |
| 1351 | /** |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1352 | * Copy 64 bytes from one location to another. |
| 1353 | * |
| 1354 | * @param src_addr TODO |
| 1355 | * @param dst_addr TODO |
| 1356 | */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 1357 | static void write_8dwords(const uint32_t *src_addr, u8 *dst_addr) |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1358 | { |
| 1359 | int i; |
| 1360 | for (i = 0; i < 8; i++) { |
| 1361 | write32(dst_addr, *src_addr); |
| 1362 | src_addr++; |
| 1363 | dst_addr += sizeof(uint32_t); |
| 1364 | } |
| 1365 | } |
| 1366 | |
| 1367 | /** |
| 1368 | * Set the E7501's (undocumented) RCOMP registers. |
| 1369 | * |
| 1370 | * Per the 855PM datasheet and IXP2800 HW Initialization Reference Manual, |
| 1371 | * RCOMP registers appear to affect drive strength, pullup/pulldown offset, |
| 1372 | * and slew rate of various signal groups. |
| 1373 | * |
| 1374 | * Comments below are conjecture based on apparent similarity between the |
| 1375 | * E7501 and these two chips. |
| 1376 | */ |
Kyösti Mälkki | 77e4f7d | 2012-04-18 19:47:56 +0300 | [diff] [blame] | 1377 | static void rcomp_copy_registers(void) |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1378 | { |
| 1379 | uint32_t dword; |
Kyösti Mälkki | 77e4f7d | 2012-04-18 19:47:56 +0300 | [diff] [blame] | 1380 | uint8_t strength_control; |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1381 | |
| 1382 | RAM_DEBUG_MESSAGE("Setting RCOMP registers.\n"); |
| 1383 | |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1384 | /* Begin to write the RCOMP registers */ |
Kyösti Mälkki | 0a0d5e8 | 2011-10-31 14:18:33 +0200 | [diff] [blame] | 1385 | write8(RCOMP_MMIO + 0x2c, 0x0); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1386 | |
| 1387 | // Set CMD and DQ/DQS strength to 2x (?) |
Kyösti Mälkki | 5bd271b | 2012-04-10 16:11:53 +0300 | [diff] [blame] | 1388 | strength_control = read8(RCOMP_MMIO + DQCMDSTR) & 0x88; |
| 1389 | strength_control |= 0x40; |
| 1390 | write8(RCOMP_MMIO + DQCMDSTR, strength_control); |
| 1391 | write_8dwords(slew_2x, RCOMP_MMIO + 0x80); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1392 | write16(RCOMP_MMIO + 0x42, 0); |
| 1393 | |
Kyösti Mälkki | 0a0d5e8 | 2011-10-31 14:18:33 +0200 | [diff] [blame] | 1394 | // Set CMD and DQ/DQS strength to 2x (?) |
Kyösti Mälkki | 5bd271b | 2012-04-10 16:11:53 +0300 | [diff] [blame] | 1395 | strength_control = read8(RCOMP_MMIO + DQCMDSTR) & 0xF8; |
| 1396 | strength_control |= 0x04; |
| 1397 | write8(RCOMP_MMIO + DQCMDSTR, strength_control); |
| 1398 | write_8dwords(slew_2x, RCOMP_MMIO + 0x60); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1399 | write16(RCOMP_MMIO + 0x40, 0); |
| 1400 | |
| 1401 | // Set RCVEnOut# strength to 2x (?) |
Kyösti Mälkki | 5bd271b | 2012-04-10 16:11:53 +0300 | [diff] [blame] | 1402 | strength_control = read8(RCOMP_MMIO + RCVENSTR) & 0xF8; |
| 1403 | strength_control |= 0x04; |
| 1404 | write8(RCOMP_MMIO + RCVENSTR, strength_control); |
| 1405 | write_8dwords(slew_2x, RCOMP_MMIO + 0x1c0); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1406 | write16(RCOMP_MMIO + 0x50, 0); |
| 1407 | |
| 1408 | // Set CS# strength for x4 SDRAM to 2x (?) |
Kyösti Mälkki | 5bd271b | 2012-04-10 16:11:53 +0300 | [diff] [blame] | 1409 | strength_control = read8(RCOMP_MMIO + CSBSTR) & 0x88; |
| 1410 | strength_control |= 0x04; |
| 1411 | write8(RCOMP_MMIO + CSBSTR, strength_control); |
| 1412 | write_8dwords(slew_2x, RCOMP_MMIO + 0x140); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1413 | write16(RCOMP_MMIO + 0x48, 0); |
| 1414 | |
Kyösti Mälkki | 0a0d5e8 | 2011-10-31 14:18:33 +0200 | [diff] [blame] | 1415 | // Set CS# strength for x4 SDRAM to 2x (?) |
Kyösti Mälkki | 5bd271b | 2012-04-10 16:11:53 +0300 | [diff] [blame] | 1416 | strength_control = read8(RCOMP_MMIO + CSBSTR) & 0x8F; |
| 1417 | strength_control |= 0x40; |
| 1418 | write8(RCOMP_MMIO + CSBSTR, strength_control); |
| 1419 | write_8dwords(slew_2x, RCOMP_MMIO + 0x160); |
Kyösti Mälkki | 0a0d5e8 | 2011-10-31 14:18:33 +0200 | [diff] [blame] | 1420 | write16(RCOMP_MMIO + 0x4a, 0); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1421 | |
Kyösti Mälkki | 0a0d5e8 | 2011-10-31 14:18:33 +0200 | [diff] [blame] | 1422 | // Set CKE strength for x4 SDRAM to 2x (?) |
Kyösti Mälkki | 5bd271b | 2012-04-10 16:11:53 +0300 | [diff] [blame] | 1423 | strength_control = read8(RCOMP_MMIO + CKESTR) & 0x88; |
| 1424 | strength_control |= 0x04; |
| 1425 | write8(RCOMP_MMIO + CKESTR, strength_control); |
| 1426 | write_8dwords(slew_2x, RCOMP_MMIO + 0xa0); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1427 | write16(RCOMP_MMIO + 0x44, 0); |
| 1428 | |
Kyösti Mälkki | 0a0d5e8 | 2011-10-31 14:18:33 +0200 | [diff] [blame] | 1429 | // Set CKE strength for x4 SDRAM to 2x (?) |
Kyösti Mälkki | 5bd271b | 2012-04-10 16:11:53 +0300 | [diff] [blame] | 1430 | strength_control = read8(RCOMP_MMIO + CKESTR) & 0x8F; |
| 1431 | strength_control |= 0x40; |
| 1432 | write8(RCOMP_MMIO + CKESTR, strength_control); |
| 1433 | write_8dwords(slew_2x, RCOMP_MMIO + 0xc0); |
Kyösti Mälkki | 0a0d5e8 | 2011-10-31 14:18:33 +0200 | [diff] [blame] | 1434 | write16(RCOMP_MMIO + 0x46, 0); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1435 | |
Kyösti Mälkki | 0a0d5e8 | 2011-10-31 14:18:33 +0200 | [diff] [blame] | 1436 | // Set CK strength for x4 SDRAM to 1x (?) |
Kyösti Mälkki | 5bd271b | 2012-04-10 16:11:53 +0300 | [diff] [blame] | 1437 | strength_control = read8(RCOMP_MMIO + CKSTR) & 0x88; |
| 1438 | strength_control |= 0x01; |
| 1439 | write8(RCOMP_MMIO + CKSTR, strength_control); |
| 1440 | write_8dwords(pull_updown_offset_table, RCOMP_MMIO + 0x180); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1441 | write16(RCOMP_MMIO + 0x4c, 0); |
| 1442 | |
Kyösti Mälkki | 0a0d5e8 | 2011-10-31 14:18:33 +0200 | [diff] [blame] | 1443 | // Set CK strength for x4 SDRAM to 1x (?) |
Kyösti Mälkki | 5bd271b | 2012-04-10 16:11:53 +0300 | [diff] [blame] | 1444 | strength_control = read8(RCOMP_MMIO + CKSTR) & 0x8F; |
| 1445 | strength_control |= 0x10; |
| 1446 | write8(RCOMP_MMIO + CKSTR, strength_control); |
| 1447 | write_8dwords(pull_updown_offset_table, RCOMP_MMIO + 0x1a0); |
Kyösti Mälkki | 0a0d5e8 | 2011-10-31 14:18:33 +0200 | [diff] [blame] | 1448 | write16(RCOMP_MMIO + 0x4e, 0); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1449 | |
Kyösti Mälkki | 0a0d5e8 | 2011-10-31 14:18:33 +0200 | [diff] [blame] | 1450 | dword = read32(RCOMP_MMIO + 0x400); |
| 1451 | dword &= 0x7f7fffff; |
| 1452 | write32(RCOMP_MMIO + 0x400, dword); |
| 1453 | |
| 1454 | dword = read32(RCOMP_MMIO + 0x408); |
| 1455 | dword &= 0x7f7fffff; |
| 1456 | write32(RCOMP_MMIO + 0x408, dword); |
Kyösti Mälkki | 77e4f7d | 2012-04-18 19:47:56 +0300 | [diff] [blame] | 1457 | } |
Kyösti Mälkki | 0a0d5e8 | 2011-10-31 14:18:33 +0200 | [diff] [blame] | 1458 | |
Kyösti Mälkki | 77e4f7d | 2012-04-18 19:47:56 +0300 | [diff] [blame] | 1459 | static void ram_set_rcomp_regs(void) |
| 1460 | { |
| 1461 | /* Set the RCOMP MMIO base address */ |
| 1462 | mchtest_control(RCOMP_BAR_ENABLE); |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 1463 | pci_write_config32(MCHDEV, SMRBASE, (uintptr_t)RCOMP_MMIO); |
Kyösti Mälkki | 77e4f7d | 2012-04-18 19:47:56 +0300 | [diff] [blame] | 1464 | |
| 1465 | /* Block RCOMP updates while we configure the registers */ |
| 1466 | rcomp_smr_control(RCOMP_HOLD); |
| 1467 | rcomp_copy_registers(); |
Kyösti Mälkki | 26c7b86 | 2012-04-12 22:46:23 +0300 | [diff] [blame] | 1468 | d060_control(D060_CMD_0); |
| 1469 | mchtest_control(MCHTST_CMD_0); |
Kyösti Mälkki | 0a0d5e8 | 2011-10-31 14:18:33 +0200 | [diff] [blame] | 1470 | |
Kyösti Mälkki | 77e4f7d | 2012-04-18 19:47:56 +0300 | [diff] [blame] | 1471 | uint8_t revision = pci_read_config8(MCHDEV, 0x08); |
Kyösti Mälkki | 0a0d5e8 | 2011-10-31 14:18:33 +0200 | [diff] [blame] | 1472 | if (revision >= 3) { |
Kyösti Mälkki | 26c7b86 | 2012-04-12 22:46:23 +0300 | [diff] [blame] | 1473 | rcomp_smr_control(RCOMP_SMR_00); |
| 1474 | rcomp_smr_control(RCOMP_SMR_01); |
Kyösti Mälkki | 0a0d5e8 | 2011-10-31 14:18:33 +0200 | [diff] [blame] | 1475 | } |
Kyösti Mälkki | 26c7b86 | 2012-04-12 22:46:23 +0300 | [diff] [blame] | 1476 | rcomp_smr_control(RCOMP_RELEASE); |
| 1477 | |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1478 | /* Wait 40 usec */ |
| 1479 | SLOW_DOWN_IO; |
| 1480 | |
Kyösti Mälkki | 26c7b86 | 2012-04-12 22:46:23 +0300 | [diff] [blame] | 1481 | /* Clear the RCOMP MMIO base address */ |
Kyösti Mälkki | 5bd271b | 2012-04-10 16:11:53 +0300 | [diff] [blame] | 1482 | pci_write_config32(MCHDEV, SMRBASE, 0); |
Kyösti Mälkki | 26c7b86 | 2012-04-12 22:46:23 +0300 | [diff] [blame] | 1483 | mchtest_control(RCOMP_BAR_DISABLE); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1484 | } |
| 1485 | |
| 1486 | /*----------------------------------------------------------------------------- |
| 1487 | Public interface: |
| 1488 | -----------------------------------------------------------------------------*/ |
| 1489 | |
| 1490 | /** |
| 1491 | * Go through the JEDEC initialization sequence for all DIMMs, then enable |
| 1492 | * refresh and initialize ECC and memory to zero. Upon exit, SDRAM is up |
| 1493 | * and running. |
| 1494 | * |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1495 | * @param ctrl PCI addresses of memory controller functions, and SMBus |
| 1496 | * addresses of DIMM slots on the mainboard. |
| 1497 | */ |
Kyösti Mälkki | 5c1ff92 | 2012-04-10 19:55:19 +0300 | [diff] [blame] | 1498 | static void sdram_enable(const struct mem_controller *ctrl) |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1499 | { |
Kyösti Mälkki | 5bd271b | 2012-04-10 16:11:53 +0300 | [diff] [blame] | 1500 | uint8_t dimm_mask = pci_read_config16(MCHDEV, SKPD); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1501 | uint32_t dram_controller_mode; |
| 1502 | |
| 1503 | if (dimm_mask == 0) |
| 1504 | return; |
| 1505 | |
| 1506 | /* 1 & 2 Power up and start clocks */ |
| 1507 | RAM_DEBUG_MESSAGE("Ram Enable 1\n"); |
| 1508 | RAM_DEBUG_MESSAGE("Ram Enable 2\n"); |
| 1509 | |
| 1510 | /* A 200us delay is needed */ |
| 1511 | DO_DELAY; EXTRA_DELAY; |
| 1512 | |
| 1513 | /* 3. Apply NOP */ |
| 1514 | RAM_DEBUG_MESSAGE("Ram Enable 3\n"); |
| 1515 | do_ram_command(RAM_COMMAND_NOP, 0); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1516 | |
| 1517 | /* 4 Precharge all */ |
| 1518 | RAM_DEBUG_MESSAGE("Ram Enable 4\n"); |
| 1519 | do_ram_command(RAM_COMMAND_PRECHARGE, 0); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1520 | /* wait until the all banks idle state... */ |
| 1521 | |
| 1522 | /* 5. Issue EMRS to enable DLL */ |
| 1523 | RAM_DEBUG_MESSAGE("Ram Enable 5\n"); |
| 1524 | do_ram_command(RAM_COMMAND_EMRS, |
| 1525 | SDRAM_EXTMODE_DLL_ENABLE | |
| 1526 | SDRAM_EXTMODE_DRIVE_NORMAL); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1527 | |
| 1528 | /* 6. Reset DLL */ |
| 1529 | RAM_DEBUG_MESSAGE("Ram Enable 6\n"); |
| 1530 | set_ram_mode(E7501_SDRAM_MODE | SDRAM_MODE_DLL_RESET); |
| 1531 | EXTRA_DELAY; |
| 1532 | /* Ensure a 200us delay between the DLL reset in step 6 and the final |
| 1533 | * mode register set in step 9. |
| 1534 | * Infineon needs this before any other command is sent to the ram. |
| 1535 | */ |
| 1536 | DO_DELAY; EXTRA_DELAY; |
| 1537 | |
| 1538 | /* 7 Precharge all */ |
| 1539 | RAM_DEBUG_MESSAGE("Ram Enable 7\n"); |
| 1540 | do_ram_command(RAM_COMMAND_PRECHARGE, 0); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1541 | |
| 1542 | /* 8 Now we need 2 AUTO REFRESH / CBR cycles to be performed */ |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1543 | /* And for good luck 6 more CBRs */ |
Kyösti Mälkki | 5c1ff92 | 2012-04-10 19:55:19 +0300 | [diff] [blame] | 1544 | RAM_DEBUG_MESSAGE("Ram Enable 8\n"); |
| 1545 | int i; |
Elyes HAOUAS | 9309552 | 2016-09-17 21:05:10 +0200 | [diff] [blame] | 1546 | for (i = 0; i < 8; i++) |
Kyösti Mälkki | 5c1ff92 | 2012-04-10 19:55:19 +0300 | [diff] [blame] | 1547 | do_ram_command(RAM_COMMAND_CBR, 0); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1548 | |
| 1549 | /* 9 mode register set */ |
| 1550 | RAM_DEBUG_MESSAGE("Ram Enable 9\n"); |
| 1551 | set_ram_mode(E7501_SDRAM_MODE | SDRAM_MODE_NORMAL); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1552 | |
| 1553 | /* 10 DDR Receive FIFO RE-Sync */ |
| 1554 | RAM_DEBUG_MESSAGE("Ram Enable 10\n"); |
| 1555 | RAM_RESET_DDR_PTR(); |
| 1556 | EXTRA_DELAY; |
| 1557 | |
| 1558 | /* 11 normal operation */ |
| 1559 | RAM_DEBUG_MESSAGE("Ram Enable 11\n"); |
| 1560 | do_ram_command(RAM_COMMAND_NORMAL, 0); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1561 | |
| 1562 | // Reconfigure the row boundaries and Top of Low Memory |
| 1563 | // to match the true size of the DIMMs |
| 1564 | configure_e7501_ram_addresses(ctrl, dimm_mask); |
| 1565 | |
| 1566 | /* Finally enable refresh */ |
Kyösti Mälkki | 5bd271b | 2012-04-10 16:11:53 +0300 | [diff] [blame] | 1567 | dram_controller_mode = pci_read_config32(MCHDEV, DRC); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1568 | dram_controller_mode |= (1 << 29); |
Kyösti Mälkki | 5bd271b | 2012-04-10 16:11:53 +0300 | [diff] [blame] | 1569 | pci_write_config32(MCHDEV, DRC, dram_controller_mode); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1570 | EXTRA_DELAY; |
Kyösti Mälkki | 97c064f | 2012-04-18 20:33:35 +0300 | [diff] [blame] | 1571 | } |
Kyösti Mälkki | 5c1ff92 | 2012-04-10 19:55:19 +0300 | [diff] [blame] | 1572 | |
Kyösti Mälkki | 97c064f | 2012-04-18 20:33:35 +0300 | [diff] [blame] | 1573 | /** |
| 1574 | * @param ctrl PCI addresses of memory controller functions, and SMBus |
| 1575 | * addresses of DIMM slots on the mainboard. |
| 1576 | */ |
| 1577 | static void sdram_post_ecc(const struct mem_controller *ctrl) |
| 1578 | { |
| 1579 | /* Fast CS# Enable. */ |
| 1580 | uint32_t dram_controller_mode = pci_read_config32(MCHDEV, DRC); |
| 1581 | dram_controller_mode = pci_read_config32(MCHDEV, DRC); |
| 1582 | dram_controller_mode |= (1 << 17); |
Kyösti Mälkki | 5bd271b | 2012-04-10 16:11:53 +0300 | [diff] [blame] | 1583 | pci_write_config32(MCHDEV, DRC, dram_controller_mode); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1584 | } |
| 1585 | |
| 1586 | /** |
| 1587 | * Configure SDRAM controller parameters that depend on characteristics of the |
| 1588 | * DIMMs installed in the system. These characteristics are read from the |
| 1589 | * DIMMs via the standard Serial Presence Detect (SPD) interface. |
| 1590 | * |
| 1591 | * @param ctrl PCI addresses of memory controller functions, and SMBus |
| 1592 | * addresses of DIMM slots on the mainboard. |
| 1593 | */ |
| 1594 | static void sdram_set_spd_registers(const struct mem_controller *ctrl) |
| 1595 | { |
| 1596 | uint8_t dimm_mask; |
| 1597 | |
| 1598 | RAM_DEBUG_MESSAGE("Reading SPD data...\n"); |
| 1599 | |
| 1600 | dimm_mask = spd_get_supported_dimms(ctrl); |
| 1601 | |
| 1602 | if (dimm_mask == 0) { |
Stefan Reinauer | 65b72ab | 2015-01-05 12:59:54 -0800 | [diff] [blame] | 1603 | printk(BIOS_DEBUG, "No usable memory for this controller\n"); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1604 | } else { |
| 1605 | enable_e7501_clocks(dimm_mask); |
| 1606 | |
| 1607 | RAM_DEBUG_MESSAGE("setting based on SPD data...\n"); |
| 1608 | |
| 1609 | configure_e7501_row_attributes(ctrl, dimm_mask); |
| 1610 | configure_e7501_dram_controller_mode(ctrl, dimm_mask); |
| 1611 | configure_e7501_cas_latency(ctrl, dimm_mask); |
| 1612 | RAM_RESET_DDR_PTR(); |
| 1613 | |
| 1614 | configure_e7501_dram_timing(ctrl, dimm_mask); |
| 1615 | DO_DELAY; |
| 1616 | RAM_DEBUG_MESSAGE("done\n"); |
| 1617 | } |
| 1618 | |
| 1619 | /* NOTE: configure_e7501_ram_addresses() is NOT called here. |
| 1620 | * We want to keep the default 64 MB/row mapping until sdram_enable() is called, |
| 1621 | * even though the default mapping is almost certainly incorrect. |
| 1622 | * The default mapping makes it easy to initialize all of the DIMMs |
| 1623 | * even if the total system memory is > 4 GB. |
| 1624 | * |
| 1625 | * Save the dimm_mask for when sdram_enable is called, so it can call |
| 1626 | * configure_e7501_ram_addresses() without having to regenerate the bitmask |
| 1627 | * of usable DIMMs. |
| 1628 | */ |
Kyösti Mälkki | 5bd271b | 2012-04-10 16:11:53 +0300 | [diff] [blame] | 1629 | pci_write_config16(MCHDEV, SKPD, dimm_mask); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1630 | } |
| 1631 | |
| 1632 | /** |
| 1633 | * Do basic RAM setup that does NOT depend on serial presence detect |
| 1634 | * information (i.e. independent of DIMM specifics). |
| 1635 | * |
| 1636 | * @param ctrl PCI addresses of memory controller functions, and SMBus |
| 1637 | * addresses of DIMM slots on the mainboard. |
| 1638 | */ |
| 1639 | static void sdram_set_registers(const struct mem_controller *ctrl) |
| 1640 | { |
Kyösti Mälkki | 77e4f7d | 2012-04-18 19:47:56 +0300 | [diff] [blame] | 1641 | uint32_t dword; |
| 1642 | uint16_t word; |
| 1643 | uint8_t byte; |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1644 | |
| 1645 | ram_set_rcomp_regs(); |
Kyösti Mälkki | 77e4f7d | 2012-04-18 19:47:56 +0300 | [diff] [blame] | 1646 | |
| 1647 | /* Enable 0:0.1, 0:2.1 */ |
| 1648 | word = pci_read_config16(MCHDEV, DVNP); |
| 1649 | word &= ~0x05; |
| 1650 | pci_write_config16(MCHDEV, DVNP, word); |
| 1651 | |
| 1652 | /* Disable high-memory remap (power-on defaults, really) */ |
| 1653 | pci_write_config16(MCHDEV, REMAPBASE, 0x03ff); |
| 1654 | pci_write_config16(MCHDEV, REMAPLIMIT, 0x0); |
| 1655 | |
| 1656 | /* Disable legacy MMIO (0xC0000-0xEFFFF is DRAM) */ |
| 1657 | int i; |
| 1658 | pci_write_config8(MCHDEV, PAM_0, 0x30); |
Elyes HAOUAS | 9309552 | 2016-09-17 21:05:10 +0200 | [diff] [blame] | 1659 | for (i = 1; i <= 6; i++) |
Kyösti Mälkki | 77e4f7d | 2012-04-18 19:47:56 +0300 | [diff] [blame] | 1660 | pci_write_config8(MCHDEV, PAM_0 + i, 0x33); |
| 1661 | |
| 1662 | /* Conservatively say each row has 64MB of ram, we will fix this up later |
| 1663 | * Initial TOLM 8 rows 64MB each (1<<3 * 1<<26) >> 16 = 1<<13 |
| 1664 | * |
| 1665 | * FIXME: Hard-coded limit to first four rows to prevent overlap! |
| 1666 | */ |
| 1667 | pci_write_config32(MCHDEV, DRB_ROW_0, 0x04030201); |
| 1668 | pci_write_config32(MCHDEV, DRB_ROW_4, 0x04040404); |
| 1669 | //pci_write_config32(MCHDEV, DRB_ROW_4, 0x08070605); |
| 1670 | pci_write_config16(MCHDEV, TOLM, (1<<13)); |
| 1671 | |
| 1672 | /* DIMM clocks off */ |
| 1673 | pci_write_config8(MCHDEV, CKDIS, 0xff); |
| 1674 | |
| 1675 | /* reset row attributes */ |
| 1676 | pci_write_config32(MCHDEV, DRA, 0x0); |
| 1677 | |
| 1678 | // The only things we need to set here are DRAM idle timer, Back-to-Back Read Turnaround, and |
| 1679 | // Back-to-Back Write-Read Turnaround. All others are configured based on SPD. |
| 1680 | dword = pci_read_config32(MCHDEV, DRT); |
| 1681 | dword &= 0xC7F8FFFF; |
| 1682 | dword |= (0x28<<24)|(0x03<<16); |
| 1683 | pci_write_config32(MCHDEV, DRT, dword); |
| 1684 | |
| 1685 | dword = pci_read_config32(MCHDEV, DRC); |
| 1686 | dword &= 0xffcef8f7; |
| 1687 | dword |= 0x00210008; |
| 1688 | pci_write_config32(MCHDEV, DRC, dword); |
| 1689 | |
| 1690 | /* Undocumented */ |
| 1691 | pci_write_config8(MCHDEV, 0x88, 0x80); |
| 1692 | |
| 1693 | /* Undocumented. Set much later in vendor BIOS. */ |
| 1694 | byte = pci_read_config8(MCHDEV, 0xd9); |
| 1695 | byte &= ~0x60; |
| 1696 | pci_write_config8(MCHDEV, 0xd9, byte); |
| 1697 | |
Kyösti Mälkki | 26c7b86 | 2012-04-12 22:46:23 +0300 | [diff] [blame] | 1698 | uint8_t revision = pci_read_config8(MCHDEV, 0x08); |
| 1699 | if (revision >= 3) |
| 1700 | d060_control(D060_CMD_1); |
Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame] | 1701 | } |
Kyösti Mälkki | 0a0d5e8 | 2011-10-31 14:18:33 +0200 | [diff] [blame] | 1702 | |
Kyösti Mälkki | d1141ab | 2020-01-07 11:16:35 +0200 | [diff] [blame] | 1703 | static int e7505_mch_is_ready(void) |
Kyösti Mälkki | 5c1ff92 | 2012-04-10 19:55:19 +0300 | [diff] [blame] | 1704 | { |
| 1705 | uint32_t dword = pci_read_config32(MCHDEV, DRC); |
| 1706 | return !!(dword & DRC_DONE); |
| 1707 | } |
Kyösti Mälkki | d1141ab | 2020-01-07 11:16:35 +0200 | [diff] [blame] | 1708 | |
| 1709 | void sdram_initialize(void) |
| 1710 | { |
| 1711 | static const struct mem_controller memctrl[] = { |
| 1712 | { |
| 1713 | .d0 = PCI_DEV(0, 0, 0), |
| 1714 | .d0f1 = PCI_DEV(0, 0, 1), |
| 1715 | .channel0 = { 0x50, 0x52, 0, 0 }, |
| 1716 | .channel1 = { 0x51, 0x53, 0, 0 }, |
| 1717 | }, |
| 1718 | }; |
| 1719 | |
| 1720 | /* If this is a warm boot, some initialisation can be skipped */ |
| 1721 | if (!e7505_mch_is_ready()) { |
| 1722 | |
| 1723 | /* The real MCH initialisation. */ |
| 1724 | timestamp_add_now(TS_BEFORE_INITRAM); |
| 1725 | |
| 1726 | sdram_set_registers(memctrl); |
| 1727 | sdram_set_spd_registers(memctrl); |
| 1728 | sdram_enable(memctrl); |
| 1729 | |
| 1730 | /* Hook for post ECC scrub settings and debug. */ |
| 1731 | sdram_post_ecc(memctrl); |
| 1732 | |
| 1733 | timestamp_add_now(TS_AFTER_INITRAM); |
| 1734 | } |
| 1735 | |
| 1736 | printk(BIOS_DEBUG, "SDRAM is up.\n"); |
| 1737 | } |