Stefan Reinauer | b15975b | 2011-10-21 12:57:59 -0700 | [diff] [blame^] | 1 | /* This was originally for the e7500, modified for e7501 |
| 2 | * The primary differences are that 7501 apparently can |
| 3 | * support single channel RAM (i haven't tested), |
| 4 | * CAS1.5 is no longer supported, The ECC scrubber |
| 5 | * now supports a mode to zero RAM and init ECC in one step |
| 6 | * and the undocumented registers at 0x80 require new |
| 7 | * (undocumented) values determined by guesswork and |
| 8 | * comparison w/ OEM BIOS values. |
| 9 | * Steven James 02/06/2003 |
| 10 | */ |
| 11 | |
| 12 | /* converted to C 6/2004 yhlu */ |
| 13 | |
| 14 | #include <assert.h> |
| 15 | #include <spd.h> |
| 16 | #include <sdram_mode.h> |
| 17 | #include <stdlib.h> |
| 18 | #include "e7501.h" |
| 19 | |
| 20 | /*----------------------------------------------------------------------------- |
| 21 | Definitions: |
| 22 | -----------------------------------------------------------------------------*/ |
| 23 | |
| 24 | // Uncomment this to enable run-time checking of DIMM parameters |
| 25 | // for dual-channel operation |
| 26 | // Unfortunately the code seems to chew up several K of space. |
| 27 | //#define VALIDATE_DIMM_COMPATIBILITY |
| 28 | |
| 29 | #if CONFIG_DEBUG_RAM_SETUP |
| 30 | #define RAM_DEBUG_MESSAGE(x) print_debug(x) |
| 31 | #define RAM_DEBUG_HEX32(x) print_debug_hex32(x) |
| 32 | #define RAM_DEBUG_HEX8(x) print_debug_hex8(x) |
| 33 | #define DUMPNORTH() dump_pci_device(PCI_DEV(0, 0, 0)) |
| 34 | #else |
| 35 | #define RAM_DEBUG_MESSAGE(x) |
| 36 | #define RAM_DEBUG_HEX32(x) |
| 37 | #define RAM_DEBUG_HEX8(x) |
| 38 | #define DUMPNORTH() |
| 39 | #endif |
| 40 | |
| 41 | #define E7501_SDRAM_MODE (SDRAM_BURST_INTERLEAVED | SDRAM_BURST_4) |
| 42 | #define SPD_ERROR "Error reading SPD info\n" |
| 43 | |
| 44 | // NOTE: This used to be 0x100000. |
| 45 | // That doesn't work on systems where A20M# is asserted, because |
| 46 | // attempts to access 0x1000NN end up accessing 0x0000NN. |
| 47 | #define RCOMP_MMIO 0x200000 |
| 48 | |
| 49 | struct dimm_size { |
| 50 | unsigned long side1; |
| 51 | unsigned long side2; |
| 52 | }; |
| 53 | |
| 54 | static const uint32_t refresh_frequency[] = { |
| 55 | /* Relative frequency (array value) of each E7501 Refresh Mode Select |
| 56 | * (RMS) value (array index) |
| 57 | * 0 == least frequent refresh (longest interval between refreshes) |
| 58 | * [0] disabled -> 0 |
| 59 | * [1] 15.6 usec -> 2 |
| 60 | * [2] 7.8 usec -> 3 |
| 61 | * [3] 64 usec -> 1 |
| 62 | * [4] reserved -> 0 |
| 63 | * [5] reserved -> 0 |
| 64 | * [6] reserved -> 0 |
| 65 | * [7] 64 clocks -> 4 |
| 66 | */ |
| 67 | 0, 2, 3, 1, 0, 0, 0, 4 |
| 68 | }; |
| 69 | |
| 70 | static const uint32_t refresh_rate_map[] = { |
| 71 | /* Map the JEDEC spd refresh rates (array index) to E7501 Refresh Mode |
| 72 | * Select values (array value) |
| 73 | * These are all the rates defined by JESD21-C Appendix D, Rev. 1.0 |
| 74 | * The E7501 supports only 15.6 us (1), 7.8 us (2), 64 us (3), and |
| 75 | * 64 clock (481 ns) (7) refresh. |
| 76 | * [0] == 15.625 us -> 15.6 us |
| 77 | * [1] == 3.9 us -> 481 ns |
| 78 | * [2] == 7.8 us -> 7.8 us |
| 79 | * [3] == 31.3 us -> 15.6 us |
| 80 | * [4] == 62.5 us -> 15.6 us |
| 81 | * [5] == 125 us -> 64 us |
| 82 | */ |
| 83 | 1, 7, 2, 1, 1, 3 |
| 84 | }; |
| 85 | |
| 86 | #define MAX_SPD_REFRESH_RATE ((sizeof(refresh_rate_map) / sizeof(uint32_t)) - 1) |
| 87 | |
| 88 | // SPD parameters that must match for dual-channel operation |
| 89 | static const uint8_t dual_channel_parameters[] = { |
| 90 | SPD_MEMORY_TYPE, |
| 91 | SPD_MODULE_VOLTAGE, |
| 92 | SPD_NUM_COLUMNS, |
| 93 | SPD_NUM_ROWS, |
| 94 | SPD_NUM_DIMM_BANKS, |
| 95 | SPD_PRIMARY_SDRAM_WIDTH, |
| 96 | SPD_NUM_BANKS_PER_SDRAM |
| 97 | }; |
| 98 | |
| 99 | /* |
| 100 | * Table: constant_register_values |
| 101 | */ |
| 102 | static const long constant_register_values[] = { |
| 103 | /* SVID - Subsystem Vendor Identification Register |
| 104 | * 0x2c - 0x2d |
| 105 | * [15:00] Subsytem Vendor ID (Indicates system board vendor) |
| 106 | */ |
| 107 | /* SID - Subsystem Identification Register |
| 108 | * 0x2e - 0x2f |
| 109 | * [15:00] Subsystem ID |
| 110 | */ |
| 111 | // Not everyone wants to be Super Micro Computer, Inc. |
| 112 | // The mainboard should set this if desired. |
| 113 | // 0x2c, 0, (0x15d9 << 0) | (0x3580 << 16), |
| 114 | |
| 115 | /* Undocumented |
| 116 | * (DRAM Read Timing Control, if similar to 855PM?) |
| 117 | * 0x80 - 0x81 |
| 118 | * This register has something to do with CAS latencies, |
| 119 | * possibily this is the real chipset control. |
| 120 | * At 0x00 CAS latency 1.5 works. |
| 121 | * At 0x06 CAS latency 2.5 works. |
| 122 | * At 0x01 CAS latency 2.0 works. |
| 123 | */ |
| 124 | /* This is still undocumented in e7501, but with different values |
| 125 | * CAS 2.0 values taken from Intel BIOS settings, others are a guess |
| 126 | * and may be terribly wrong. Old values preserved as comments until I |
| 127 | * figure this out for sure. |
| 128 | * e7501 docs claim that CAS1.5 is unsupported, so it may or may not |
| 129 | * work at all. |
| 130 | * Steven James 02/06/2003 |
| 131 | */ |
| 132 | /* NOTE: values now configured in configure_e7501_cas_latency() based |
| 133 | * on SPD info and total number of DIMMs (per Intel) |
| 134 | */ |
| 135 | |
| 136 | /* FDHC - Fixed DRAM Hole Control |
| 137 | * 0x58 |
| 138 | * [7:7] Hole_Enable |
| 139 | * 0 == No memory Hole |
| 140 | * 1 == Memory Hole from 15MB to 16MB |
| 141 | * [6:0] Reserved |
| 142 | * |
| 143 | * PAM - Programmable Attribute Map |
| 144 | * 0x59 [1:0] Reserved |
| 145 | * 0x59 [5:4] 0xF0000 - 0xFFFFF |
| 146 | * 0x5A [1:0] 0xC0000 - 0xC3FFF |
| 147 | * 0x5A [5:4] 0xC4000 - 0xC7FFF |
| 148 | * 0x5B [1:0] 0xC8000 - 0xCBFFF |
| 149 | * 0x5B [5:4] 0xCC000 - 0xCFFFF |
| 150 | * 0x5C [1:0] 0xD0000 - 0xD3FFF |
| 151 | * 0x5C [5:4] 0xD4000 - 0xD7FFF |
| 152 | * 0x5D [1:0] 0xD8000 - 0xDBFFF |
| 153 | * 0x5D [5:4] 0xDC000 - 0xDFFFF |
| 154 | * 0x5E [1:0] 0xE0000 - 0xE3FFF |
| 155 | * 0x5E [5:4] 0xE4000 - 0xE7FFF |
| 156 | * 0x5F [1:0] 0xE8000 - 0xEBFFF |
| 157 | * 0x5F [5:4] 0xEC000 - 0xEFFFF |
| 158 | * 00 == DRAM Disabled (All Access go to memory mapped I/O space) |
| 159 | * 01 == Read Only (Reads to DRAM, Writes to memory mapped I/O space) |
| 160 | * 10 == Write Only (Writes to DRAM, Reads to memory mapped I/O space) |
| 161 | * 11 == Normal (All Access go to DRAM) |
| 162 | */ |
| 163 | |
| 164 | // Map all legacy ranges to DRAM |
| 165 | 0x58, 0xcccccf7f, (0x00 << 0) | (0x30 << 8) | (0x33 << 16) | (0x33 << 24), |
| 166 | 0x5C, 0xcccccccc, (0x33 << 0) | (0x33 << 8) | (0x33 << 16) | (0x33 << 24), |
| 167 | |
| 168 | /* DRB - DRAM Row Boundary Registers |
| 169 | * 0x60 - 0x6F |
| 170 | * An array of 8 byte registers, which hold the ending |
| 171 | * memory address assigned to each pair of DIMMS, in 64MB |
| 172 | * granularity. |
| 173 | */ |
| 174 | // Conservatively say each row has 64MB of ram, we will fix this up later |
| 175 | // NOTE: These defaults allow us to prime all of the DIMMs on the board |
| 176 | // without jumping through 36-bit adddressing hoops, even if the |
| 177 | // total memory is > 4 GB. Changing these values may break do_ram_command()! |
| 178 | 0x60, 0x00000000, (0x01 << 0) | (0x02 << 8) | (0x03 << 16) | (0x04 << 24), |
| 179 | 0x64, 0x00000000, (0x05 << 0) | (0x06 << 8) | (0x07 << 16) | (0x08 << 24), |
| 180 | |
| 181 | /* DRA - DRAM Row Attribute Register |
| 182 | * 0x70 Row 0,1 |
| 183 | * 0x71 Row 2,3 |
| 184 | * 0x72 Row 4,5 |
| 185 | * 0x73 Row 6,7 |
| 186 | * [7:7] Device width for Odd numbered rows |
| 187 | * 0 == 8 bits wide x8 |
| 188 | * 1 == 4 bits wide x4 |
| 189 | * [6:4] Row Attributes for Odd numbered rows |
| 190 | * 010 == 8KB (for dual-channel) |
| 191 | * 011 == 16KB (for dual-channel) |
| 192 | * 100 == 32KB (for dual-channel) |
| 193 | * 101 == 64KB (for dual-channel) |
| 194 | * Others == Reserved |
| 195 | * [3:3] Device width for Even numbered rows |
| 196 | * 0 == 8 bits wide x8 |
| 197 | * 1 == 4 bits wide x4 |
| 198 | * [2:0] Row Attributes for Even numbered rows |
| 199 | * 010 == 8KB (for dual-channel) |
| 200 | * 011 == 16KB (for dual-channel) |
| 201 | * 100 == 32KB (for dual-channel) |
| 202 | * 101 == 64KB (This page size appears broken) |
| 203 | * Others == Reserved |
| 204 | */ |
| 205 | // NOTE: overridden by configure_e7501_row_attributes(), later |
| 206 | 0x70, 0x00000000, 0, |
| 207 | |
| 208 | /* DRT - DRAM Timing Register |
| 209 | * 0x78 |
| 210 | * [31:30] Reserved |
| 211 | * [29:29] Back to Back Write-Read Turn Around |
| 212 | * 0 == 3 clocks between WR-RD commands |
| 213 | * 1 == 2 clocks between WR-RD commands |
| 214 | * [28:28] Back to Back Read-Write Turn Around |
| 215 | * 0 == 5 clocks between RD-WR commands |
| 216 | * 1 == 4 clocks between RD-WR commands |
| 217 | * [27:27] Back to Back Read Turn Around |
| 218 | * 0 == 4 clocks between RD commands |
| 219 | * 1 == 3 clocks between RD commands |
| 220 | * [26:24] Read Delay (tRD) |
| 221 | * 000 == 7 clocks |
| 222 | * 001 == 6 clocks |
| 223 | * 010 == 5 clocks |
| 224 | * Others == Reserved |
| 225 | * [23:19] Reserved |
| 226 | * [18:16] DRAM idle timer |
| 227 | * 000 == infinite |
| 228 | * 011 == 16 dram clocks |
| 229 | * 001 == 0 clocks |
| 230 | * [15:11] Reserved |
| 231 | * [10:09] Active to Precharge (tRAS) |
| 232 | * 00 == 7 clocks |
| 233 | * 01 == 6 clocks |
| 234 | * 10 == 5 clocks |
| 235 | * 11 == Reserved |
| 236 | * [08:06] Reserved |
| 237 | * [05:04] Cas Latency (tCL) |
| 238 | * 00 == 2.5 Clocks |
| 239 | * 01 == 2.0 Clocks |
| 240 | * 10 == Reserved (was 1.5 Clocks for E7500) |
| 241 | * 11 == Reserved |
| 242 | * [03:03] Write Ras# to Cas# Delay (tRCD) |
| 243 | * 0 == 3 DRAM Clocks |
| 244 | * 1 == 2 DRAM Clocks |
| 245 | * [02:01] Read RAS# to CAS# Delay (tRCD) |
| 246 | * 00 == reserved |
| 247 | * 01 == reserved |
| 248 | * 10 == 3 DRAM Clocks |
| 249 | * 11 == 2 DRAM Clocks |
| 250 | * [00:00] DRAM RAS# to Precharge (tRP) |
| 251 | * 0 == 3 DRAM Clocks |
| 252 | * 1 == 2 DRAM Clocks |
| 253 | */ |
| 254 | |
| 255 | // Some earlier settings: |
| 256 | /* Most aggressive settings possible */ |
| 257 | // 0x78, 0xc0fff8c4, (1<<29)|(1<<28)|(1<<27)|(2<<24)|(2<<9)|CAS_LATENCY|(1<<3)|(1<<1)|(1<<0), |
| 258 | // 0x78, 0xc0f8f8c0, (1<<29)|(1<<28)|(1<<27)|(1<<24)|(1<<16)|(2<<9)|CAS_LATENCY|(1<<3)|(3<<1)|(1<<0), |
| 259 | // 0x78, 0xc0f8f9c0, (1<<29)|(1<<28)|(1<<27)|(1<<24)|(1<<16)|(2<<9)|CAS_LATENCY|(1<<3)|(3<<1)|(1<<0), |
| 260 | |
| 261 | // The only things we need to set here are DRAM idle timer, Back-to-Back Read Turnaround, and |
| 262 | // Back-to-Back Write-Read Turnaround. All others are configured based on SPD. |
| 263 | 0x78, 0xD7F8FFFF, (1 << 29) | (1 << 27) | (1 << 16), |
| 264 | |
| 265 | /* FIXME why was I attempting to set a reserved bit? */ |
| 266 | /* 0x0100040f */ |
| 267 | |
| 268 | /* DRC - DRAM Contoller Mode Register |
| 269 | * 0x7c |
| 270 | * [31:30] Reserved |
| 271 | * [29:29] Initialization Complete |
| 272 | * 0 == Not Complete |
| 273 | * 1 == Complete |
| 274 | * [28:23] Reserved |
| 275 | * [22:22] Channels |
| 276 | * 0 == Single channel |
| 277 | * 1 == Dual Channel |
| 278 | * [21:20] DRAM Data Integrity Mode |
| 279 | * 00 == Disabled, no ECC |
| 280 | * 01 == Reserved |
| 281 | * 10 == Error checking, using chip-kill, with correction |
| 282 | * 11 == Reserved |
| 283 | * [19:18] DRB Granularity (Read-Only) |
| 284 | * 00 == 32 MB quantities (single channel mode) |
| 285 | * 01 == 64 MB quantities (dual-channel mode) |
| 286 | * 10 == Reserved |
| 287 | * 11 == Reserved |
| 288 | * [17:17] (Intel Undocumented) should always be set to 1 (SJM: comment inconsistent with current setting, below) |
| 289 | * [16:16] Command Per Clock - Address/Control Assertion Rule (CPC) |
| 290 | * 0 == 2n Rule |
| 291 | * 1 == 1n rule |
| 292 | * [15:11] Reserved |
| 293 | * [10:08] Refresh mode select |
| 294 | * 000 == Refresh disabled |
| 295 | * 001 == Refresh interval 15.6 usec |
| 296 | * 010 == Refresh interval 7.8 usec |
| 297 | * 011 == Refresh interval 64 usec |
| 298 | * 111 == Refresh every 64 clocks (fast refresh) |
| 299 | * [07:07] Reserved |
| 300 | * [06:04] Mode Select (SMS) |
| 301 | * 000 == Reserved (was Self Refresh Mode in E7500) |
| 302 | * 001 == NOP Command |
| 303 | * 010 == All Banks Precharge |
| 304 | * 011 == Mode Register Set |
| 305 | * 100 == Extended Mode Register Set |
| 306 | * 101 == Reserved |
| 307 | * 110 == CBR Refresh |
| 308 | * 111 == Normal Operation |
| 309 | * [03:00] Reserved |
| 310 | */ |
| 311 | // .long 0x7c, 0xffcefcff, (1<<22)|(2 << 20)|(1 << 16)| (0 << 8), |
| 312 | // .long 0x7c, 0xff8cfcff, (1<<22)|(2 << 20)|(1 << 17)|(1 << 16)| (0 << 8), |
| 313 | // .long 0x7c, 0xff80fcff, (1<<22)|(2 << 20)|(1 << 18)|(1 << 17)|(1 << 16)| (0 << 8), |
| 314 | |
| 315 | // Default to dual-channel mode, ECC, 1-clock address/cmd hold |
| 316 | // NOTE: configure_e7501_dram_controller_mode() configures further |
| 317 | 0x7c, 0xff8ef8ff, (1 << 22) | (2 << 20) | (1 << 16) | (0 << 8), |
| 318 | |
| 319 | /* Another Intel undocumented register |
| 320 | * 0x88 - 0x8B |
| 321 | * [31:31] Purpose unknown |
| 322 | * [26:26] Master DLL Reset? |
| 323 | * 0 == Normal operation? |
| 324 | * 1 == Reset? |
| 325 | * [07:07] Periodic memory recalibration? |
| 326 | * 0 == Disabled? |
| 327 | * 1 == Enabled? |
| 328 | * [04:04] Receive FIFO RE-Sync? |
| 329 | * 0 == Normal operation? |
| 330 | * 1 == Reset? |
| 331 | */ |
| 332 | // NOTE: Some factory BIOSs don't do this. |
| 333 | // Doesn't seem to matter either way. |
| 334 | 0x88, 0xffffff00, 0x80, |
| 335 | |
| 336 | /* CLOCK_DIS - CK/CK# Disable Register |
| 337 | * 0x8C |
| 338 | * [7:7] DDR Frequency |
| 339 | * 0 == 100 MHz (200 MHz data rate) |
| 340 | * 1 == 133 MHz (266 MHz data rate) |
| 341 | * [6:4] Reserved |
| 342 | * [3:3] CK3 |
| 343 | * 0 == Enable |
| 344 | * 1 == Disable |
| 345 | * [2:2] CK2 |
| 346 | * 0 == Enable |
| 347 | * 1 == Disable |
| 348 | * [1:1] CK1 |
| 349 | * 0 == Enable |
| 350 | * 1 == Disable |
| 351 | * [0:0] CK0 |
| 352 | * 0 == Enable |
| 353 | * 1 == Disable |
| 354 | */ |
| 355 | // NOTE: Disable all clocks initially; turn ones we need back on |
| 356 | // in enable_e7501_clocks() |
| 357 | 0x8C, 0xfffffff0, 0xf, |
| 358 | |
| 359 | /* TOLM - Top of Low Memory Register |
| 360 | * 0xC4 - 0xC5 |
| 361 | * [15:11] Top of low memory (TOLM) |
| 362 | * The address below 4GB that should be treated as RAM, |
| 363 | * on a 128MB granularity. |
| 364 | * [10:00] Reserved |
| 365 | */ |
| 366 | /* REMAPBASE - Remap Base Address Regsiter |
| 367 | * 0xC6 - 0xC7 |
| 368 | * [15:10] Reserved |
| 369 | * [09:00] Remap Base Address [35:26] 64M aligned |
| 370 | * Bits [25:0] are assumed to be 0. |
| 371 | */ |
| 372 | |
| 373 | // NOTE: TOLM overridden by configure_e7501_ram_addresses() |
| 374 | 0xc4, 0xfc0007ff, (0x2000 << 0) | (0x3ff << 16), |
| 375 | |
| 376 | /* REMAPLIMIT - Remap Limit Address Register |
| 377 | * 0xC8 - 0xC9 |
| 378 | * [15:10] Reserved |
| 379 | * [09:00] Remap Limit Address [35:26] 64M aligned |
| 380 | * When remaplimit < remapbase the remap window is disabled. |
| 381 | */ |
| 382 | 0xc8, 0xfffffc00, 0, |
| 383 | |
| 384 | /* DVNP - Device Not Present Register |
| 385 | * 0xE0 - 0xE1 |
| 386 | * [15:05] Reserved |
| 387 | * [04:04] Device 4 Function 1 Present |
| 388 | * 0 == Present |
| 389 | * 1 == Absent |
| 390 | * [03:03] Device 3 Function 1 Present |
| 391 | * 0 == Present |
| 392 | * 1 == Absent |
| 393 | * [02:02] Device 2 Function 1 Present |
| 394 | * 0 == Present |
| 395 | * 1 == Absent |
| 396 | * [01:01] Reserved |
| 397 | * [00:00] Device 0 Function 1 Present |
| 398 | * 0 == Present |
| 399 | * 1 == Absent |
| 400 | */ |
| 401 | |
| 402 | // Enable D0:D1, disable D2:F1, D3:F1, D4:F1 |
| 403 | 0xe0, 0xffffffe2, (1 << 4) | (1 << 3) | (1 << 2) | (0 << 0), |
| 404 | |
| 405 | // Undocumented |
| 406 | 0xd8, 0xffff9fff, 0x00000000, |
| 407 | |
| 408 | // Undocumented - this is pure conjecture based on similarity to 855PM |
| 409 | /* MCHTST - MCH Test Register |
| 410 | * 0xF4 - 0xF7 |
| 411 | * [31:31] Purpose unknown |
| 412 | * [30:30] Purpose unknown |
| 413 | * [29:23] Unknown - not used? |
| 414 | * [22:22] System Memory MMR Enable |
| 415 | * 0 == Disable: mem space and BAR at 0x14 are not accessible |
| 416 | * 1 == Enable: mem space and BAR at 0x14 are accessible |
| 417 | * [21:20] Purpose unknown |
| 418 | * [19:02] Unknown - not used? |
| 419 | * [01:01] D6EN (Device #6 enable) |
| 420 | * 0 == Disable |
| 421 | * 1 == Enable |
| 422 | * [00:00] Unknown - not used? |
| 423 | */ |
| 424 | |
| 425 | 0xf4, 0x3f8ffffd, 0x40300002, |
| 426 | |
| 427 | #ifdef SUSPICIOUS_LOOKING_CODE |
| 428 | // SJM: Undocumented. |
| 429 | // This will access D2:F0:0x50, is this correct?? |
| 430 | 0x1050, 0xffffffcf, 0x00000030, |
| 431 | #endif |
| 432 | }; |
| 433 | |
| 434 | /* DDR RECOMP tables */ |
| 435 | |
| 436 | // Slew table for 1x drive? |
| 437 | static const uint32_t maybe_1x_slew_table[] = { |
| 438 | 0x44332211, 0xc9776655, 0xffffffff, 0xffffffff, |
| 439 | 0x22111111, 0x55444332, 0xfffca876, 0xffffffff, |
| 440 | }; |
| 441 | |
| 442 | // Slew table for 2x drive? |
| 443 | static const uint32_t maybe_2x_slew_table[] = { |
| 444 | 0x00000000, 0x76543210, 0xffffeca8, 0xffffffff, |
| 445 | 0x21000000, 0xa8765432, 0xffffffec, 0xffffffff, |
| 446 | }; |
| 447 | |
| 448 | // Pull Up / Pull Down offset table, if analogous to IXP2800? |
| 449 | static const uint32_t maybe_pull_updown_offset_table[] = { |
| 450 | 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, |
| 451 | 0x88888888, 0x88888888, 0x88888888, 0x88888888, |
| 452 | }; |
| 453 | |
| 454 | /*----------------------------------------------------------------------------- |
| 455 | Delay functions: |
| 456 | -----------------------------------------------------------------------------*/ |
| 457 | |
| 458 | #define SLOW_DOWN_IO inb(0x80) |
| 459 | //#define SLOW_DOWN_IO udelay(40); |
| 460 | |
| 461 | /* Estimate that SLOW_DOWN_IO takes about 50&76us */ |
| 462 | /* delay for 200us */ |
| 463 | |
| 464 | #if 1 |
| 465 | static void do_delay(void) |
| 466 | { |
| 467 | int i; |
| 468 | for (i = 0; i < 16; i++) { |
| 469 | SLOW_DOWN_IO; |
| 470 | } |
| 471 | } |
| 472 | |
| 473 | #define DO_DELAY do_delay() |
| 474 | #else |
| 475 | #define DO_DELAY \ |
| 476 | udelay(200) |
| 477 | #endif |
| 478 | |
| 479 | #define EXTRA_DELAY DO_DELAY |
| 480 | |
| 481 | static void die_on_spd_error(int spd_return_value) |
| 482 | { |
| 483 | if (spd_return_value < 0) |
| 484 | die("Error reading SPD info\n"); |
| 485 | } |
| 486 | |
| 487 | /*----------------------------------------------------------------------------- |
| 488 | Serial presence detect (SPD) functions: |
| 489 | -----------------------------------------------------------------------------*/ |
| 490 | |
| 491 | /** |
| 492 | * Calculate the page size for each physical bank of the DIMM: |
| 493 | * log2(page size) = (# columns) + log2(data width) |
| 494 | * |
| 495 | * NOTE: Page size is the total number of data bits in a row. |
| 496 | * |
| 497 | * @param dimm_socket_address SMBus address of DIMM socket to interrogate. |
| 498 | * @return log2(page size) for each side of the DIMM. |
| 499 | */ |
| 500 | static struct dimm_size sdram_spd_get_page_size(uint16_t dimm_socket_address) |
| 501 | { |
| 502 | uint16_t module_data_width; |
| 503 | int value; |
| 504 | struct dimm_size pgsz; |
| 505 | |
| 506 | pgsz.side1 = 0; |
| 507 | pgsz.side2 = 0; |
| 508 | |
| 509 | // Side 1 |
| 510 | value = spd_read_byte(dimm_socket_address, SPD_NUM_COLUMNS); |
| 511 | if (value < 0) |
| 512 | goto hw_err; |
| 513 | pgsz.side1 = value & 0xf; // # columns in bank 1 |
| 514 | |
| 515 | /* Get the module data width and convert it to a power of two */ |
| 516 | value = |
| 517 | spd_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_MSB); |
| 518 | if (value < 0) |
| 519 | goto hw_err; |
| 520 | module_data_width = (value & 0xff) << 8; |
| 521 | |
| 522 | value = |
| 523 | spd_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_LSB); |
| 524 | if (value < 0) |
| 525 | goto hw_err; |
| 526 | module_data_width |= (value & 0xff); |
| 527 | |
| 528 | pgsz.side1 += log2(module_data_width); |
| 529 | |
| 530 | /* side two */ |
| 531 | value = spd_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS); |
| 532 | if (value < 0) |
| 533 | goto hw_err; |
| 534 | if (value > 2) |
| 535 | die("Bad SPD value\n"); |
| 536 | if (value == 2) { |
| 537 | |
| 538 | pgsz.side2 = pgsz.side1; // Assume symmetric banks until we know differently |
| 539 | value = |
| 540 | spd_read_byte(dimm_socket_address, SPD_NUM_COLUMNS); |
| 541 | if (value < 0) |
| 542 | goto hw_err; |
| 543 | if ((value & 0xf0) != 0) { |
| 544 | // Asymmetric banks |
| 545 | pgsz.side2 -= value & 0xf; /* Subtract out columns on side 1 */ |
| 546 | pgsz.side2 += (value >> 4) & 0xf; /* Add in columns on side 2 */ |
| 547 | } |
| 548 | } |
| 549 | |
| 550 | return pgsz; |
| 551 | |
| 552 | hw_err: |
| 553 | die(SPD_ERROR); |
| 554 | return pgsz; // Never reached |
| 555 | } |
| 556 | |
| 557 | /** |
| 558 | * Read the width in bits of each DIMM side's DRAMs via SPD (i.e. 4, 8, 16). |
| 559 | * |
| 560 | * @param dimm_socket_address SMBus address of DIMM socket to interrogate. |
| 561 | * @return Width in bits of each DIMM side's DRAMs. |
| 562 | */ |
| 563 | static struct dimm_size sdram_spd_get_width(uint16_t dimm_socket_address) |
| 564 | { |
| 565 | int value; |
| 566 | struct dimm_size width; |
| 567 | |
| 568 | width.side1 = 0; |
| 569 | width.side2 = 0; |
| 570 | |
| 571 | value = |
| 572 | spd_read_byte(dimm_socket_address, SPD_PRIMARY_SDRAM_WIDTH); |
| 573 | die_on_spd_error(value); |
| 574 | |
| 575 | width.side1 = value & 0x7f; // Mask off bank 2 flag |
| 576 | |
| 577 | if (value & 0x80) { |
| 578 | width.side2 = width.side1 << 1; // Bank 2 exists and is double-width |
| 579 | } else { |
| 580 | // If bank 2 exists, it's the same width as bank 1 |
| 581 | value = |
| 582 | spd_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS); |
| 583 | die_on_spd_error(value); |
| 584 | |
| 585 | #ifdef ROMCC_IF_BUG_FIXED |
| 586 | if (value == 2) |
| 587 | width.side2 = width.side1; |
| 588 | #else |
| 589 | switch (value) { |
| 590 | case 2: |
| 591 | width.side2 = width.side1; |
| 592 | break; |
| 593 | |
| 594 | default: |
| 595 | break; |
| 596 | } |
| 597 | #endif |
| 598 | } |
| 599 | |
| 600 | return width; |
| 601 | } |
| 602 | |
| 603 | /** |
| 604 | * Calculate the log base 2 size in bits of both DIMM sides. |
| 605 | * |
| 606 | * log2(# bits) = (# columns) + log2(data width) + |
| 607 | * (# rows) + log2(banks per SDRAM) |
| 608 | * |
| 609 | * Note that it might be easier to use SPD byte 31 here, it has the DIMM size |
| 610 | * as a multiple of 4MB. The way we do it now we can size both sides of an |
| 611 | * asymmetric DIMM. |
| 612 | * |
| 613 | * @param dimm_socket_address SMBus address of DIMM socket to interrogate. |
| 614 | * @return log2(number of bits) for each side of the DIMM. |
| 615 | */ |
| 616 | static struct dimm_size spd_get_dimm_size(unsigned dimm_socket_address) |
| 617 | { |
| 618 | int value; |
| 619 | |
| 620 | // Start with log2(page size) |
| 621 | struct dimm_size sz = sdram_spd_get_page_size(dimm_socket_address); |
| 622 | |
| 623 | if (sz.side1 > 0) { |
| 624 | |
| 625 | value = spd_read_byte(dimm_socket_address, SPD_NUM_ROWS); |
| 626 | die_on_spd_error(value); |
| 627 | |
| 628 | sz.side1 += value & 0xf; |
| 629 | |
| 630 | if (sz.side2 > 0) { |
| 631 | |
| 632 | // Double-sided DIMM |
| 633 | if (value & 0xF0) |
| 634 | sz.side2 += value >> 4; // Asymmetric |
| 635 | else |
| 636 | sz.side2 += value; // Symmetric |
| 637 | } |
| 638 | |
| 639 | value = |
| 640 | spd_read_byte(dimm_socket_address, |
| 641 | SPD_NUM_BANKS_PER_SDRAM); |
| 642 | die_on_spd_error(value); |
| 643 | |
| 644 | value = log2(value); |
| 645 | sz.side1 += value; |
| 646 | if (sz.side2 > 0) |
| 647 | sz.side2 += value; |
| 648 | } |
| 649 | |
| 650 | return sz; |
| 651 | } |
| 652 | |
| 653 | #ifdef VALIDATE_DIMM_COMPATIBILITY |
| 654 | |
| 655 | /** |
| 656 | * Determine whether two DIMMs have the same value for an SPD parameter. |
| 657 | * |
| 658 | * @param spd_byte_number The SPD byte number to compare in both DIMMs. |
| 659 | * @param dimm0_address SMBus address of the 1st DIMM socket to interrogate. |
| 660 | * @param dimm1_address SMBus address of the 2nd DIMM socket to interrogate. |
| 661 | * @return 1 if both DIMM sockets report the same value for the specified |
| 662 | * SPD parameter, 0 if the values differed or an error occurred. |
| 663 | */ |
| 664 | static uint8_t are_spd_values_equal(uint8_t spd_byte_number, |
| 665 | uint16_t dimm0_address, |
| 666 | uint16_t dimm1_address) |
| 667 | { |
| 668 | uint8_t bEqual = 0; |
| 669 | int dimm0_value = spd_read_byte(dimm0_address, spd_byte_number); |
| 670 | int dimm1_value = spd_read_byte(dimm1_address, spd_byte_number); |
| 671 | |
| 672 | if ((dimm0_value >= 0) && (dimm1_value >= 0) |
| 673 | && (dimm0_value == dimm1_value)) |
| 674 | bEqual = 1; |
| 675 | |
| 676 | return bEqual; |
| 677 | } |
| 678 | #endif |
| 679 | |
| 680 | /** |
| 681 | * Scan for compatible DIMMs. |
| 682 | * |
| 683 | * The code in this module only supports dual-channel operation, so we test |
| 684 | * that compatible DIMMs are paired. |
| 685 | * |
| 686 | * @param ctrl PCI addresses of memory controller functions, and SMBus |
| 687 | * addresses of DIMM slots on the mainboard. |
| 688 | * @return A bitmask indicating which of the possible sockets for each channel |
| 689 | * was found to contain a compatible DIMM. |
| 690 | * Bit 0 corresponds to the closest socket for channel 0 |
| 691 | * Bit 1 to the next socket for channel 0 |
| 692 | * ... |
| 693 | * Bit MAX_DIMM_SOCKETS_PER_CHANNEL-1 to the last socket for channel 0 |
| 694 | * Bit MAX_DIMM_SOCKETS_PER_CHANNEL is the closest socket for channel 1 |
| 695 | * ... |
| 696 | * Bit 2*MAX_DIMM_SOCKETS_PER_CHANNEL-1 is the last socket for channel 1 |
| 697 | */ |
| 698 | static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl) |
| 699 | { |
| 700 | int i; |
| 701 | uint8_t dimm_mask = 0; |
| 702 | |
| 703 | // Have to increase size of dimm_mask if this assertion is violated |
| 704 | ASSERT(MAX_DIMM_SOCKETS_PER_CHANNEL <= 4); |
| 705 | |
| 706 | // Find DIMMs we can support on channel 0. |
| 707 | // Then see if the corresponding channel 1 DIMM has the same parameters, |
| 708 | // since we only support dual-channel. |
| 709 | |
| 710 | for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) { |
| 711 | |
| 712 | uint16_t channel0_dimm = ctrl->channel0[i]; |
| 713 | uint16_t channel1_dimm = ctrl->channel1[i]; |
| 714 | uint8_t bDualChannel = 1; |
| 715 | #ifdef VALIDATE_DIMM_COMPATIBILITY |
| 716 | struct dimm_size page_size; |
| 717 | struct dimm_size sdram_width; |
| 718 | #endif |
| 719 | int spd_value; |
| 720 | |
| 721 | if (channel0_dimm == 0) |
| 722 | continue; // No such socket on this mainboard |
| 723 | |
| 724 | if (spd_read_byte(channel0_dimm, SPD_MEMORY_TYPE) != |
| 725 | SPD_MEMORY_TYPE_SDRAM_DDR) |
| 726 | continue; |
| 727 | |
| 728 | #ifdef VALIDATE_DIMM_COMPATIBILITY |
| 729 | if (spd_read_byte(channel0_dimm, SPD_MODULE_VOLTAGE) != |
| 730 | SPD_VOLTAGE_SSTL2) |
| 731 | continue; // Unsupported voltage |
| 732 | |
| 733 | // E7501 does not support unregistered DIMMs |
| 734 | spd_value = |
| 735 | spd_read_byte(channel0_dimm, SPD_MODULE_ATTRIBUTES); |
| 736 | if (!(spd_value & MODULE_REGISTERED) || (spd_value < 0)) |
| 737 | continue; |
| 738 | |
| 739 | // Must support burst = 4 for dual-channel operation on E7501 |
| 740 | // NOTE: for single-channel, burst = 8 is required |
| 741 | spd_value = |
| 742 | spd_read_byte(channel0_dimm, |
| 743 | SPD_SUPPORTED_BURST_LENGTHS); |
| 744 | if (!(spd_value & SPD_BURST_LENGTH_4) || (spd_value < 0)) |
| 745 | continue; |
| 746 | |
| 747 | page_size = sdram_spd_get_page_size(channel0_dimm); |
| 748 | sdram_width = sdram_spd_get_width(channel0_dimm); |
| 749 | |
| 750 | // Validate DIMM page size |
| 751 | // The E7501 only supports page sizes of 4, 8, 16, or 32 KB per channel |
| 752 | // NOTE: 4 KB = 32 Kb = 2^15 |
| 753 | // 32 KB = 262 Kb = 2^18 |
| 754 | |
| 755 | if ((page_size.side1 < 15) || (page_size.side1 > 18)) |
| 756 | continue; |
| 757 | |
| 758 | // If DIMM is double-sided, verify side2 page size |
| 759 | if (page_size.side2 != 0) { |
| 760 | if ((page_size.side2 < 15) |
| 761 | || (page_size.side2 > 18)) |
| 762 | continue; |
| 763 | } |
| 764 | // Validate SDRAM width |
| 765 | // The E7501 only supports x4 and x8 devices |
| 766 | |
| 767 | if ((sdram_width.side1 != 4) && (sdram_width.side1 != 8)) |
| 768 | continue; |
| 769 | |
| 770 | // If DIMM is double-sided, verify side2 width |
| 771 | if (sdram_width.side2 != 0) { |
| 772 | if ((sdram_width.side2 != 4) |
| 773 | && (sdram_width.side2 != 8)) |
| 774 | continue; |
| 775 | } |
| 776 | #endif |
| 777 | // Channel 0 DIMM looks compatible. |
| 778 | // Now see if it is paired with the proper DIMM on channel 1. |
| 779 | |
| 780 | ASSERT(channel1_dimm != 0); // No such socket on this mainboard?? |
| 781 | |
| 782 | // NOTE: unpopulated DIMMs cause read to fail |
| 783 | spd_value = |
| 784 | spd_read_byte(channel1_dimm, SPD_MODULE_ATTRIBUTES); |
| 785 | if (!(spd_value & MODULE_REGISTERED) || (spd_value < 0)) { |
| 786 | |
| 787 | print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n"); |
| 788 | continue; |
| 789 | } |
| 790 | #ifdef VALIDATE_DIMM_COMPATIBILITY |
| 791 | spd_value = |
| 792 | spd_read_byte(channel1_dimm, |
| 793 | SPD_SUPPORTED_BURST_LENGTHS); |
| 794 | if (!(spd_value & SPD_BURST_LENGTH_4) || (spd_value < 0)) |
| 795 | continue; |
| 796 | |
| 797 | int j; |
| 798 | for (j = 0; j < sizeof(dual_channel_parameters); ++j) { |
| 799 | if (!are_spd_values_equal |
| 800 | (dual_channel_parameters[j], channel0_dimm, |
| 801 | channel1_dimm)) { |
| 802 | |
| 803 | bDualChannel = 0; |
| 804 | break; |
| 805 | } |
| 806 | } |
| 807 | #endif |
| 808 | |
| 809 | // Code around ROMCC bug in optimization of "if" statements |
| 810 | #ifdef ROMCC_IF_BUG_FIXED |
| 811 | if (bDualChannel) { |
| 812 | // Made it through all the checks, this DIMM pair is usable |
| 813 | dimm_mask |= ((1 << i) | (1 << (MAX_DIMM_SOCKETS_PER_CHANNEL + i))); |
| 814 | } else |
| 815 | print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n"); |
| 816 | #else |
| 817 | switch (bDualChannel) { |
| 818 | case 0: |
| 819 | print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n"); |
| 820 | break; |
| 821 | |
| 822 | default: |
| 823 | // Made it through all the checks, this DIMM pair is usable |
| 824 | dimm_mask |= (1 << i) | (1 << (MAX_DIMM_SOCKETS_PER_CHANNEL + i)); |
| 825 | break; |
| 826 | } |
| 827 | #endif |
| 828 | } |
| 829 | |
| 830 | return dimm_mask; |
| 831 | } |
| 832 | |
| 833 | /*----------------------------------------------------------------------------- |
| 834 | SDRAM configuration functions: |
| 835 | -----------------------------------------------------------------------------*/ |
| 836 | |
| 837 | /** |
| 838 | * Send the specified command to all DIMMs. |
| 839 | * |
| 840 | * @param command Specifies the command to be sent to the DIMMs. |
| 841 | * @param jedec_mode_bits For the MRS & EMRS commands, bits 0-12 contain the |
| 842 | * register value in JEDEC format. |
| 843 | */ |
| 844 | static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits) |
| 845 | { |
| 846 | int i; |
| 847 | uint32_t dram_controller_mode; |
| 848 | uint8_t dimm_start_64M_multiple = 0; |
| 849 | uint16_t e7501_mode_bits = jedec_mode_bits; |
| 850 | |
| 851 | // Configure the RAM command |
| 852 | dram_controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC); |
| 853 | dram_controller_mode &= 0xFFFFFF8F; |
| 854 | dram_controller_mode |= command; |
| 855 | pci_write_config32(PCI_DEV(0, 0, 0), DRC, dram_controller_mode); |
| 856 | |
| 857 | // RAM_COMMAND_NORMAL is an exception. |
| 858 | // It affects only the memory controller and does not need to be "sent" to the DIMMs. |
| 859 | |
| 860 | if (command != RAM_COMMAND_NORMAL) { |
| 861 | |
| 862 | // Send the command to all DIMMs by accessing a memory location within each |
| 863 | // NOTE: for mode select commands, some of the location address bits |
| 864 | // are part of the command |
| 865 | |
| 866 | // Map JEDEC mode bits to E7501 |
| 867 | if (command == RAM_COMMAND_MRS) { |
| 868 | // Host address lines [15:5] map to DIMM address lines [12:11, 9:1] |
| 869 | // The E7501 hard-sets DIMM address lines 10 & 0 to zero |
| 870 | |
| 871 | ASSERT(!(jedec_mode_bits & 0x0401)); |
| 872 | |
| 873 | e7501_mode_bits = ((jedec_mode_bits & 0x1800) << (15 - 12)) | // JEDEC bits 11-12 move to bits 14-15 |
| 874 | ((jedec_mode_bits & 0x03FE) << (13 - 9)); // JEDEC bits 1-9 move to bits 5-13 |
| 875 | |
| 876 | } else if (command == RAM_COMMAND_EMRS) { |
| 877 | // Host address lines [15:3] map to DIMM address lines [12:0] |
| 878 | e7501_mode_bits = jedec_mode_bits <<= 3; |
| 879 | } else |
| 880 | ASSERT(jedec_mode_bits == 0); |
| 881 | |
| 882 | dimm_start_64M_multiple = 0; |
| 883 | |
| 884 | for (i = 0; i < (MAX_NUM_CHANNELS * MAX_DIMM_SOCKETS_PER_CHANNEL); ++i) { |
| 885 | |
| 886 | uint8_t dimm_end_64M_multiple = |
| 887 | pci_read_config8(PCI_DEV(0, 0, 0), DRB_ROW_0 + i); |
| 888 | if (dimm_end_64M_multiple > dimm_start_64M_multiple) { |
| 889 | |
| 890 | // This code assumes DRAM row boundaries are all set below 4 GB |
| 891 | // NOTE: 0x40 * 64 MB == 4 GB |
| 892 | ASSERT(dimm_start_64M_multiple < 0x40); |
| 893 | |
| 894 | // NOTE: 2^26 == 64 MB |
| 895 | |
| 896 | uint32_t dimm_start_address = |
| 897 | dimm_start_64M_multiple << 26; |
| 898 | |
| 899 | RAM_DEBUG_MESSAGE(" Sending RAM command to 0x"); |
| 900 | RAM_DEBUG_HEX32(dimm_start_address + e7501_mode_bits); |
| 901 | RAM_DEBUG_MESSAGE("\n"); |
| 902 | |
| 903 | read32(dimm_start_address + e7501_mode_bits); |
| 904 | |
| 905 | // Set the start of the next DIMM |
| 906 | dimm_start_64M_multiple = |
| 907 | dimm_end_64M_multiple; |
| 908 | } |
| 909 | } |
| 910 | } |
| 911 | } |
| 912 | |
| 913 | /** |
| 914 | * Set the mode register of all DIMMs. |
| 915 | * |
| 916 | * The proper CAS# latency setting is added to the mode bits specified |
| 917 | * by the caller. |
| 918 | * |
| 919 | * @param jedec_mode_bits For the MRS & EMRS commands, bits 0-12 contain the |
| 920 | * register value in JEDEC format. |
| 921 | */ |
| 922 | static void set_ram_mode(uint16_t jedec_mode_bits) |
| 923 | { |
| 924 | ASSERT(!(jedec_mode_bits & SDRAM_CAS_MASK)); |
| 925 | |
| 926 | uint32_t dram_cas_latency = |
| 927 | pci_read_config32(PCI_DEV(0, 0, 0), DRT) & DRT_CAS_MASK; |
| 928 | |
| 929 | switch (dram_cas_latency) { |
| 930 | case DRT_CAS_2_5: |
| 931 | jedec_mode_bits |= SDRAM_CAS_2_5; |
| 932 | break; |
| 933 | |
| 934 | case DRT_CAS_2_0: |
| 935 | jedec_mode_bits |= SDRAM_CAS_2_0; |
| 936 | break; |
| 937 | |
| 938 | default: |
| 939 | BUG(); |
| 940 | break; |
| 941 | } |
| 942 | |
| 943 | do_ram_command(RAM_COMMAND_MRS, jedec_mode_bits); |
| 944 | } |
| 945 | |
| 946 | /*----------------------------------------------------------------------------- |
| 947 | DIMM-independant configuration functions: |
| 948 | -----------------------------------------------------------------------------*/ |
| 949 | |
| 950 | /** |
| 951 | * Configure the E7501's DRAM Row Boundary (DRB) registers for the memory |
| 952 | * present in the specified DIMM. |
| 953 | * |
| 954 | * @param dimm_log2_num_bits Specifies log2(number of bits) for each side of |
| 955 | * the DIMM. |
| 956 | * @param total_dram_64M_multiple Total DRAM in the system (as a multiple of |
| 957 | * 64 MB) for DIMMs < dimm_index. |
| 958 | * @param dimm_index Which DIMM pair is being processed |
| 959 | * (0..MAX_DIMM_SOCKETS_PER_CHANNEL). |
| 960 | * @return New multiple of 64 MB total DRAM in the system. |
| 961 | */ |
| 962 | static uint8_t configure_dimm_row_boundaries(struct dimm_size dimm_log2_num_bits, uint8_t total_dram_64M_multiple, unsigned dimm_index) |
| 963 | { |
| 964 | int i; |
| 965 | |
| 966 | ASSERT(dimm_index < MAX_DIMM_SOCKETS_PER_CHANNEL); |
| 967 | |
| 968 | // DIMM sides must be at least 32 MB |
| 969 | ASSERT(dimm_log2_num_bits.side1 >= 28); |
| 970 | ASSERT((dimm_log2_num_bits.side2 == 0) |
| 971 | || (dimm_log2_num_bits.side2 >= 28)); |
| 972 | |
| 973 | // In dual-channel mode, we are called only once for each pair of DIMMs. |
| 974 | // Each time we process twice the capacity of a single DIMM. |
| 975 | |
| 976 | // Convert single DIMM capacity to paired DIMM capacity |
| 977 | // (multiply by two ==> add 1 to log2) |
| 978 | dimm_log2_num_bits.side1++; |
| 979 | if (dimm_log2_num_bits.side2 > 0) |
| 980 | dimm_log2_num_bits.side2++; |
| 981 | |
| 982 | // Add the capacity of side 1 this DIMM pair (as a multiple of 64 MB) |
| 983 | // to the total capacity of the system |
| 984 | // NOTE: 64 MB == 512 Mb, and log2(512 Mb) == 29 |
| 985 | |
| 986 | total_dram_64M_multiple += (1 << (dimm_log2_num_bits.side1 - 29)); |
| 987 | |
| 988 | // Configure the boundary address for the row on side 1 |
| 989 | pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_0 + (dimm_index << 1), |
| 990 | total_dram_64M_multiple); |
| 991 | |
| 992 | // If the DIMMs are double-sided, add the capacity of side 2 this DIMM pair |
| 993 | // (as a multiple of 64 MB) to the total capacity of the system |
| 994 | if (dimm_log2_num_bits.side2 >= 29) |
| 995 | total_dram_64M_multiple += |
| 996 | (1 << (dimm_log2_num_bits.side2 - 29)); |
| 997 | |
| 998 | // Configure the boundary address for the row (if any) on side 2 |
| 999 | pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_1 + (dimm_index << 1), |
| 1000 | total_dram_64M_multiple); |
| 1001 | |
| 1002 | // Update boundaries for rows subsequent to these. |
| 1003 | // These settings will be overridden by a subsequent call if a populated physical slot exists |
| 1004 | |
| 1005 | for (i = dimm_index + 1; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) { |
| 1006 | pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_0 + (i << 1), |
| 1007 | total_dram_64M_multiple); |
| 1008 | pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_1 + (i << 1), |
| 1009 | total_dram_64M_multiple); |
| 1010 | } |
| 1011 | |
| 1012 | return total_dram_64M_multiple; |
| 1013 | } |
| 1014 | |
| 1015 | /** |
| 1016 | * Set the E7501's DRAM row boundary addresses & its Top Of Low Memory (TOLM). |
| 1017 | * |
| 1018 | * If necessary, set up a remap window so we don't waste DRAM that ordinarily |
| 1019 | * would lie behind addresses reserved for memory-mapped I/O. |
| 1020 | * |
| 1021 | * @param ctrl PCI addresses of memory controller functions, and SMBus |
| 1022 | * addresses of DIMM slots on the mainboard. |
| 1023 | * @param dimm_mask Bitmask of populated DIMMs, see spd_get_supported_dimms(). |
| 1024 | */ |
| 1025 | static void configure_e7501_ram_addresses(const struct mem_controller |
| 1026 | *ctrl, uint8_t dimm_mask) |
| 1027 | { |
| 1028 | int i; |
| 1029 | uint8_t total_dram_64M_multiple = 0; |
| 1030 | |
| 1031 | // Configure the E7501's DRAM row boundaries |
| 1032 | // Start by zeroing out the temporary initial configuration |
| 1033 | pci_write_config32(PCI_DEV(0, 0, 0), DRB_ROW_0, 0); |
| 1034 | pci_write_config32(PCI_DEV(0, 0, 0), DRB_ROW_4, 0); |
| 1035 | |
| 1036 | for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) { |
| 1037 | |
| 1038 | uint16_t dimm_socket_address = ctrl->channel0[i]; |
| 1039 | struct dimm_size sz; |
| 1040 | |
| 1041 | if (!(dimm_mask & (1 << i))) |
| 1042 | continue; // This DIMM not present |
| 1043 | |
| 1044 | sz = spd_get_dimm_size(dimm_socket_address); |
| 1045 | |
| 1046 | RAM_DEBUG_MESSAGE("dimm size ="); |
| 1047 | RAM_DEBUG_HEX32((u32)sz.side1); |
| 1048 | RAM_DEBUG_MESSAGE(" "); |
| 1049 | RAM_DEBUG_HEX32((u32)sz.side2); |
| 1050 | RAM_DEBUG_MESSAGE("\n"); |
| 1051 | |
| 1052 | if (sz.side1 == 0) |
| 1053 | die("Bad SPD value\n"); |
| 1054 | |
| 1055 | total_dram_64M_multiple = |
| 1056 | configure_dimm_row_boundaries(sz, total_dram_64M_multiple, i); |
| 1057 | } |
| 1058 | |
| 1059 | // Configure the Top Of Low Memory (TOLM) in the E7501 |
| 1060 | // This address must be a multiple of 128 MB that is less than 4 GB. |
| 1061 | // NOTE: 16-bit wide TOLM register stores only the highest 5 bits of a 32-bit address |
| 1062 | // in the highest 5 bits. |
| 1063 | |
| 1064 | // We set TOLM to the smaller of 0xC0000000 (3 GB) or the total DRAM in the system. |
| 1065 | // This reserves addresses from 0xC0000000 - 0xFFFFFFFF for non-DRAM purposes |
| 1066 | // such as flash and memory-mapped I/O. |
| 1067 | |
| 1068 | // If there is more than 3 GB of DRAM, we define a remap window which |
| 1069 | // makes the DRAM "behind" the reserved region available above the top of physical |
| 1070 | // memory. |
| 1071 | |
| 1072 | // NOTE: 0xC0000000 / (64 MB) == 0x30 |
| 1073 | |
| 1074 | if (total_dram_64M_multiple <= 0x30) { |
| 1075 | |
| 1076 | // <= 3 GB total RAM |
| 1077 | |
| 1078 | /* I should really adjust all of this in C after I have resources |
| 1079 | * to all of the pci devices. |
| 1080 | */ |
| 1081 | |
| 1082 | // Round up to 128MB granularity |
| 1083 | // SJM: Is "missing" 64 MB of memory a potential issue? Should this round down? |
| 1084 | |
| 1085 | uint8_t total_dram_128M_multiple = |
| 1086 | (total_dram_64M_multiple + 1) >> 1; |
| 1087 | |
| 1088 | // Convert to high 16 bits of address |
| 1089 | uint16_t top_of_low_memory = |
| 1090 | total_dram_128M_multiple << 11; |
| 1091 | |
| 1092 | pci_write_config16(PCI_DEV(0, 0, 0), TOLM, |
| 1093 | top_of_low_memory); |
| 1094 | |
| 1095 | } else { |
| 1096 | |
| 1097 | // > 3 GB total RAM |
| 1098 | |
| 1099 | // Set defaults for > 4 GB DRAM, i.e. remap a 1 GB (= 0x10 * 64 MB) range of memory |
| 1100 | uint16_t remap_base = total_dram_64M_multiple; // A[25:0] == 0 |
| 1101 | uint16_t remap_limit = total_dram_64M_multiple + 0x10 - 1; // A[25:0] == 0xF |
| 1102 | |
| 1103 | // Put TOLM at 3 GB |
| 1104 | |
| 1105 | pci_write_config16(PCI_DEV(0, 0, 0), TOLM, 0xc000); |
| 1106 | |
| 1107 | // Define a remap window to make the RAM that would appear from 3 GB - 4 GB |
| 1108 | // visible just beyond 4 GB or the end of physical memory, whichever is larger |
| 1109 | // NOTE: 16-bit wide REMAP registers store only the highest 10 bits of a 36-bit address, |
| 1110 | // (i.e. a multiple of 64 MB) in the lowest 10 bits. |
| 1111 | // NOTE: 0x100000000 / (64 MB) == 0x40 |
| 1112 | |
| 1113 | if (total_dram_64M_multiple < 0x40) { |
| 1114 | remap_base = 0x40; // 0x100000000 |
| 1115 | remap_limit = |
| 1116 | 0x40 + (total_dram_64M_multiple - 0x30) - 1; |
| 1117 | } |
| 1118 | |
| 1119 | pci_write_config16(PCI_DEV(0, 0, 0), REMAPBASE, |
| 1120 | remap_base); |
| 1121 | pci_write_config16(PCI_DEV(0, 0, 0), REMAPLIMIT, |
| 1122 | remap_limit); |
| 1123 | } |
| 1124 | } |
| 1125 | |
| 1126 | /** |
| 1127 | * If we're configured to use ECC, initialize the SDRAM and clear the E7501's |
| 1128 | * ECC error flags. |
| 1129 | */ |
| 1130 | static void initialize_ecc(void) |
| 1131 | { |
| 1132 | uint32_t dram_controller_mode; |
| 1133 | |
| 1134 | /* Test to see if ECC support is enabled */ |
| 1135 | dram_controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC); |
| 1136 | dram_controller_mode >>= 20; |
| 1137 | dram_controller_mode &= 3; |
| 1138 | if (dram_controller_mode == 2) { |
| 1139 | |
| 1140 | uint8_t byte; |
| 1141 | |
| 1142 | RAM_DEBUG_MESSAGE("Initializing ECC state...\n"); |
| 1143 | /* Initialize ECC bits , use ECC zero mode (new to 7501) */ |
| 1144 | pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, 0x06); |
| 1145 | pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, 0x07); |
| 1146 | |
| 1147 | // Wait for scrub cycle to complete |
| 1148 | do { |
| 1149 | byte = |
| 1150 | pci_read_config8(PCI_DEV(0, 0, 0), MCHCFGNS); |
| 1151 | } while ((byte & 0x08) == 0); |
| 1152 | |
| 1153 | pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, byte & 0xfc); |
| 1154 | RAM_DEBUG_MESSAGE("ECC state initialized.\n"); |
| 1155 | |
| 1156 | /* Clear the ECC error bits */ |
| 1157 | pci_write_config8(PCI_DEV(0, 0, 1), DRAM_FERR, 0x03); |
| 1158 | pci_write_config8(PCI_DEV(0, 0, 1), DRAM_NERR, 0x03); |
| 1159 | |
| 1160 | // Clear DRAM Interface error bits (write-one-clear) |
| 1161 | pci_write_config32(PCI_DEV(0, 0, 1), FERR_GLOBAL, 1 << 18); |
| 1162 | pci_write_config32(PCI_DEV(0, 0, 1), NERR_GLOBAL, 1 << 18); |
| 1163 | |
| 1164 | // Start normal ECC scrub |
| 1165 | pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, 5); |
| 1166 | } |
| 1167 | |
| 1168 | } |
| 1169 | |
| 1170 | /** |
| 1171 | * Program the DRAM Timing register (DRT) of the E7501 (except for CAS# |
| 1172 | * latency, which is assumed to have been programmed already), based on the |
| 1173 | * parameters of the various installed DIMMs. |
| 1174 | * |
| 1175 | * @param ctrl PCI addresses of memory controller functions, and SMBus |
| 1176 | * addresses of DIMM slots on the mainboard. |
| 1177 | * @param dimm_mask Bitmask of populated DIMMs, see spd_get_supported_dimms(). |
| 1178 | */ |
| 1179 | static void configure_e7501_dram_timing(const struct mem_controller *ctrl, |
| 1180 | uint8_t dimm_mask) |
| 1181 | { |
| 1182 | int i; |
| 1183 | uint32_t dram_timing; |
| 1184 | int value; |
| 1185 | uint8_t slowest_row_precharge = 0; |
| 1186 | uint8_t slowest_ras_cas_delay = 0; |
| 1187 | uint8_t slowest_active_to_precharge_delay = 0; |
| 1188 | uint32_t current_cas_latency = |
| 1189 | pci_read_config32(PCI_DEV(0, 0, 0), DRT) & DRT_CAS_MASK; |
| 1190 | |
| 1191 | // CAS# latency must be programmed beforehand |
| 1192 | ASSERT((current_cas_latency == DRT_CAS_2_0) |
| 1193 | || (current_cas_latency == DRT_CAS_2_5)); |
| 1194 | |
| 1195 | // Each timing parameter is determined by the slowest DIMM |
| 1196 | |
| 1197 | for (i = 0; i < MAX_DIMM_SOCKETS; i++) { |
| 1198 | uint16_t dimm_socket_address; |
| 1199 | |
| 1200 | if (!(dimm_mask & (1 << i))) |
| 1201 | continue; // This DIMM not present |
| 1202 | |
| 1203 | if (i < MAX_DIMM_SOCKETS_PER_CHANNEL) |
| 1204 | dimm_socket_address = ctrl->channel0[i]; |
| 1205 | else |
| 1206 | dimm_socket_address = |
| 1207 | ctrl->channel1[i - MAX_DIMM_SOCKETS_PER_CHANNEL]; |
| 1208 | |
| 1209 | value = |
| 1210 | spd_read_byte(dimm_socket_address, |
| 1211 | SPD_MIN_ROW_PRECHARGE_TIME); |
| 1212 | if (value < 0) |
| 1213 | goto hw_err; |
| 1214 | if (value > slowest_row_precharge) |
| 1215 | slowest_row_precharge = value; |
| 1216 | |
| 1217 | value = |
| 1218 | spd_read_byte(dimm_socket_address, |
| 1219 | SPD_MIN_RAS_TO_CAS_DELAY); |
| 1220 | if (value < 0) |
| 1221 | goto hw_err; |
| 1222 | if (value > slowest_ras_cas_delay) |
| 1223 | slowest_ras_cas_delay = value; |
| 1224 | |
| 1225 | value = |
| 1226 | spd_read_byte(dimm_socket_address, |
| 1227 | SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY); |
| 1228 | if (value < 0) |
| 1229 | goto hw_err; |
| 1230 | if (value > slowest_active_to_precharge_delay) |
| 1231 | slowest_active_to_precharge_delay = value; |
| 1232 | } |
| 1233 | |
| 1234 | // NOTE for timing parameters: |
| 1235 | // At 133 MHz, 1 clock == 7.52 ns |
| 1236 | |
| 1237 | /* Read the initial state */ |
| 1238 | dram_timing = pci_read_config32(PCI_DEV(0, 0, 0), DRT); |
| 1239 | |
| 1240 | /* Trp */ |
| 1241 | |
| 1242 | // E7501 supports only 2 or 3 clocks for tRP |
| 1243 | if (slowest_row_precharge > ((22 << 2) | (2 << 0))) |
| 1244 | die("unsupported DIMM tRP"); // > 22.5 ns: 4 or more clocks |
| 1245 | else if (slowest_row_precharge > (15 << 2)) |
| 1246 | dram_timing &= ~(1 << 0); // > 15.0 ns: 3 clocks |
| 1247 | else |
| 1248 | dram_timing |= (1 << 0); // <= 15.0 ns: 2 clocks |
| 1249 | |
| 1250 | /* Trcd */ |
| 1251 | |
| 1252 | // E7501 supports only 2 or 3 clocks for tRCD |
| 1253 | // Use the same value for both read & write |
| 1254 | dram_timing &= ~((1 << 3) | (3 << 1)); |
| 1255 | if (slowest_ras_cas_delay > ((22 << 2) | (2 << 0))) |
| 1256 | die("unsupported DIMM tRCD"); // > 22.5 ns: 4 or more clocks |
| 1257 | else if (slowest_ras_cas_delay > (15 << 2)) |
| 1258 | dram_timing |= (2 << 1); // > 15.0 ns: 3 clocks |
| 1259 | else |
| 1260 | dram_timing |= ((1 << 3) | (3 << 1)); // <= 15.0 ns: 2 clocks |
| 1261 | |
| 1262 | /* Tras */ |
| 1263 | |
| 1264 | // E7501 supports only 5, 6, or 7 clocks for tRAS |
| 1265 | // 5 clocks ~= 37.6 ns, 6 clocks ~= 45.1 ns, 7 clocks ~= 52.6 ns |
| 1266 | dram_timing &= ~(3 << 9); |
| 1267 | |
| 1268 | if (slowest_active_to_precharge_delay > 52) |
| 1269 | die("unsupported DIMM tRAS"); // > 52 ns: 8 or more clocks |
| 1270 | else if (slowest_active_to_precharge_delay > 45) |
| 1271 | dram_timing |= (0 << 9); // 46-52 ns: 7 clocks |
| 1272 | else if (slowest_active_to_precharge_delay > 37) |
| 1273 | dram_timing |= (1 << 9); // 38-45 ns: 6 clocks |
| 1274 | else |
| 1275 | dram_timing |= (2 << 9); // < 38 ns: 5 clocks |
| 1276 | |
| 1277 | /* Trd */ |
| 1278 | |
| 1279 | /* Set to a 7 clock read delay. This is for 133Mhz |
| 1280 | * with a CAS latency of 2.5 if 2.0 a 6 clock |
| 1281 | * delay is good */ |
| 1282 | |
| 1283 | dram_timing &= ~(7 << 24); // 7 clocks |
| 1284 | if (current_cas_latency == DRT_CAS_2_0) |
| 1285 | dram_timing |= (1 << 24); // 6 clocks |
| 1286 | |
| 1287 | /* |
| 1288 | * Back to Back Read-Write Turn Around |
| 1289 | */ |
| 1290 | /* Set to a 5 clock back to back read to write turn around. |
| 1291 | * 4 is a good delay if the CAS latency is 2.0 */ |
| 1292 | |
| 1293 | dram_timing &= ~(1 << 28); // 5 clocks |
| 1294 | if (current_cas_latency == DRT_CAS_2_0) |
| 1295 | dram_timing |= (1 << 28); // 4 clocks |
| 1296 | |
| 1297 | pci_write_config32(PCI_DEV(0, 0, 0), DRT, dram_timing); |
| 1298 | |
| 1299 | return; |
| 1300 | |
| 1301 | hw_err: |
| 1302 | die(SPD_ERROR); |
| 1303 | } |
| 1304 | |
| 1305 | /** |
| 1306 | * Determine the shortest CAS# latency that the E7501 and all DIMMs have in |
| 1307 | * common, and program the E7501 to use it. |
| 1308 | * |
| 1309 | * @param ctrl PCI addresses of memory controller functions, and SMBus |
| 1310 | * addresses of DIMM slots on the mainboard. |
| 1311 | * @param dimm_mask Bitmask of populated DIMMs, spd_get_supported_dimms(). |
| 1312 | */ |
| 1313 | static void configure_e7501_cas_latency(const struct mem_controller *ctrl, |
| 1314 | uint8_t dimm_mask) |
| 1315 | { |
| 1316 | int i; |
| 1317 | int value; |
| 1318 | uint32_t dram_timing; |
| 1319 | uint16_t maybe_dram_read_timing; |
| 1320 | uint32_t dword; |
| 1321 | |
| 1322 | // CAS# latency bitmasks in SPD_ACCEPTABLE_CAS_LATENCIES format |
| 1323 | // NOTE: E7501 supports only 2.0 and 2.5 |
| 1324 | uint32_t system_compatible_cas_latencies = |
| 1325 | SPD_CAS_LATENCY_2_0 | SPD_CAS_LATENCY_2_5; |
| 1326 | uint32_t current_cas_latency; |
| 1327 | uint32_t dimm_compatible_cas_latencies; |
| 1328 | |
| 1329 | for (i = 0; i < MAX_DIMM_SOCKETS; i++) { |
| 1330 | |
| 1331 | uint16_t dimm_socket_address; |
| 1332 | |
| 1333 | if (!(dimm_mask & (1 << i))) |
| 1334 | continue; // This DIMM not usable |
| 1335 | |
| 1336 | if (i < MAX_DIMM_SOCKETS_PER_CHANNEL) |
| 1337 | dimm_socket_address = ctrl->channel0[i]; |
| 1338 | else |
| 1339 | dimm_socket_address = |
| 1340 | ctrl->channel1[i - MAX_DIMM_SOCKETS_PER_CHANNEL]; |
| 1341 | |
| 1342 | value = |
| 1343 | spd_read_byte(dimm_socket_address, |
| 1344 | SPD_ACCEPTABLE_CAS_LATENCIES); |
| 1345 | if (value < 0) |
| 1346 | goto hw_err; |
| 1347 | |
| 1348 | dimm_compatible_cas_latencies = value & 0x7f; // Start with all supported by DIMM |
| 1349 | current_cas_latency = 1 << log2(dimm_compatible_cas_latencies); // Max supported by DIMM |
| 1350 | |
| 1351 | // Can we support the highest CAS# latency? |
| 1352 | |
| 1353 | value = |
| 1354 | spd_read_byte(dimm_socket_address, |
| 1355 | SPD_MIN_CYCLE_TIME_AT_CAS_MAX); |
| 1356 | if (value < 0) |
| 1357 | goto hw_err; |
| 1358 | |
| 1359 | // NOTE: At 133 MHz, 1 clock == 7.52 ns |
| 1360 | if (value > 0x75) { |
| 1361 | // Our bus is too fast for this CAS# latency |
| 1362 | // Remove it from the bitmask of those supported by the DIMM that are compatible |
| 1363 | dimm_compatible_cas_latencies &= ~current_cas_latency; |
| 1364 | } |
| 1365 | // Can we support the next-highest CAS# latency (max - 0.5)? |
| 1366 | |
| 1367 | current_cas_latency >>= 1; |
| 1368 | if (current_cas_latency != 0) { |
| 1369 | value = |
| 1370 | spd_read_byte(dimm_socket_address, |
| 1371 | SPD_SDRAM_CYCLE_TIME_2ND); |
| 1372 | if (value < 0) |
| 1373 | goto hw_err; |
| 1374 | if (value > 0x75) |
| 1375 | dimm_compatible_cas_latencies &= |
| 1376 | ~current_cas_latency; |
| 1377 | } |
| 1378 | // Can we support the next-highest CAS# latency (max - 1.0)? |
| 1379 | current_cas_latency >>= 1; |
| 1380 | if (current_cas_latency != 0) { |
| 1381 | value = |
| 1382 | spd_read_byte(dimm_socket_address, |
| 1383 | SPD_SDRAM_CYCLE_TIME_3RD); |
| 1384 | if (value < 0) |
| 1385 | goto hw_err; |
| 1386 | if (value > 0x75) |
| 1387 | dimm_compatible_cas_latencies &= |
| 1388 | ~current_cas_latency; |
| 1389 | } |
| 1390 | // Restrict the system to CAS# latencies compatible with this DIMM |
| 1391 | system_compatible_cas_latencies &= |
| 1392 | dimm_compatible_cas_latencies; |
| 1393 | |
| 1394 | /* go to the next DIMM */ |
| 1395 | } |
| 1396 | |
| 1397 | /* After all of the arduous calculation setup with the fastest |
| 1398 | * cas latency I can use. |
| 1399 | */ |
| 1400 | |
| 1401 | dram_timing = pci_read_config32(PCI_DEV(0, 0, 0), DRT); |
| 1402 | dram_timing &= ~(DRT_CAS_MASK); |
| 1403 | |
| 1404 | maybe_dram_read_timing = |
| 1405 | pci_read_config16(PCI_DEV(0, 0, 0), MAYBE_DRDCTL); |
| 1406 | maybe_dram_read_timing &= 0xF00C; |
| 1407 | |
| 1408 | if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_0) { |
| 1409 | dram_timing |= DRT_CAS_2_0; |
| 1410 | maybe_dram_read_timing |= 0xBB1; |
| 1411 | } else if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_5) { |
| 1412 | |
| 1413 | uint32_t dram_row_attributes = |
| 1414 | pci_read_config32(PCI_DEV(0, 0, 0), DRA); |
| 1415 | |
| 1416 | dram_timing |= DRT_CAS_2_5; |
| 1417 | |
| 1418 | // At CAS# 2.5, DRAM Read Timing (if that's what it its) appears to need a slightly |
| 1419 | // different value if all DIMM slots are populated |
| 1420 | |
| 1421 | if ((dram_row_attributes & 0xff) |
| 1422 | && (dram_row_attributes & 0xff00) |
| 1423 | && (dram_row_attributes & 0xff0000) |
| 1424 | && (dram_row_attributes & 0xff000000)) { |
| 1425 | |
| 1426 | // All slots populated |
| 1427 | maybe_dram_read_timing |= 0x0882; |
| 1428 | } else { |
| 1429 | // Some unpopulated slots |
| 1430 | maybe_dram_read_timing |= 0x0662; |
| 1431 | } |
| 1432 | } else |
| 1433 | die("No CAS# latencies compatible with all DIMMs!!\n"); |
| 1434 | |
| 1435 | pci_write_config32(PCI_DEV(0, 0, 0), DRT, dram_timing); |
| 1436 | |
| 1437 | /* set master DLL reset */ |
| 1438 | dword = pci_read_config32(PCI_DEV(0, 0, 0), 0x88); |
| 1439 | dword |= (1 << 26); |
| 1440 | pci_write_config32(PCI_DEV(0, 0, 0), 0x88, dword); |
| 1441 | |
| 1442 | dword &= 0x0c0007ff; /* patch try register 88 is undocumented tnz */ |
| 1443 | dword |= 0xd2109800; |
| 1444 | |
| 1445 | pci_write_config32(PCI_DEV(0, 0, 0), 0x88, dword); |
| 1446 | |
| 1447 | pci_write_config16(PCI_DEV(0, 0, 0), MAYBE_DRDCTL, |
| 1448 | maybe_dram_read_timing); |
| 1449 | |
| 1450 | dword = pci_read_config32(PCI_DEV(0, 0, 0), 0x88); /* reset master DLL reset */ |
| 1451 | dword &= ~(1 << 26); |
| 1452 | pci_write_config32(PCI_DEV(0, 0, 0), 0x88, dword); |
| 1453 | |
| 1454 | return; |
| 1455 | |
| 1456 | hw_err: |
| 1457 | die(SPD_ERROR); |
| 1458 | } |
| 1459 | |
| 1460 | /** |
| 1461 | * Configure the refresh interval so that we refresh no more often than |
| 1462 | * required by the "most needy" DIMM. Also disable ECC if any of the DIMMs |
| 1463 | * don't support it. |
| 1464 | * |
| 1465 | * @param ctrl PCI addresses of memory controller functions, and SMBus |
| 1466 | * addresses of DIMM slots on the mainboard. |
| 1467 | * @param dimm_mask Bitmask of populated DIMMs, spd_get_supported_dimms(). |
| 1468 | */ |
| 1469 | static void configure_e7501_dram_controller_mode(const struct |
| 1470 | mem_controller *ctrl, |
| 1471 | uint8_t dimm_mask) |
| 1472 | { |
| 1473 | int i; |
| 1474 | |
| 1475 | // Initial settings |
| 1476 | uint32_t controller_mode = |
| 1477 | pci_read_config32(PCI_DEV(0, 0, 0), DRC); |
| 1478 | uint32_t system_refresh_mode = (controller_mode >> 8) & 7; |
| 1479 | |
| 1480 | // Code below assumes that most aggressive settings are in |
| 1481 | // force when we are called, either via E7501 reset defaults |
| 1482 | // or by sdram_set_registers(): |
| 1483 | // - ECC enabled |
| 1484 | // - No refresh |
| 1485 | |
| 1486 | ASSERT((controller_mode & (3 << 20)) == (2 << 20)); // ECC |
| 1487 | ASSERT(!(controller_mode & (7 << 8))); // Refresh |
| 1488 | |
| 1489 | /* Walk through _all_ dimms and find the least-common denominator for: |
| 1490 | * - ECC support |
| 1491 | * - refresh rates |
| 1492 | */ |
| 1493 | |
| 1494 | for (i = 0; i < MAX_DIMM_SOCKETS; i++) { |
| 1495 | |
| 1496 | uint32_t dimm_refresh_mode; |
| 1497 | int value; |
| 1498 | uint16_t dimm_socket_address; |
| 1499 | |
| 1500 | if (!(dimm_mask & (1 << i))) { |
| 1501 | continue; // This DIMM not usable |
| 1502 | } |
| 1503 | |
| 1504 | if (i < MAX_DIMM_SOCKETS_PER_CHANNEL) |
| 1505 | dimm_socket_address = ctrl->channel0[i]; |
| 1506 | else |
| 1507 | dimm_socket_address = |
| 1508 | ctrl->channel1[i - |
| 1509 | MAX_DIMM_SOCKETS_PER_CHANNEL]; |
| 1510 | |
| 1511 | // Disable ECC mode if any one of the DIMMs does not support ECC |
| 1512 | // SJM: Should we just die here? E7501 datasheet says non-ECC DIMMs aren't supported. |
| 1513 | |
| 1514 | value = |
| 1515 | spd_read_byte(dimm_socket_address, |
| 1516 | SPD_DIMM_CONFIG_TYPE); |
| 1517 | die_on_spd_error(value); |
| 1518 | if (value != ERROR_SCHEME_ECC) { |
| 1519 | controller_mode &= ~(3 << 20); |
| 1520 | } |
| 1521 | |
| 1522 | value = spd_read_byte(dimm_socket_address, SPD_REFRESH); |
| 1523 | die_on_spd_error(value); |
| 1524 | value &= 0x7f; // Mask off self-refresh bit |
| 1525 | if (value > MAX_SPD_REFRESH_RATE) { |
| 1526 | print_err("unsupported refresh rate\n"); |
| 1527 | continue; |
| 1528 | } |
| 1529 | // Get the appropriate E7501 refresh mode for this DIMM |
| 1530 | dimm_refresh_mode = refresh_rate_map[value]; |
| 1531 | if (dimm_refresh_mode > 7) { |
| 1532 | print_err("unsupported refresh rate\n"); |
| 1533 | continue; |
| 1534 | } |
| 1535 | // If this DIMM requires more frequent refresh than others, |
| 1536 | // update the system setting |
| 1537 | if (refresh_frequency[dimm_refresh_mode] > |
| 1538 | refresh_frequency[system_refresh_mode]) |
| 1539 | system_refresh_mode = dimm_refresh_mode; |
| 1540 | |
| 1541 | #ifdef SUSPICIOUS_LOOKING_CODE |
| 1542 | // SJM NOTE: This code doesn't look right. SPD values are an order of magnitude smaller |
| 1543 | // than the clock period of the memory controller. Also, no other northbridge |
| 1544 | // looks at SPD_CMD_SIGNAL_INPUT_HOLD_TIME. |
| 1545 | |
| 1546 | // Switch to 2 clocks for address/command if required by any one of the DIMMs |
| 1547 | // NOTE: At 133 MHz, 1 clock == 7.52 ns |
| 1548 | value = |
| 1549 | spd_read_byte(dimm_socket_address, |
| 1550 | SPD_CMD_SIGNAL_INPUT_HOLD_TIME); |
| 1551 | die_on_spd_error(value); |
| 1552 | if (value >= 0xa0) { /* At 133MHz this constant should be 0x75 */ |
| 1553 | controller_mode &= ~(1 << 16); /* Use two clock cyles instead of one */ |
| 1554 | } |
| 1555 | #endif |
| 1556 | |
| 1557 | /* go to the next DIMM */ |
| 1558 | } |
| 1559 | |
| 1560 | controller_mode |= (system_refresh_mode << 8); |
| 1561 | |
| 1562 | // Configure the E7501 |
| 1563 | pci_write_config32(PCI_DEV(0, 0, 0), DRC, controller_mode); |
| 1564 | } |
| 1565 | |
| 1566 | /** |
| 1567 | * Configure the E7501's DRAM Row Attributes (DRA) registers based on DIMM |
| 1568 | * parameters read via SPD. This tells the controller the width of the SDRAM |
| 1569 | * chips on each DIMM side (x4 or x8) and the page size of each DIMM side |
| 1570 | * (4, 8, 16, or 32 KB). |
| 1571 | * |
| 1572 | * @param ctrl PCI addresses of memory controller functions, and SMBus |
| 1573 | * addresses of DIMM slots on the mainboard. |
| 1574 | * @param dimm_mask Bitmask of populated DIMMs, spd_get_supported_dimms(). |
| 1575 | */ |
| 1576 | static void configure_e7501_row_attributes(const struct mem_controller |
| 1577 | *ctrl, uint8_t dimm_mask) |
| 1578 | { |
| 1579 | int i; |
| 1580 | uint32_t row_attributes = 0; |
| 1581 | |
| 1582 | for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) { |
| 1583 | |
| 1584 | uint16_t dimm_socket_address = ctrl->channel0[i]; |
| 1585 | struct dimm_size page_size; |
| 1586 | struct dimm_size sdram_width; |
| 1587 | |
| 1588 | if (!(dimm_mask & (1 << i))) |
| 1589 | continue; // This DIMM not usable |
| 1590 | |
| 1591 | // Get the relevant parameters via SPD |
| 1592 | page_size = sdram_spd_get_page_size(dimm_socket_address); |
| 1593 | sdram_width = sdram_spd_get_width(dimm_socket_address); |
| 1594 | |
| 1595 | // Update the DRAM Row Attributes. |
| 1596 | // Page size is encoded as log2(page size in bits) - log2(8 Kb) |
| 1597 | // NOTE: 8 Kb = 2^13 |
| 1598 | row_attributes |= (page_size.side1 - 13) << (i << 3); // Side 1 of each DIMM is an EVEN row |
| 1599 | |
| 1600 | if (sdram_width.side2 > 0) |
| 1601 | row_attributes |= (page_size.side2 - 13) << ((i << 3) + 4); // Side 2 is ODD |
| 1602 | |
| 1603 | // Set x4 flags if appropriate |
| 1604 | if (sdram_width.side1 == 4) { |
| 1605 | row_attributes |= 0x08 << (i << 3); |
| 1606 | } |
| 1607 | |
| 1608 | if (sdram_width.side2 == 4) { |
| 1609 | row_attributes |= 0x08 << ((i << 3) + 4); |
| 1610 | } |
| 1611 | |
| 1612 | /* go to the next DIMM */ |
| 1613 | } |
| 1614 | |
| 1615 | /* Write the new row attributes register */ |
| 1616 | pci_write_config32(PCI_DEV(0, 0, 0), DRA, row_attributes); |
| 1617 | } |
| 1618 | |
| 1619 | /* |
| 1620 | * Enable clock signals for populated DIMM sockets and disable them for |
| 1621 | * unpopulated sockets (to reduce EMI). |
| 1622 | * |
| 1623 | * @param dimm_mask Bitmask of populated DIMMs, see spd_get_supported_dimms(). |
| 1624 | */ |
| 1625 | static void enable_e7501_clocks(uint8_t dimm_mask) |
| 1626 | { |
| 1627 | int i; |
| 1628 | uint8_t clock_disable = pci_read_config8(PCI_DEV(0, 0, 0), CKDIS); |
| 1629 | |
| 1630 | for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) { |
| 1631 | |
| 1632 | uint8_t socket_mask = 1 << i; |
| 1633 | |
| 1634 | if (dimm_mask & socket_mask) |
| 1635 | clock_disable &= ~socket_mask; // DIMM present, enable clock |
| 1636 | else |
| 1637 | clock_disable |= socket_mask; // DIMM absent, disable clock |
| 1638 | } |
| 1639 | |
| 1640 | pci_write_config8(PCI_DEV(0, 0, 0), CKDIS, clock_disable); |
| 1641 | } |
| 1642 | |
| 1643 | /* DIMM-dedependent configuration functions */ |
| 1644 | |
| 1645 | /** |
| 1646 | * DDR Receive FIFO RE-Sync (?) |
| 1647 | */ |
| 1648 | static void RAM_RESET_DDR_PTR(void) |
| 1649 | { |
| 1650 | uint8_t byte; |
| 1651 | byte = pci_read_config8(PCI_DEV(0, 0, 0), 0x88); |
| 1652 | byte |= (1 << 4); |
| 1653 | pci_write_config8(PCI_DEV(0, 0, 0), 0x88, byte); |
| 1654 | |
| 1655 | byte = pci_read_config8(PCI_DEV(0, 0, 0), 0x88); |
| 1656 | byte &= ~(1 << 4); |
| 1657 | pci_write_config8(PCI_DEV(0, 0, 0), 0x88, byte); |
| 1658 | } |
| 1659 | |
| 1660 | /** |
| 1661 | * Set E7501 registers that are either independent of DIMM specifics, or |
| 1662 | * establish default settings that will be overridden when we learn the |
| 1663 | * specifics. |
| 1664 | * |
| 1665 | * This sets PCI configuration registers to known good values based on the |
| 1666 | * table 'constant_register_values', which are a triple of configuration |
| 1667 | * register offset, mask, and bits to set. |
| 1668 | */ |
| 1669 | static void ram_set_d0f0_regs(void) |
| 1670 | { |
| 1671 | int i; |
| 1672 | int num_values = ARRAY_SIZE(constant_register_values); |
| 1673 | |
| 1674 | ASSERT((num_values % 3) == 0); // Bad table? |
| 1675 | |
| 1676 | for (i = 0; i < num_values; i += 3) { |
| 1677 | |
| 1678 | uint32_t register_offset = constant_register_values[i]; |
| 1679 | uint32_t bits_to_mask = constant_register_values[i + 1]; |
| 1680 | uint32_t bits_to_set = constant_register_values[i + 2]; |
| 1681 | uint32_t register_value; |
| 1682 | |
| 1683 | // It's theoretically possible to set values for something other than D0:F0, |
| 1684 | // but it's not typically done here |
| 1685 | ASSERT(!(register_offset & 0xFFFFFF00)); |
| 1686 | |
| 1687 | // bits_to_mask and bits_to_set should not reference the same bits |
| 1688 | // Again, not strictly an error, but flagged as a potential bug |
| 1689 | ASSERT((bits_to_mask & bits_to_set) == 0); |
| 1690 | |
| 1691 | register_value = |
| 1692 | pci_read_config32(PCI_DEV(0, 0, 0), register_offset); |
| 1693 | register_value &= bits_to_mask; |
| 1694 | register_value |= bits_to_set; |
| 1695 | |
| 1696 | pci_write_config32(PCI_DEV(0, 0, 0), register_offset, |
| 1697 | register_value); |
| 1698 | } |
| 1699 | } |
| 1700 | |
| 1701 | /** |
| 1702 | * Copy 64 bytes from one location to another. |
| 1703 | * |
| 1704 | * @param src_addr TODO |
| 1705 | * @param dst_addr TODO |
| 1706 | */ |
| 1707 | static void write_8dwords(const uint32_t *src_addr, uint32_t dst_addr) |
| 1708 | { |
| 1709 | int i; |
| 1710 | for (i = 0; i < 8; i++) { |
| 1711 | write32(dst_addr, *src_addr); |
| 1712 | src_addr++; |
| 1713 | dst_addr += sizeof(uint32_t); |
| 1714 | } |
| 1715 | } |
| 1716 | |
| 1717 | /** |
| 1718 | * Set the E7501's (undocumented) RCOMP registers. |
| 1719 | * |
| 1720 | * Per the 855PM datasheet and IXP2800 HW Initialization Reference Manual, |
| 1721 | * RCOMP registers appear to affect drive strength, pullup/pulldown offset, |
| 1722 | * and slew rate of various signal groups. |
| 1723 | * |
| 1724 | * Comments below are conjecture based on apparent similarity between the |
| 1725 | * E7501 and these two chips. |
| 1726 | */ |
| 1727 | static void ram_set_rcomp_regs(void) |
| 1728 | { |
| 1729 | uint32_t dword; |
| 1730 | uint8_t maybe_strength_control; |
| 1731 | |
| 1732 | RAM_DEBUG_MESSAGE("Setting RCOMP registers.\n"); |
| 1733 | |
| 1734 | /*enable access to the rcomp bar */ |
| 1735 | dword = pci_read_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST); |
| 1736 | dword |= (1 << 22); |
| 1737 | pci_write_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST, dword); |
| 1738 | |
| 1739 | // Set the RCOMP MMIO base address |
| 1740 | pci_write_config32(PCI_DEV(0, 0, 0), MAYBE_SMRBASE, RCOMP_MMIO); |
| 1741 | |
| 1742 | // Block RCOMP updates while we configure the registers |
| 1743 | dword = read32(RCOMP_MMIO + MAYBE_SMRCTL); |
| 1744 | dword |= (1 << 9); |
| 1745 | write32(RCOMP_MMIO + MAYBE_SMRCTL, dword); |
| 1746 | |
| 1747 | /* Begin to write the RCOMP registers */ |
| 1748 | |
| 1749 | // Set CMD and DQ/DQS strength to 2x (?) |
| 1750 | maybe_strength_control = read8(RCOMP_MMIO + MAYBE_DQCMDSTR) & 0x88; |
| 1751 | maybe_strength_control |= 0x44; |
| 1752 | write8(RCOMP_MMIO + MAYBE_DQCMDSTR, maybe_strength_control); |
| 1753 | |
| 1754 | write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0x80); |
| 1755 | write16(RCOMP_MMIO + 0x42, 0); |
| 1756 | |
| 1757 | write_8dwords(maybe_1x_slew_table, RCOMP_MMIO + 0x60); |
| 1758 | |
| 1759 | // NOTE: some factory BIOS set 0x9088 here. Seems to work either way. |
| 1760 | write16(RCOMP_MMIO + 0x40, 0); |
| 1761 | |
| 1762 | // Set RCVEnOut# strength to 2x (?) |
| 1763 | maybe_strength_control = read8(RCOMP_MMIO + MAYBE_RCVENSTR) & 0xF8; |
| 1764 | maybe_strength_control |= 4; |
| 1765 | write8(RCOMP_MMIO + MAYBE_RCVENSTR, maybe_strength_control); |
| 1766 | |
| 1767 | write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0x1c0); |
| 1768 | write16(RCOMP_MMIO + 0x50, 0); |
| 1769 | |
| 1770 | // Set CS# strength for x4 SDRAM to 2x (?) |
| 1771 | maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CSBSTR) & 0xF8; |
| 1772 | maybe_strength_control |= 4; |
| 1773 | write8(RCOMP_MMIO + MAYBE_CSBSTR, maybe_strength_control); |
| 1774 | |
| 1775 | write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0x140); |
| 1776 | write16(RCOMP_MMIO + 0x48, 0); |
| 1777 | |
| 1778 | // Set CKE strength for x4 SDRAM to 2x (?) |
| 1779 | maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CKESTR) & 0xF8; |
| 1780 | maybe_strength_control |= 4; |
| 1781 | write8(RCOMP_MMIO + MAYBE_CKESTR, maybe_strength_control); |
| 1782 | |
| 1783 | write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0xa0); |
| 1784 | write16(RCOMP_MMIO + 0x44, 0); |
| 1785 | |
| 1786 | // Set CK strength for x4 SDRAM to 1x (?) |
| 1787 | maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CKSTR) & 0xF8; |
| 1788 | maybe_strength_control |= 1; |
| 1789 | write8(RCOMP_MMIO + MAYBE_CKSTR, maybe_strength_control); |
| 1790 | |
| 1791 | write_8dwords(maybe_pull_updown_offset_table, RCOMP_MMIO + 0x180); |
| 1792 | write16(RCOMP_MMIO + 0x4c, 0); |
| 1793 | |
| 1794 | write8(RCOMP_MMIO + 0x2c, 0xff); |
| 1795 | |
| 1796 | // Set the digital filter length to 8 (?) |
| 1797 | dword = read32(RCOMP_MMIO + MAYBE_SMRCTL); |
| 1798 | |
| 1799 | // NOTE: Some factory BIOS don't do this. |
| 1800 | // Doesn't seem to matter either way. |
| 1801 | dword &= ~2; |
| 1802 | |
| 1803 | dword |= 1; |
| 1804 | write32(RCOMP_MMIO + MAYBE_SMRCTL, dword); |
| 1805 | |
| 1806 | /* Wait 40 usec */ |
| 1807 | SLOW_DOWN_IO; |
| 1808 | |
| 1809 | /* unblock updates */ |
| 1810 | dword = read32(RCOMP_MMIO + MAYBE_SMRCTL); |
| 1811 | dword &= ~(1 << 9); |
| 1812 | write32(RCOMP_MMIO + MAYBE_SMRCTL, dword); |
| 1813 | |
| 1814 | // Force a RCOMP measurement cycle? |
| 1815 | dword |= (1 << 8); |
| 1816 | write32(RCOMP_MMIO + MAYBE_SMRCTL, dword); |
| 1817 | dword &= ~(1 << 8); |
| 1818 | write32(RCOMP_MMIO + MAYBE_SMRCTL, dword); |
| 1819 | |
| 1820 | /* Wait 40 usec */ |
| 1821 | SLOW_DOWN_IO; |
| 1822 | |
| 1823 | /*disable access to the rcomp bar */ |
| 1824 | dword = pci_read_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST); |
| 1825 | dword &= ~(1 << 22); |
| 1826 | pci_write_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST, dword); |
| 1827 | |
| 1828 | } |
| 1829 | |
| 1830 | /*----------------------------------------------------------------------------- |
| 1831 | Public interface: |
| 1832 | -----------------------------------------------------------------------------*/ |
| 1833 | |
| 1834 | /** |
| 1835 | * Go through the JEDEC initialization sequence for all DIMMs, then enable |
| 1836 | * refresh and initialize ECC and memory to zero. Upon exit, SDRAM is up |
| 1837 | * and running. |
| 1838 | * |
| 1839 | * @param controllers Not used. |
| 1840 | * @param ctrl PCI addresses of memory controller functions, and SMBus |
| 1841 | * addresses of DIMM slots on the mainboard. |
| 1842 | */ |
| 1843 | static void sdram_enable(int controllers, |
| 1844 | const struct mem_controller *ctrl) |
| 1845 | { |
| 1846 | uint8_t dimm_mask = pci_read_config16(PCI_DEV(0, 0, 0), SKPD); |
| 1847 | uint32_t dram_controller_mode; |
| 1848 | |
| 1849 | if (dimm_mask == 0) |
| 1850 | return; |
| 1851 | |
| 1852 | /* 1 & 2 Power up and start clocks */ |
| 1853 | RAM_DEBUG_MESSAGE("Ram Enable 1\n"); |
| 1854 | RAM_DEBUG_MESSAGE("Ram Enable 2\n"); |
| 1855 | |
| 1856 | /* A 200us delay is needed */ |
| 1857 | DO_DELAY; EXTRA_DELAY; |
| 1858 | |
| 1859 | /* 3. Apply NOP */ |
| 1860 | RAM_DEBUG_MESSAGE("Ram Enable 3\n"); |
| 1861 | do_ram_command(RAM_COMMAND_NOP, 0); |
| 1862 | EXTRA_DELAY; |
| 1863 | |
| 1864 | /* 4 Precharge all */ |
| 1865 | RAM_DEBUG_MESSAGE("Ram Enable 4\n"); |
| 1866 | do_ram_command(RAM_COMMAND_PRECHARGE, 0); |
| 1867 | EXTRA_DELAY; |
| 1868 | /* wait until the all banks idle state... */ |
| 1869 | |
| 1870 | /* 5. Issue EMRS to enable DLL */ |
| 1871 | RAM_DEBUG_MESSAGE("Ram Enable 5\n"); |
| 1872 | do_ram_command(RAM_COMMAND_EMRS, |
| 1873 | SDRAM_EXTMODE_DLL_ENABLE | |
| 1874 | SDRAM_EXTMODE_DRIVE_NORMAL); |
| 1875 | EXTRA_DELAY; |
| 1876 | |
| 1877 | /* 6. Reset DLL */ |
| 1878 | RAM_DEBUG_MESSAGE("Ram Enable 6\n"); |
| 1879 | set_ram_mode(E7501_SDRAM_MODE | SDRAM_MODE_DLL_RESET); |
| 1880 | EXTRA_DELAY; |
| 1881 | /* Ensure a 200us delay between the DLL reset in step 6 and the final |
| 1882 | * mode register set in step 9. |
| 1883 | * Infineon needs this before any other command is sent to the ram. |
| 1884 | */ |
| 1885 | DO_DELAY; EXTRA_DELAY; |
| 1886 | |
| 1887 | /* 7 Precharge all */ |
| 1888 | RAM_DEBUG_MESSAGE("Ram Enable 7\n"); |
| 1889 | do_ram_command(RAM_COMMAND_PRECHARGE, 0); |
| 1890 | EXTRA_DELAY; |
| 1891 | |
| 1892 | /* 8 Now we need 2 AUTO REFRESH / CBR cycles to be performed */ |
| 1893 | RAM_DEBUG_MESSAGE("Ram Enable 8\n"); |
| 1894 | do_ram_command(RAM_COMMAND_CBR, 0); |
| 1895 | EXTRA_DELAY; |
| 1896 | do_ram_command(RAM_COMMAND_CBR, 0); |
| 1897 | EXTRA_DELAY; |
| 1898 | |
| 1899 | /* And for good luck 6 more CBRs */ |
| 1900 | do_ram_command(RAM_COMMAND_CBR, 0); |
| 1901 | EXTRA_DELAY; |
| 1902 | do_ram_command(RAM_COMMAND_CBR, 0); |
| 1903 | EXTRA_DELAY; |
| 1904 | do_ram_command(RAM_COMMAND_CBR, 0); |
| 1905 | EXTRA_DELAY; |
| 1906 | do_ram_command(RAM_COMMAND_CBR, 0); |
| 1907 | EXTRA_DELAY; |
| 1908 | do_ram_command(RAM_COMMAND_CBR, 0); |
| 1909 | EXTRA_DELAY; |
| 1910 | do_ram_command(RAM_COMMAND_CBR, 0); |
| 1911 | EXTRA_DELAY; |
| 1912 | |
| 1913 | /* 9 mode register set */ |
| 1914 | RAM_DEBUG_MESSAGE("Ram Enable 9\n"); |
| 1915 | set_ram_mode(E7501_SDRAM_MODE | SDRAM_MODE_NORMAL); |
| 1916 | EXTRA_DELAY; |
| 1917 | |
| 1918 | /* 10 DDR Receive FIFO RE-Sync */ |
| 1919 | RAM_DEBUG_MESSAGE("Ram Enable 10\n"); |
| 1920 | RAM_RESET_DDR_PTR(); |
| 1921 | EXTRA_DELAY; |
| 1922 | |
| 1923 | /* 11 normal operation */ |
| 1924 | RAM_DEBUG_MESSAGE("Ram Enable 11\n"); |
| 1925 | do_ram_command(RAM_COMMAND_NORMAL, 0); |
| 1926 | EXTRA_DELAY; |
| 1927 | |
| 1928 | // Reconfigure the row boundaries and Top of Low Memory |
| 1929 | // to match the true size of the DIMMs |
| 1930 | configure_e7501_ram_addresses(ctrl, dimm_mask); |
| 1931 | |
| 1932 | /* Finally enable refresh */ |
| 1933 | dram_controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC); |
| 1934 | dram_controller_mode |= (1 << 29); |
| 1935 | pci_write_config32(PCI_DEV(0, 0, 0), DRC, dram_controller_mode); |
| 1936 | EXTRA_DELAY; |
| 1937 | initialize_ecc(); |
| 1938 | |
| 1939 | dram_controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC); /* FCS_EN */ |
| 1940 | dram_controller_mode |= (1 << 17); // NOTE: undocumented reserved bit |
| 1941 | pci_write_config32(PCI_DEV(0, 0, 0), DRC, dram_controller_mode); |
| 1942 | |
| 1943 | RAM_DEBUG_MESSAGE("Northbridge following SDRAM init:\n"); |
| 1944 | DUMPNORTH(); |
| 1945 | } |
| 1946 | |
| 1947 | /** |
| 1948 | * Configure SDRAM controller parameters that depend on characteristics of the |
| 1949 | * DIMMs installed in the system. These characteristics are read from the |
| 1950 | * DIMMs via the standard Serial Presence Detect (SPD) interface. |
| 1951 | * |
| 1952 | * @param ctrl PCI addresses of memory controller functions, and SMBus |
| 1953 | * addresses of DIMM slots on the mainboard. |
| 1954 | */ |
| 1955 | static void sdram_set_spd_registers(const struct mem_controller *ctrl) |
| 1956 | { |
| 1957 | uint8_t dimm_mask; |
| 1958 | |
| 1959 | RAM_DEBUG_MESSAGE("Reading SPD data...\n"); |
| 1960 | |
| 1961 | dimm_mask = spd_get_supported_dimms(ctrl); |
| 1962 | |
| 1963 | if (dimm_mask == 0) { |
| 1964 | print_debug("No usable memory for this controller\n"); |
| 1965 | } else { |
| 1966 | enable_e7501_clocks(dimm_mask); |
| 1967 | |
| 1968 | RAM_DEBUG_MESSAGE("setting based on SPD data...\n"); |
| 1969 | |
| 1970 | configure_e7501_row_attributes(ctrl, dimm_mask); |
| 1971 | configure_e7501_dram_controller_mode(ctrl, dimm_mask); |
| 1972 | configure_e7501_cas_latency(ctrl, dimm_mask); |
| 1973 | RAM_RESET_DDR_PTR(); |
| 1974 | |
| 1975 | configure_e7501_dram_timing(ctrl, dimm_mask); |
| 1976 | DO_DELAY; |
| 1977 | RAM_DEBUG_MESSAGE("done\n"); |
| 1978 | } |
| 1979 | |
| 1980 | /* NOTE: configure_e7501_ram_addresses() is NOT called here. |
| 1981 | * We want to keep the default 64 MB/row mapping until sdram_enable() is called, |
| 1982 | * even though the default mapping is almost certainly incorrect. |
| 1983 | * The default mapping makes it easy to initialize all of the DIMMs |
| 1984 | * even if the total system memory is > 4 GB. |
| 1985 | * |
| 1986 | * Save the dimm_mask for when sdram_enable is called, so it can call |
| 1987 | * configure_e7501_ram_addresses() without having to regenerate the bitmask |
| 1988 | * of usable DIMMs. |
| 1989 | */ |
| 1990 | pci_write_config16(PCI_DEV(0, 0, 0), SKPD, dimm_mask); |
| 1991 | } |
| 1992 | |
| 1993 | /** |
| 1994 | * Do basic RAM setup that does NOT depend on serial presence detect |
| 1995 | * information (i.e. independent of DIMM specifics). |
| 1996 | * |
| 1997 | * @param ctrl PCI addresses of memory controller functions, and SMBus |
| 1998 | * addresses of DIMM slots on the mainboard. |
| 1999 | */ |
| 2000 | static void sdram_set_registers(const struct mem_controller *ctrl) |
| 2001 | { |
| 2002 | RAM_DEBUG_MESSAGE("Northbridge prior to SDRAM init:\n"); |
| 2003 | DUMPNORTH(); |
| 2004 | |
| 2005 | ram_set_rcomp_regs(); |
| 2006 | ram_set_d0f0_regs(); |
| 2007 | } |