Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 2 | |
| 3 | #ifndef __NORTHBRIDGE_INTEL_HASWELL_HASWELL_H__ |
Edward O'Callaghan | 089a510 | 2015-01-06 02:48:57 +1100 | [diff] [blame] | 4 | #define __NORTHBRIDGE_INTEL_HASWELL_HASWELL_H__ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 5 | |
| 6 | /* Chipset types */ |
| 7 | #define HASWELL_MOBILE 0 |
| 8 | #define HASWELL_DESKTOP 1 |
| 9 | #define HASWELL_SERVER 2 |
| 10 | |
Aaron Durbin | 8ce667e | 2013-02-15 21:45:06 -0600 | [diff] [blame] | 11 | /* Intel Enhanced Debug region */ |
| 12 | #define IED_SIZE CONFIG_IED_REGION_SIZE |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 13 | |
| 14 | /* Northbridge BARs */ |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 15 | #define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ |
| 16 | #define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ |
| 17 | #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 18 | |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 19 | #define GFXVT_BASE_ADDRESS 0xfed90000ULL |
| 20 | #define GFXVT_BASE_SIZE 0x1000 |
| 21 | |
| 22 | #define VTVC0_BASE_ADDRESS 0xfed91000ULL |
| 23 | #define VTVC0_BASE_SIZE 0x1000 |
| 24 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 25 | #include <southbridge/intel/lynxpoint/pch.h> |
| 26 | |
| 27 | /* Everything below this line is ignored in the DSDT */ |
| 28 | #ifndef __ACPI__ |
| 29 | |
| 30 | /* Device 0:0.0 PCI configuration space (Host Bridge) */ |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 31 | #define HOST_BRIDGE PCI_DEV(0, 0, 0) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 32 | |
| 33 | #define EPBAR 0x40 |
| 34 | #define MCHBAR 0x48 |
| 35 | #define PCIEXBAR 0x60 |
| 36 | #define DMIBAR 0x68 |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 37 | |
| 38 | #define GGC 0x50 /* GMCH Graphics Control */ |
Tristan Corrick | c5d367b | 2018-12-17 22:10:07 +1300 | [diff] [blame] | 39 | #define GGC_DISABLE_VGA_IO_DECODE (1 << 1) |
| 40 | #define GGC_IGD_MEM_IN_32MB_UNITS(x) (((x) & 0x1f) << 3) |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 41 | #define GGC_GTT_0MB (0 << 8) |
| 42 | #define GGC_GTT_1MB (1 << 8) |
| 43 | #define GGC_GTT_2MB (2 << 8) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 44 | |
| 45 | #define DEVEN 0x54 /* Device Enable */ |
Duncan Laurie | 0a7c49e | 2013-06-20 12:40:55 -0700 | [diff] [blame] | 46 | #define DEVEN_D7EN (1 << 14) |
| 47 | #define DEVEN_D4EN (1 << 7) |
| 48 | #define DEVEN_D3EN (1 << 5) |
| 49 | #define DEVEN_D2EN (1 << 4) |
| 50 | #define DEVEN_D1F0EN (1 << 3) |
| 51 | #define DEVEN_D1F1EN (1 << 2) |
| 52 | #define DEVEN_D1F2EN (1 << 1) |
| 53 | #define DEVEN_D0EN (1 << 0) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 54 | |
| 55 | #define PAM0 0x80 |
| 56 | #define PAM1 0x81 |
| 57 | #define PAM2 0x82 |
| 58 | #define PAM3 0x83 |
| 59 | #define PAM4 0x84 |
| 60 | #define PAM5 0x85 |
| 61 | #define PAM6 0x86 |
| 62 | |
| 63 | #define LAC 0x87 /* Legacy Access Control */ |
| 64 | #define SMRAM 0x88 /* System Management RAM Control */ |
| 65 | #define D_OPEN (1 << 6) |
| 66 | #define D_CLS (1 << 5) |
| 67 | #define D_LCK (1 << 4) |
| 68 | #define G_SMRAME (1 << 3) |
| 69 | #define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) |
| 70 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 71 | #define MESEG_BASE 0x70 /* Management Engine Base */ |
| 72 | #define MESEG_LIMIT 0x78 /* Management Engine Limit */ |
| 73 | #define REMAPBASE 0x90 /* Remap base */ |
| 74 | #define REMAPLIMIT 0x98 /* Remap limit */ |
| 75 | #define TOM 0xa0 /* Top of DRAM in memory controller space */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 76 | #define TOUUD 0xa8 /* Top of Upper Usable DRAM */ |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 77 | #define BDSM 0xb0 /* Base Data Stolen Memory */ |
| 78 | #define BGSM 0xb4 /* Base GTT Stolen Memory */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 79 | #define TSEG 0xb8 /* TSEG base */ |
| 80 | #define TOLUD 0xbc /* Top of Low Used Memory */ |
| 81 | |
| 82 | #define SKPAD 0xdc /* Scratchpad Data */ |
| 83 | |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 84 | #define CAPID0_A 0xe4 |
| 85 | #define VTD_DISABLE (1 << 23) |
| 86 | #define ARCHDIS 0xff0 /* DMA Remap Engine Policy Control */ |
| 87 | #define DMAR_LCKDN (1 << 31) |
| 88 | #define SPCAPCTRL (1 << 25) |
| 89 | #define L3HIT2PEND_DIS (1 << 20) |
| 90 | #define PRSCAPDIS (1 << 2) |
| 91 | #define GLBIOTLBINV (1 << 1) |
| 92 | #define GLBCTXTINV (1 << 0) |
| 93 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 94 | |
| 95 | /* Device 0:2.0 PCI configuration space (Graphics Device) */ |
| 96 | |
| 97 | #define MSAC 0x62 /* Multi Size Aperture Control */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 98 | |
| 99 | /* |
| 100 | * MCHBAR |
| 101 | */ |
| 102 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 103 | #define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) |
| 104 | #define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) |
| 105 | #define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) |
| 106 | #define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) |
| 107 | #define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) |
| 108 | #define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) |
| 109 | #define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or)) |
| 110 | #define MCHBAR16_OR(x, or) (MCHBAR16(x) = MCHBAR16(x) | (or)) |
| 111 | #define MCHBAR32_OR(x, or) (MCHBAR32(x) = MCHBAR32(x) | (or)) |
| 112 | #define MCHBAR8_AND_OR(x, and, or) (MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or)) |
| 113 | #define MCHBAR16_AND_OR(x, and, or) (MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or)) |
| 114 | #define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 115 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 116 | /* As there are many registers, define them on a separate file */ |
| 117 | #include "mchbar_regs.h" |
Duncan Laurie | c70353f | 2013-06-28 14:40:38 -0700 | [diff] [blame] | 118 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 119 | /* |
| 120 | * EPBAR - Egress Port Root Complex Register Block |
| 121 | */ |
| 122 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 123 | #define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + x)) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 124 | #define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + x)) |
| 125 | #define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + x)) |
| 126 | |
| 127 | #define EPPVCCAP1 0x004 /* 32bit */ |
| 128 | #define EPPVCCAP2 0x008 /* 32bit */ |
| 129 | |
| 130 | #define EPVC0RCAP 0x010 /* 32bit */ |
| 131 | #define EPVC0RCTL 0x014 /* 32bit */ |
| 132 | #define EPVC0RSTS 0x01a /* 16bit */ |
| 133 | |
| 134 | #define EPVC1RCAP 0x01c /* 32bit */ |
| 135 | #define EPVC1RCTL 0x020 /* 32bit */ |
| 136 | #define EPVC1RSTS 0x026 /* 16bit */ |
| 137 | |
| 138 | #define EPVC1MTS 0x028 /* 32bit */ |
| 139 | #define EPVC1IST 0x038 /* 64bit */ |
| 140 | |
| 141 | #define EPESD 0x044 /* 32bit */ |
| 142 | |
| 143 | #define EPLE1D 0x050 /* 32bit */ |
| 144 | #define EPLE1A 0x058 /* 64bit */ |
| 145 | #define EPLE2D 0x060 /* 32bit */ |
| 146 | #define EPLE2A 0x068 /* 64bit */ |
| 147 | |
| 148 | #define PORTARB 0x100 /* 256bit */ |
| 149 | |
| 150 | /* |
| 151 | * DMIBAR |
| 152 | */ |
| 153 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 154 | #define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + x)) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 155 | #define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + x)) |
| 156 | #define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + x)) |
| 157 | |
| 158 | #define DMIVCECH 0x000 /* 32bit */ |
| 159 | #define DMIPVCCAP1 0x004 /* 32bit */ |
| 160 | #define DMIPVCCAP2 0x008 /* 32bit */ |
| 161 | |
| 162 | #define DMIPVCCCTL 0x00c /* 16bit */ |
| 163 | |
| 164 | #define DMIVC0RCAP 0x010 /* 32bit */ |
| 165 | #define DMIVC0RCTL0 0x014 /* 32bit */ |
| 166 | #define DMIVC0RSTS 0x01a /* 16bit */ |
| 167 | |
| 168 | #define DMIVC1RCAP 0x01c /* 32bit */ |
| 169 | #define DMIVC1RCTL 0x020 /* 32bit */ |
| 170 | #define DMIVC1RSTS 0x026 /* 16bit */ |
| 171 | |
| 172 | #define DMILE1D 0x050 /* 32bit */ |
| 173 | #define DMILE1A 0x058 /* 64bit */ |
| 174 | #define DMILE2D 0x060 /* 32bit */ |
| 175 | #define DMILE2A 0x068 /* 64bit */ |
| 176 | |
| 177 | #define DMILCAP 0x084 /* 32bit */ |
| 178 | #define DMILCTL 0x088 /* 16bit */ |
| 179 | #define DMILSTS 0x08a /* 16bit */ |
| 180 | |
| 181 | #define DMICTL1 0x0f0 /* 32bit */ |
| 182 | #define DMICTL2 0x0fc /* 32bit */ |
| 183 | |
| 184 | #define DMICC 0x208 /* 32bit */ |
| 185 | |
| 186 | #define DMIDRCCFG 0xeb4 /* 32bit */ |
| 187 | |
| 188 | #ifndef __ASSEMBLER__ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 189 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 190 | void intel_northbridge_haswell_finalize_smm(void); |
Kyösti Mälkki | d7205be | 2019-09-27 07:24:17 +0300 | [diff] [blame] | 191 | |
Angel Pons | 73fa035 | 2020-07-03 12:29:03 +0200 | [diff] [blame] | 192 | void mb_late_romstage_setup(void); /* optional */ |
Angel Pons | 2e25ac6 | 2020-07-03 12:06:04 +0200 | [diff] [blame] | 193 | |
Angel Pons | e816829 | 2020-07-03 11:42:22 +0200 | [diff] [blame] | 194 | void haswell_early_initialization(void); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 195 | void haswell_late_initialization(void); |
Ronald G. Minnich | 4c8465c | 2013-09-30 15:57:21 -0700 | [diff] [blame] | 196 | void set_translation_table(int start, int end, u64 base, int inc); |
Tristan Corrick | 334be32 | 2018-12-17 22:10:21 +1300 | [diff] [blame] | 197 | void haswell_unhide_peg(void); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 198 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 199 | void report_platform_info(void); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 200 | |
Matt DeVillier | 85d98d9 | 2018-03-04 01:41:23 -0600 | [diff] [blame] | 201 | #include <device/device.h> |
| 202 | |
| 203 | struct acpi_rsdp; |
Furquan Shaikh | 0f007d8 | 2020-04-24 06:41:18 -0700 | [diff] [blame] | 204 | unsigned long northbridge_write_acpi_tables(const struct device *device, unsigned long start, |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 205 | struct acpi_rsdp *rsdp); |
Matt DeVillier | 85d98d9 | 2018-03-04 01:41:23 -0600 | [diff] [blame] | 206 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 207 | #endif /* __ASSEMBLER__ */ |
| 208 | #endif /* __ACPI__ */ |
Edward O'Callaghan | 089a510 | 2015-01-06 02:48:57 +1100 | [diff] [blame] | 209 | #endif /* __NORTHBRIDGE_INTEL_HASWELL_HASWELL_H__ */ |