Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
Paul Menzel | a46a712 | 2013-02-23 18:37:27 +0100 | [diff] [blame] | 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 18 | */ |
| 19 | |
| 20 | #include <console/console.h> |
Kyösti Mälkki | ab56b3b | 2013-11-28 16:44:51 +0200 | [diff] [blame] | 21 | #include <bootmode.h> |
Patrick Georgi | 6444bd4 | 2012-07-06 11:31:39 +0200 | [diff] [blame] | 22 | #include <delay.h> |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 23 | #include <device/device.h> |
| 24 | #include <device/pci.h> |
| 25 | #include <device/pci_ids.h> |
Sven Schnelle | b629d14 | 2011-06-12 14:30:10 +0200 | [diff] [blame] | 26 | #include <pc80/mc146818rtc.h> |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 27 | #include <edid.h> |
| 28 | #include <drivers/intel/gma/edid.h> |
| 29 | #include <drivers/intel/gma/i915.h> |
| 30 | #include <string.h> |
Vladimir Serbinenko | 0092c99 | 2014-08-21 01:06:53 +0200 | [diff] [blame] | 31 | #include <pc80/vga.h> |
| 32 | #include <pc80/vga_io.h> |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 33 | |
Patrick Georgi | ce6e9fe | 2012-07-20 12:37:06 +0200 | [diff] [blame] | 34 | #include "i945.h" |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 35 | #include "chip.h" |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 36 | |
Patrick Georgi | 6444bd4 | 2012-07-06 11:31:39 +0200 | [diff] [blame] | 37 | #define GDRST 0xc0 |
| 38 | |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 39 | #define LVDS_CLOCK_A_POWERUP_ALL (3 << 8) |
| 40 | #define LVDS_CLOCK_B_POWERUP_ALL (3 << 4) |
| 41 | #define LVDS_CLOCK_BOTH_POWERUP_ALL (3 << 2) |
| 42 | #define DISPPLANE_BGRX888 (0x6<<26) |
| 43 | #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ |
| 44 | |
| 45 | #define DPLL_INTEGRATED_CRI_CLK_VLV (1<<14) |
| 46 | |
| 47 | #define PGETBL_CTL 0x2020 |
| 48 | #define PGETBL_ENABLED 0x00000001 |
| 49 | |
| 50 | #define BASE_FREQUENCY 120000 |
| 51 | |
| 52 | #if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT |
| 53 | |
| 54 | static int gtt_setup(unsigned int mmiobase) |
| 55 | { |
| 56 | unsigned long PGETBL_save; |
Paul Menzel | cc95f18 | 2014-06-05 22:45:35 +0200 | [diff] [blame] | 57 | unsigned long tom; // top of memory |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 58 | |
Paul Menzel | cc95f18 | 2014-06-05 22:45:35 +0200 | [diff] [blame] | 59 | /* |
| 60 | * The Video BIOS places the GTT right below top of memory. |
| 61 | * |
| 62 | * It is not documented in the Intel 945 datasheet, but the Intel |
| 63 | * developers said that it is normally placed there. |
| 64 | * |
| 65 | * TODO: Add option to make the GTT size runtime configurable |
| 66 | */ |
| 67 | tom = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), TOLUD) << 24; |
| 68 | PGETBL_save = tom - 256 * KiB; |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 69 | PGETBL_save |= PGETBL_ENABLED; |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 70 | PGETBL_save |= 2; /* set GTT to 256kb */ |
| 71 | |
| 72 | write32(mmiobase + GFX_FLSH_CNTL, 0); |
| 73 | |
| 74 | write32(mmiobase + PGETBL_CTL, PGETBL_save); |
| 75 | |
| 76 | /* verify */ |
| 77 | if (read32(mmiobase + PGETBL_CTL) & PGETBL_ENABLED) { |
| 78 | printk(BIOS_DEBUG, "gtt_setup is enabled.\n"); |
| 79 | } else { |
| 80 | printk(BIOS_DEBUG, "gtt_setup failed!!!\n"); |
| 81 | return 1; |
| 82 | } |
| 83 | write32(mmiobase + GFX_FLSH_CNTL, 0); |
| 84 | |
| 85 | return 0; |
| 86 | } |
| 87 | |
| 88 | static int intel_gma_init(struct northbridge_intel_i945_config *conf, |
| 89 | unsigned int pphysbase, unsigned int piobase, |
| 90 | unsigned int pmmio, unsigned int pgfx) |
| 91 | { |
| 92 | struct edid edid; |
| 93 | u8 edid_data[128]; |
| 94 | unsigned long temp; |
| 95 | int hpolarity, vpolarity; |
| 96 | u32 candp1, candn; |
| 97 | u32 best_delta = 0xffffffff; |
| 98 | u32 target_frequency; |
| 99 | u32 pixel_p1 = 1; |
| 100 | u32 pixel_n = 1; |
| 101 | u32 pixel_m1 = 1; |
| 102 | u32 pixel_m2 = 1; |
| 103 | u32 hactive, vactive, right_border, bottom_border; |
| 104 | u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch; |
| 105 | u32 i, j; |
| 106 | u32 uma_size; |
| 107 | u16 reg16; |
| 108 | |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 109 | printk(BIOS_SPEW, |
| 110 | "i915lightup: graphics %p mmio %08x addrport %04x physbase %08x\n", |
| 111 | (void *)pgfx, pmmio, piobase, pphysbase); |
| 112 | |
| 113 | intel_gmbus_read_edid(pmmio + GMBUS0, 3, 0x50, edid_data, 128); |
| 114 | decode_edid(edid_data, sizeof(edid_data), &edid); |
| 115 | |
| 116 | hpolarity = (edid.phsync == '-'); |
| 117 | vpolarity = (edid.pvsync == '-'); |
| 118 | hactive = edid.x_resolution; |
| 119 | vactive = edid.y_resolution; |
| 120 | right_border = edid.hborder; |
| 121 | bottom_border = edid.vborder; |
| 122 | vblank = edid.vbl; |
| 123 | hblank = edid.hbl; |
| 124 | vsync = edid.vspw; |
| 125 | hsync = edid.hspw; |
| 126 | hfront_porch = edid.hso; |
| 127 | vfront_porch = edid.vso; |
| 128 | |
| 129 | for (i = 0; i < 2; i++) |
| 130 | for (j = 0; j < 0x100; j++) |
| 131 | /* R=j, G=j, B=j. */ |
| 132 | write32(pmmio + PALETTE(i) + 4 * j, 0x10101 * j); |
| 133 | |
| 134 | write32(pmmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS |
| 135 | | (read32(pmmio + PCH_PP_CONTROL) & ~PANEL_UNLOCK_MASK)); |
| 136 | |
| 137 | write32(pmmio + MI_ARB_STATE, MI_ARB_C3_LP_WRITE_ENABLE | (1 << 27)); |
| 138 | /* Clean registers. */ |
| 139 | for (i = 0; i < 0x20; i += 4) |
| 140 | write32(pmmio + RENDER_RING_BASE + i, 0); |
| 141 | for (i = 0; i < 0x20; i += 4) |
| 142 | write32(pmmio + FENCE_REG_965_0 + i, 0); |
| 143 | write32(pmmio + PP_ON_DELAYS, 0); |
| 144 | write32(pmmio + PP_OFF_DELAYS, 0); |
| 145 | |
| 146 | /* Disable VGA. */ |
| 147 | write32(pmmio + VGACNTRL, VGA_DISP_DISABLE); |
| 148 | |
| 149 | /* Disable pipes. */ |
| 150 | write32(pmmio + PIPECONF(0), 0); |
| 151 | write32(pmmio + PIPECONF(1), 0); |
| 152 | |
| 153 | /* Init PRB0. */ |
| 154 | write32(pmmio + HWS_PGA, 0x352d2000); |
| 155 | write32(pmmio + PRB0_CTL, 0); |
| 156 | write32(pmmio + PRB0_HEAD, 0); |
| 157 | write32(pmmio + PRB0_TAIL, 0); |
| 158 | write32(pmmio + PRB0_START, 0); |
| 159 | write32(pmmio + PRB0_CTL, 0x0001f001); |
| 160 | |
| 161 | write32(pmmio + D_STATE, DSTATE_PLL_D3_OFF |
| 162 | | DSTATE_GFX_CLOCK_GATING | DSTATE_DOT_CLOCK_GATING); |
| 163 | write32(pmmio + ECOSKPD, 0x00010000); |
| 164 | write32(pmmio + HWSTAM, 0xeffe); |
| 165 | write32(pmmio + PORT_HOTPLUG_EN, conf->gpu_hotplug); |
| 166 | write32(pmmio + INSTPM, 0x08000000 | INSTPM_AGPBUSY_DIS); |
| 167 | |
| 168 | target_frequency = conf->gpu_lvds_is_dual_channel ? edid.pixel_clock |
| 169 | : (2 * edid.pixel_clock); |
| 170 | |
| 171 | /* Find suitable divisors. */ |
| 172 | for (candp1 = 1; candp1 <= 8; candp1++) { |
| 173 | for (candn = 5; candn <= 10; candn++) { |
| 174 | u32 cur_frequency; |
| 175 | u32 m; /* 77 - 131. */ |
| 176 | u32 denom; /* 35 - 560. */ |
| 177 | u32 current_delta; |
| 178 | |
| 179 | denom = candn * candp1 * 7; |
| 180 | /* Doesnt overflow for up to |
| 181 | 5000000 kHz = 5 GHz. */ |
| 182 | m = (target_frequency * denom |
| 183 | + BASE_FREQUENCY / 2) / BASE_FREQUENCY; |
| 184 | |
| 185 | if (m < 77 || m > 131) |
| 186 | continue; |
| 187 | |
| 188 | cur_frequency = (BASE_FREQUENCY * m) / denom; |
| 189 | if (target_frequency > cur_frequency) |
| 190 | current_delta = target_frequency - cur_frequency; |
| 191 | else |
| 192 | current_delta = cur_frequency - target_frequency; |
| 193 | |
| 194 | if (best_delta > current_delta) { |
| 195 | best_delta = current_delta; |
| 196 | pixel_n = candn; |
| 197 | pixel_p1 = candp1; |
| 198 | pixel_m2 = ((m + 3) % 5) + 7; |
| 199 | pixel_m1 = (m - pixel_m2) / 5; |
| 200 | } |
| 201 | } |
| 202 | } |
| 203 | |
| 204 | if (best_delta == 0xffffffff) { |
| 205 | printk (BIOS_ERR, "Couldn't find GFX clock divisors\n"); |
| 206 | return -1; |
| 207 | } |
| 208 | |
| 209 | printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", |
| 210 | hactive, vactive); |
| 211 | printk(BIOS_DEBUG, "Borders %d x %d\n", right_border, bottom_border); |
| 212 | printk(BIOS_DEBUG, "Blank %d x %d\n", hblank, vblank); |
| 213 | printk(BIOS_DEBUG, "Sync %d x %d\n", hsync, vsync); |
| 214 | printk(BIOS_DEBUG, "Front porch %d x %d\n", hfront_porch, vfront_porch); |
| 215 | printk(BIOS_DEBUG, (conf->gpu_lvds_use_spread_spectrum_clock |
| 216 | ? "Spread spectrum clock\n" |
| 217 | : "DREF clock\n")); |
| 218 | printk(BIOS_DEBUG, (conf->gpu_lvds_is_dual_channel |
| 219 | ? "Dual channel\n" |
| 220 | : "Single channel\n")); |
| 221 | printk(BIOS_DEBUG, "Polarities %d, %d\n", |
| 222 | hpolarity, vpolarity); |
| 223 | printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", |
| 224 | pixel_n, pixel_m1, pixel_m2, pixel_p1); |
| 225 | printk(BIOS_DEBUG, "Pixel clock %d kHz\n", |
| 226 | BASE_FREQUENCY * (5 * pixel_m1 + pixel_m2) / pixel_n |
| 227 | / (pixel_p1 * 7)); |
| 228 | |
Vladimir Serbinenko | 0092c99 | 2014-08-21 01:06:53 +0200 | [diff] [blame] | 229 | #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) |
| 230 | write32(pmmio + PF_WIN_SZ(0), vactive | (hactive << 16)); |
| 231 | write32(pmmio + PF_WIN_POS(0), 0); |
| 232 | write32(pmmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3); |
| 233 | write32(pmmio + PFIT_CONTROL, PFIT_ENABLE | (1 << PFIT_PIPE_SHIFT) | HORIZ_AUTO_SCALE | VERT_AUTO_SCALE); |
| 234 | #else |
| 235 | /* Disable panel fitter (we're in native resolution). */ |
| 236 | write32(pmmio + PF_CTL(0), 0); |
| 237 | write32(pmmio + PF_WIN_SZ(0), 0); |
| 238 | write32(pmmio + PF_WIN_POS(0), 0); |
| 239 | write32(pmmio + PFIT_PGM_RATIOS, 0); |
| 240 | write32(pmmio + PFIT_CONTROL, 0); |
| 241 | #endif |
| 242 | |
| 243 | mdelay(1); |
| 244 | |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 245 | write32(pmmio + DSPCNTR(0), DISPPLANE_BGRX888 |
| 246 | | DISPPLANE_SEL_PIPE_B | DISPPLANE_GAMMA_ENABLE); |
| 247 | |
| 248 | mdelay(1); |
| 249 | write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS |
| 250 | | (read32(pmmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK)); |
| 251 | write32(pmmio + FP0(1), |
| 252 | ((pixel_n - 2) << 16) |
| 253 | | ((pixel_m1 - 2) << 8) | pixel_m2); |
| 254 | write32(pmmio + DPLL(1), |
| 255 | DPLL_VGA_MODE_DIS | |
| 256 | DPLL_VCO_ENABLE | DPLLB_MODE_LVDS |
| 257 | | (conf->gpu_lvds_is_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 |
| 258 | : DPLLB_LVDS_P2_CLOCK_DIV_14) |
| 259 | | (conf->gpu_lvds_use_spread_spectrum_clock |
| 260 | ? DPLL_INTEGRATED_CLOCK_VLV | DPLL_INTEGRATED_CRI_CLK_VLV |
| 261 | : 0) |
| 262 | | (pixel_p1 << 16) |
| 263 | | (pixel_p1)); |
| 264 | mdelay(1); |
| 265 | write32(pmmio + DPLL(1), |
| 266 | DPLL_VGA_MODE_DIS | |
| 267 | DPLL_VCO_ENABLE | DPLLB_MODE_LVDS |
| 268 | | (conf->gpu_lvds_is_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 |
| 269 | : DPLLB_LVDS_P2_CLOCK_DIV_14) |
| 270 | | ((conf->gpu_lvds_use_spread_spectrum_clock ? 3 : 0) << 13) |
| 271 | | (pixel_p1 << 16) |
| 272 | | (pixel_p1)); |
| 273 | mdelay(1); |
| 274 | write32(pmmio + HTOTAL(1), |
| 275 | ((hactive + right_border + hblank - 1) << 16) |
| 276 | | (hactive - 1)); |
| 277 | write32(pmmio + HBLANK(1), |
| 278 | ((hactive + right_border + hblank - 1) << 16) |
| 279 | | (hactive + right_border - 1)); |
| 280 | write32(pmmio + HSYNC(1), |
| 281 | ((hactive + right_border + hfront_porch + hsync - 1) << 16) |
| 282 | | (hactive + right_border + hfront_porch - 1)); |
| 283 | |
| 284 | write32(pmmio + VTOTAL(1), ((vactive + bottom_border + vblank - 1) << 16) |
| 285 | | (vactive - 1)); |
| 286 | write32(pmmio + VBLANK(1), ((vactive + bottom_border + vblank - 1) << 16) |
| 287 | | (vactive + bottom_border - 1)); |
| 288 | write32(pmmio + VSYNC(1), |
| 289 | (vactive + bottom_border + vfront_porch + vsync - 1) |
| 290 | | (vactive + bottom_border + vfront_porch - 1)); |
| 291 | |
Vladimir Serbinenko | 0092c99 | 2014-08-21 01:06:53 +0200 | [diff] [blame] | 292 | #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) |
| 293 | write32(pmmio + PIPESRC(1), (639 << 16) | 399); |
| 294 | #else |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 295 | write32(pmmio + PIPESRC(1), ((hactive - 1) << 16) | (vactive - 1)); |
Vladimir Serbinenko | 0092c99 | 2014-08-21 01:06:53 +0200 | [diff] [blame] | 296 | #endif |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 297 | mdelay(1); |
| 298 | |
| 299 | write32(pmmio + DSPSIZE(0), (hactive - 1) | ((vactive - 1) << 16)); |
| 300 | write32(pmmio + DSPPOS(0), 0); |
| 301 | |
| 302 | /* Backlight init. */ |
| 303 | write32(pmmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK); |
| 304 | write32(pmmio + FW_BLC, 0x011d011a); |
| 305 | write32(pmmio + FW_BLC2, 0x00000102); |
| 306 | write32(pmmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK); |
| 307 | write32(pmmio + FW_BLC_SELF, 0x0001003f); |
| 308 | write32(pmmio + FW_BLC, 0x011d0109); |
| 309 | write32(pmmio + FW_BLC2, 0x00000102); |
| 310 | write32(pmmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK); |
| 311 | write32(pmmio + BLC_PWM_CTL, conf->gpu_backlight); |
| 312 | |
| 313 | edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; |
| 314 | write32(pmmio + DSPADDR(0), 0); |
| 315 | write32(pmmio + DSPSURF(0), 0); |
| 316 | write32(pmmio + DSPSTRIDE(0), edid.bytes_per_line); |
| 317 | write32(pmmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888 |
| 318 | | DISPPLANE_SEL_PIPE_B | DISPPLANE_GAMMA_ENABLE); |
| 319 | mdelay(1); |
| 320 | |
| 321 | write32(pmmio + PIPECONF(1), PIPECONF_ENABLE); |
| 322 | write32(pmmio + LVDS, LVDS_ON |
| 323 | | (hpolarity << 20) | (vpolarity << 21) |
| 324 | | (conf->gpu_lvds_is_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL |
| 325 | | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) |
| 326 | | LVDS_CLOCK_A_POWERUP_ALL |
| 327 | | LVDS_PIPE(1)); |
| 328 | |
| 329 | write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); |
| 330 | write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_RESET); |
| 331 | mdelay(1); |
| 332 | write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS |
| 333 | | PANEL_POWER_ON | PANEL_POWER_RESET); |
| 334 | |
| 335 | printk (BIOS_DEBUG, "waiting for panel powerup\n"); |
| 336 | while (1) { |
| 337 | u32 reg32; |
| 338 | reg32 = read32(pmmio + PP_STATUS); |
| 339 | if ((reg32 & PP_SEQUENCE_MASK) == PP_SEQUENCE_NONE) |
| 340 | break; |
| 341 | } |
| 342 | printk (BIOS_DEBUG, "panel powered up\n"); |
| 343 | |
| 344 | write32(pmmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); |
| 345 | |
| 346 | /* Clear interrupts. */ |
| 347 | write32(pmmio + DEIIR, 0xffffffff); |
| 348 | write32(pmmio + SDEIIR, 0xffffffff); |
| 349 | write32(pmmio + IIR, 0xffffffff); |
| 350 | write32(pmmio + IMR, 0xffffffff); |
| 351 | write32(pmmio + EIR, 0xffffffff); |
| 352 | |
| 353 | if (gtt_setup(pmmio)) { |
| 354 | printk(BIOS_ERR, "ERROR: GTT Setup Failed!!!\n"); |
| 355 | return 0; |
| 356 | } |
| 357 | |
| 358 | /* Setup GTT. */ |
| 359 | |
| 360 | reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC); |
| 361 | uma_size = 0; |
| 362 | if (!(reg16 & 2)) { |
| 363 | reg16 >>= 4; |
| 364 | reg16 &= 7; |
| 365 | switch (reg16) { |
| 366 | case 1: |
| 367 | uma_size = 1024; |
| 368 | break; |
| 369 | case 3: |
| 370 | uma_size = 8192; |
| 371 | break; |
| 372 | } |
| 373 | |
| 374 | printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10); |
| 375 | } |
| 376 | |
Vladimir Serbinenko | 055fe03 | 2014-08-19 23:59:27 +0200 | [diff] [blame] | 377 | for (i = 0; i < (uma_size - 256) / 4; i++) |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 378 | { |
| 379 | outl((i << 2) | 1, piobase); |
| 380 | outl(pphysbase + (i << 12) + 1, piobase + 4); |
| 381 | } |
| 382 | |
| 383 | temp = read32(pmmio + PGETBL_CTL); |
| 384 | printk(BIOS_INFO, "GTT PGETBL_CTL register: 0x%lx\n", temp); |
| 385 | |
| 386 | if (temp & 1) |
| 387 | printk(BIOS_INFO, "GTT Enabled\n"); |
| 388 | else |
| 389 | printk(BIOS_ERR, "ERROR: GTT is still Disabled!!!\n"); |
| 390 | |
Vladimir Serbinenko | 0092c99 | 2014-08-21 01:06:53 +0200 | [diff] [blame] | 391 | #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) |
| 392 | vga_misc_write(0x67); |
| 393 | |
| 394 | write32(pmmio + DSPCNTR(0), DISPPLANE_SEL_PIPE_B); |
| 395 | |
| 396 | write32(pmmio + VGACNTRL, 0x02c4008e | VGA_PIPE_B_SELECT); |
| 397 | |
| 398 | vga_textmode_init(); |
| 399 | #else |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 400 | printk(BIOS_SPEW, "memset %p to 0x00 for %d bytes\n", |
| 401 | (void *)pgfx, hactive * vactive * 4); |
| 402 | memset((void *)pgfx, 0x00, hactive * vactive * 4); |
| 403 | |
| 404 | set_vbe_mode_info_valid(&edid, pgfx); |
Vladimir Serbinenko | 0092c99 | 2014-08-21 01:06:53 +0200 | [diff] [blame] | 405 | #endif |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 406 | return 0; |
| 407 | } |
| 408 | #endif |
| 409 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 410 | static void gma_func0_init(struct device *dev) |
| 411 | { |
| 412 | u32 reg32; |
| 413 | |
Patrick Georgi | 6444bd4 | 2012-07-06 11:31:39 +0200 | [diff] [blame] | 414 | /* Unconditionally reset graphics */ |
| 415 | pci_write_config8(dev, GDRST, 1); |
| 416 | udelay(50); |
| 417 | pci_write_config8(dev, GDRST, 0); |
| 418 | /* wait for device to finish */ |
| 419 | while (pci_read_config8(dev, GDRST) & 1) { }; |
| 420 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 421 | /* IGD needs to be Bus Master */ |
| 422 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 423 | pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER |
| 424 | | PCI_COMMAND_IO | PCI_COMMAND_MEMORY); |
Denis 'GNUtoo' Carikli | ed7e29e | 2013-02-24 12:01:44 +0100 | [diff] [blame] | 425 | |
| 426 | #if !CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT |
| 427 | /* PCI Init, will run VBIOS */ |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 428 | pci_dev_init(dev); |
Denis 'GNUtoo' Carikli | ed7e29e | 2013-02-24 12:01:44 +0100 | [diff] [blame] | 429 | #endif |
| 430 | |
| 431 | |
| 432 | #if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT |
| 433 | /* This should probably run before post VBIOS init. */ |
| 434 | printk(BIOS_SPEW, "Initializing VGA without OPROM.\n"); |
Peter Stuge | 03e4ac6 | 2013-06-08 01:25:43 +0200 | [diff] [blame] | 435 | u32 iobase, mmiobase, graphics_base; |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 436 | struct northbridge_intel_i945_config *conf = dev->chip_info; |
| 437 | |
Denis 'GNUtoo' Carikli | ed7e29e | 2013-02-24 12:01:44 +0100 | [diff] [blame] | 438 | iobase = dev->resource_list[1].base; |
| 439 | mmiobase = dev->resource_list[0].base; |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 440 | graphics_base = dev->resource_list[2].base; |
Denis 'GNUtoo' Carikli | ed7e29e | 2013-02-24 12:01:44 +0100 | [diff] [blame] | 441 | |
Peter Stuge | c6f0997 | 2013-06-08 01:31:44 +0200 | [diff] [blame] | 442 | printk(BIOS_SPEW, "GMADR=0x%08x GTTADR=0x%08x\n", |
Paul Menzel | d235da1 | 2014-06-03 00:15:30 +0200 | [diff] [blame] | 443 | pci_read_config32(dev, GMADR), |
| 444 | pci_read_config32(dev, GTTADR) |
Peter Stuge | c6f0997 | 2013-06-08 01:31:44 +0200 | [diff] [blame] | 445 | ); |
| 446 | |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 447 | int err; |
| 448 | err = intel_gma_init(conf, pci_read_config32(dev, 0x5c) & ~0xf, |
| 449 | iobase, mmiobase, graphics_base); |
| 450 | if (err == 0) |
Kyösti Mälkki | ab56b3b | 2013-11-28 16:44:51 +0200 | [diff] [blame] | 451 | gfx_set_init_done(1); |
Denis 'GNUtoo' Carikli | ed7e29e | 2013-02-24 12:01:44 +0100 | [diff] [blame] | 452 | #endif |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 453 | } |
| 454 | |
Patrick Georgi | ce6e9fe | 2012-07-20 12:37:06 +0200 | [diff] [blame] | 455 | /* This doesn't reclaim stolen UMA memory, but IGD could still |
| 456 | be reenabled later. */ |
| 457 | static void gma_func0_disable(struct device *dev) |
| 458 | { |
| 459 | struct device *dev_host = dev_find_slot(0, PCI_DEVFN(0x0, 0)); |
| 460 | |
| 461 | pci_write_config16(dev, GCFC, 0xa00); |
| 462 | pci_write_config16(dev_host, GGC, (1 << 1)); |
| 463 | |
| 464 | unsigned int reg32 = pci_read_config32(dev_host, DEVEN); |
| 465 | reg32 &= ~(DEVEN_D2F0 | DEVEN_D2F1); |
| 466 | pci_write_config32(dev_host, DEVEN, reg32); |
| 467 | |
| 468 | dev->enabled = 0; |
| 469 | } |
| 470 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 471 | static void gma_func1_init(struct device *dev) |
| 472 | { |
| 473 | u32 reg32; |
Sven Schnelle | b629d14 | 2011-06-12 14:30:10 +0200 | [diff] [blame] | 474 | u8 val; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 475 | |
| 476 | /* IGD needs to be Bus Master, also enable IO accesss */ |
| 477 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
Stefan Reinauer | 109ab31 | 2009-08-12 16:08:05 +0000 | [diff] [blame] | 478 | pci_write_config32(dev, PCI_COMMAND, reg32 | |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 479 | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); |
Sven Schnelle | b629d14 | 2011-06-12 14:30:10 +0200 | [diff] [blame] | 480 | |
Alexandru Gagniuc | 72dccce | 2013-11-23 19:22:53 -0600 | [diff] [blame] | 481 | if (get_option(&val, "tft_brightness") == CB_SUCCESS) |
Sven Schnelle | b629d14 | 2011-06-12 14:30:10 +0200 | [diff] [blame] | 482 | pci_write_config8(dev, 0xf4, val); |
| 483 | else |
| 484 | pci_write_config8(dev, 0xf4, 0xff); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 485 | } |
| 486 | |
| 487 | static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) |
| 488 | { |
| 489 | if (!vendor || !device) { |
| 490 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 491 | pci_read_config32(dev, PCI_VENDOR_ID)); |
| 492 | } else { |
| 493 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 494 | ((device & 0xffff) << 16) | (vendor & 0xffff)); |
| 495 | } |
| 496 | } |
| 497 | |
| 498 | static struct pci_operations gma_pci_ops = { |
| 499 | .set_subsystem = gma_set_subsystem, |
| 500 | }; |
| 501 | |
| 502 | static struct device_operations gma_func0_ops = { |
| 503 | .read_resources = pci_dev_read_resources, |
| 504 | .set_resources = pci_dev_set_resources, |
| 505 | .enable_resources = pci_dev_enable_resources, |
| 506 | .init = gma_func0_init, |
| 507 | .scan_bus = 0, |
| 508 | .enable = 0, |
Patrick Georgi | ce6e9fe | 2012-07-20 12:37:06 +0200 | [diff] [blame] | 509 | .disable = gma_func0_disable, |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 510 | .ops_pci = &gma_pci_ops, |
| 511 | }; |
| 512 | |
| 513 | |
| 514 | static struct device_operations gma_func1_ops = { |
| 515 | .read_resources = pci_dev_read_resources, |
| 516 | .set_resources = pci_dev_set_resources, |
| 517 | .enable_resources = pci_dev_enable_resources, |
| 518 | .init = gma_func1_init, |
| 519 | .scan_bus = 0, |
| 520 | .enable = 0, |
| 521 | .ops_pci = &gma_pci_ops, |
| 522 | }; |
| 523 | |
Vladimir Serbinenko | 10dd0e3 | 2014-11-17 00:07:12 +0100 | [diff] [blame] | 524 | static const unsigned short pci_device_ids[] = { 0x27a2, 0x27ae, 0 }; |
| 525 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 526 | static const struct pci_driver i945_gma_func0_driver __pci_driver = { |
| 527 | .ops = &gma_func0_ops, |
| 528 | .vendor = PCI_VENDOR_ID_INTEL, |
Vladimir Serbinenko | 10dd0e3 | 2014-11-17 00:07:12 +0100 | [diff] [blame] | 529 | .devices = pci_device_ids, |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 530 | }; |
| 531 | |
| 532 | static const struct pci_driver i945_gma_func1_driver __pci_driver = { |
| 533 | .ops = &gma_func1_ops, |
| 534 | .vendor = PCI_VENDOR_ID_INTEL, |
| 535 | .device = 0x27a6, |
| 536 | }; |