Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 2 | |
| 3 | #include <stdint.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 4 | #include <console/console.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 5 | #include <device/mmio.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 6 | #include <device/pci_def.h> |
Tristan Corrick | 334be32 | 2018-12-17 22:10:21 +1300 | [diff] [blame] | 7 | #include <device/pci_ops.h> |
Elyes HAOUAS | c27014b | 2019-06-23 11:11:53 +0200 | [diff] [blame] | 8 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 9 | #include "haswell.h" |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 10 | |
Tristan Corrick | 334be32 | 2018-12-17 22:10:21 +1300 | [diff] [blame] | 11 | static bool peg_hidden[3]; |
| 12 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 13 | static void haswell_setup_bars(void) |
| 14 | { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 15 | printk(BIOS_DEBUG, "Setting up static northbridge registers..."); |
| 16 | /* Set up all hardcoded northbridge BARs */ |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 17 | pci_write_config32(HOST_BRIDGE, EPBAR, DEFAULT_EPBAR | 1); |
| 18 | pci_write_config32(HOST_BRIDGE, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32); |
| 19 | pci_write_config32(HOST_BRIDGE, MCHBAR, DEFAULT_MCHBAR | 1); |
| 20 | pci_write_config32(HOST_BRIDGE, MCHBAR + 4, (0LL + DEFAULT_MCHBAR) >> 32); |
| 21 | pci_write_config32(HOST_BRIDGE, DMIBAR, DEFAULT_DMIBAR | 1); |
| 22 | pci_write_config32(HOST_BRIDGE, DMIBAR + 4, (0LL + DEFAULT_DMIBAR) >> 32); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 23 | |
| 24 | /* Set C0000-FFFFF to access RAM on both reads and writes */ |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 25 | pci_write_config8(HOST_BRIDGE, PAM0, 0x30); |
| 26 | pci_write_config8(HOST_BRIDGE, PAM1, 0x33); |
| 27 | pci_write_config8(HOST_BRIDGE, PAM2, 0x33); |
| 28 | pci_write_config8(HOST_BRIDGE, PAM3, 0x33); |
| 29 | pci_write_config8(HOST_BRIDGE, PAM4, 0x33); |
| 30 | pci_write_config8(HOST_BRIDGE, PAM5, 0x33); |
| 31 | pci_write_config8(HOST_BRIDGE, PAM6, 0x33); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 32 | |
| 33 | printk(BIOS_DEBUG, " done.\n"); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 34 | } |
| 35 | |
Tristan Corrick | 334be32 | 2018-12-17 22:10:21 +1300 | [diff] [blame] | 36 | static void haswell_setup_igd(void) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 37 | { |
Tristan Corrick | c5d367b | 2018-12-17 22:10:07 +1300 | [diff] [blame] | 38 | bool igd_enabled; |
| 39 | u16 ggc; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 40 | u8 reg8; |
| 41 | |
Tristan Corrick | 334be32 | 2018-12-17 22:10:21 +1300 | [diff] [blame] | 42 | printk(BIOS_DEBUG, "Initializing IGD...\n"); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 43 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 44 | igd_enabled = !!(pci_read_config32(HOST_BRIDGE, DEVEN) & DEVEN_D2EN); |
Tristan Corrick | c5d367b | 2018-12-17 22:10:07 +1300 | [diff] [blame] | 45 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 46 | ggc = pci_read_config16(HOST_BRIDGE, GGC); |
Tristan Corrick | c5d367b | 2018-12-17 22:10:07 +1300 | [diff] [blame] | 47 | ggc &= ~0x3f8; |
| 48 | if (igd_enabled) { |
| 49 | ggc |= GGC_GTT_2MB | GGC_IGD_MEM_IN_32MB_UNITS(1); |
| 50 | ggc &= ~GGC_DISABLE_VGA_IO_DECODE; |
| 51 | } else { |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 52 | ggc |= GGC_GTT_0MB | GGC_IGD_MEM_IN_32MB_UNITS(0) | GGC_DISABLE_VGA_IO_DECODE; |
Tristan Corrick | c5d367b | 2018-12-17 22:10:07 +1300 | [diff] [blame] | 53 | } |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 54 | pci_write_config16(HOST_BRIDGE, GGC, ggc); |
Tristan Corrick | c5d367b | 2018-12-17 22:10:07 +1300 | [diff] [blame] | 55 | |
| 56 | if (!igd_enabled) { |
| 57 | printk(BIOS_DEBUG, "IGD is disabled.\n"); |
| 58 | return; |
| 59 | } |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 60 | |
| 61 | /* Enable 256MB aperture */ |
| 62 | reg8 = pci_read_config8(PCI_DEV(0, 2, 0), MSAC); |
| 63 | reg8 &= ~0x06; |
| 64 | reg8 |= 0x02; |
| 65 | pci_write_config8(PCI_DEV(0, 2, 0), MSAC, reg8); |
Tristan Corrick | c5d367b | 2018-12-17 22:10:07 +1300 | [diff] [blame] | 66 | } |
| 67 | |
Tristan Corrick | 334be32 | 2018-12-17 22:10:21 +1300 | [diff] [blame] | 68 | static void start_peg2_link_training(const pci_devfn_t dev) |
| 69 | { |
| 70 | u32 mask; |
| 71 | |
| 72 | switch (dev) { |
| 73 | case PCI_DEV(0, 1, 2): |
| 74 | mask = DEVEN_D1F2EN; |
| 75 | break; |
| 76 | case PCI_DEV(0, 1, 1): |
| 77 | mask = DEVEN_D1F1EN; |
| 78 | break; |
| 79 | case PCI_DEV(0, 1, 0): |
| 80 | mask = DEVEN_D1F0EN; |
| 81 | break; |
| 82 | default: |
| 83 | printk(BIOS_ERR, "Link training tried on a non-PEG device!\n"); |
| 84 | return; |
| 85 | } |
| 86 | |
| 87 | pci_update_config32(dev, 0xc24, ~(1 << 16), 1 << 5); |
Chris Morgan | 2806ec9 | 2020-02-05 10:51:46 -0600 | [diff] [blame] | 88 | printk(BIOS_DEBUG, "Started PEG1%d link training.\n", PCI_FUNC(PCI_DEV2DEVFN(dev))); |
Tristan Corrick | 334be32 | 2018-12-17 22:10:21 +1300 | [diff] [blame] | 89 | |
| 90 | /* |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 91 | * Hide the PEG device while the MRC runs. This is because the MRC makes |
| 92 | * configurations that are not ideal if it sees a VGA device in a PEG slot, |
| 93 | * and it locks registers preventing changes to these configurations. |
Tristan Corrick | 334be32 | 2018-12-17 22:10:21 +1300 | [diff] [blame] | 94 | */ |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 95 | pci_update_config32(HOST_BRIDGE, DEVEN, ~mask, 0); |
Chris Morgan | 2806ec9 | 2020-02-05 10:51:46 -0600 | [diff] [blame] | 96 | peg_hidden[PCI_FUNC(PCI_DEV2DEVFN(dev))] = true; |
| 97 | printk(BIOS_DEBUG, "Temporarily hiding PEG1%d.\n", PCI_FUNC(PCI_DEV2DEVFN(dev))); |
Tristan Corrick | 334be32 | 2018-12-17 22:10:21 +1300 | [diff] [blame] | 98 | } |
| 99 | |
| 100 | void haswell_unhide_peg(void) |
| 101 | { |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 102 | u32 deven = pci_read_config32(HOST_BRIDGE, DEVEN); |
Tristan Corrick | 334be32 | 2018-12-17 22:10:21 +1300 | [diff] [blame] | 103 | |
| 104 | for (u8 fn = 0; fn <= 2; fn++) { |
| 105 | if (peg_hidden[fn]) { |
| 106 | deven |= DEVEN_D1F0EN >> fn; |
| 107 | peg_hidden[fn] = false; |
| 108 | printk(BIOS_DEBUG, "Unhiding PEG1%d.\n", fn); |
| 109 | } |
| 110 | } |
| 111 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 112 | pci_write_config32(HOST_BRIDGE, DEVEN, deven); |
Tristan Corrick | 334be32 | 2018-12-17 22:10:21 +1300 | [diff] [blame] | 113 | } |
| 114 | |
| 115 | static void haswell_setup_peg(void) |
| 116 | { |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 117 | u32 deven = pci_read_config32(HOST_BRIDGE, DEVEN); |
Tristan Corrick | 334be32 | 2018-12-17 22:10:21 +1300 | [diff] [blame] | 118 | |
| 119 | if (deven & DEVEN_D1F2EN) |
| 120 | start_peg2_link_training(PCI_DEV(0, 1, 2)); |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 121 | |
Tristan Corrick | 334be32 | 2018-12-17 22:10:21 +1300 | [diff] [blame] | 122 | if (deven & DEVEN_D1F1EN) |
| 123 | start_peg2_link_training(PCI_DEV(0, 1, 1)); |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 124 | |
Tristan Corrick | 334be32 | 2018-12-17 22:10:21 +1300 | [diff] [blame] | 125 | if (deven & DEVEN_D1F0EN) |
| 126 | start_peg2_link_training(PCI_DEV(0, 1, 0)); |
| 127 | } |
| 128 | |
Tristan Corrick | c5d367b | 2018-12-17 22:10:07 +1300 | [diff] [blame] | 129 | static void haswell_setup_misc(void) |
| 130 | { |
| 131 | u32 reg32; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 132 | |
| 133 | /* Erratum workarounds */ |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 134 | reg32 = MCHBAR32(SAPMCTL); |
| 135 | reg32 |= (1 << 9) | (1 << 10); |
| 136 | MCHBAR32(SAPMCTL) = reg32; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 137 | |
| 138 | /* Enable SA Clock Gating */ |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 139 | reg32 = MCHBAR32(SAPMCTL); |
| 140 | MCHBAR32(SAPMCTL) = reg32 | 1; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 141 | |
| 142 | /* GPU RC6 workaround for sighting 366252 */ |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 143 | reg32 = MCHBAR32(SSKPD + 4); |
Ryan Salsamendi | b9bc257 | 2017-07-04 13:35:06 -0700 | [diff] [blame] | 144 | reg32 |= (1UL << 31); |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 145 | MCHBAR32(SSKPD + 4) = reg32; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 146 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 147 | /* VLW (Virtual Legacy Wire?) */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 148 | reg32 = MCHBAR32(0x6120); |
| 149 | reg32 &= ~(1 << 0); |
| 150 | MCHBAR32(0x6120) = reg32; |
| 151 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 152 | reg32 = MCHBAR32(INTRDIRCTL); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 153 | reg32 |= (1 << 4) | (1 << 5); |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 154 | MCHBAR32(INTRDIRCTL) = reg32; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 155 | } |
| 156 | |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 157 | static void haswell_setup_iommu(void) |
| 158 | { |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 159 | const u32 capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A); |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 160 | |
| 161 | if (capid0_a & VTD_DISABLE) |
| 162 | return; |
| 163 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 164 | /* Setup BARs: zeroize top 32 bits; set enable bit */ |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 165 | MCHBAR32(GFXVTBAR + 4) = GFXVT_BASE_ADDRESS >> 32; |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 166 | MCHBAR32(GFXVTBAR) = GFXVT_BASE_ADDRESS | 1; |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 167 | MCHBAR32(VTVC0BAR + 4) = VTVC0_BASE_ADDRESS >> 32; |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 168 | MCHBAR32(VTVC0BAR) = VTVC0_BASE_ADDRESS | 1; |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 169 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 170 | /* Set L3HIT2PEND_DIS, lock GFXVTBAR policy config registers */ |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 171 | u32 reg32; |
| 172 | reg32 = read32((void *)(GFXVT_BASE_ADDRESS + ARCHDIS)); |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 173 | write32((void *)(GFXVT_BASE_ADDRESS + ARCHDIS), reg32 | DMAR_LCKDN | L3HIT2PEND_DIS); |
| 174 | |
| 175 | /* Clear SPCAPCTRL */ |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 176 | reg32 = read32((void *)(VTVC0_BASE_ADDRESS + ARCHDIS)) & ~SPCAPCTRL; |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 177 | |
| 178 | /* Set GLBIOTLBINV, GLBCTXTINV; lock VTVC0BAR policy config registers */ |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 179 | write32((void *)(VTVC0_BASE_ADDRESS + ARCHDIS), |
| 180 | reg32 | DMAR_LCKDN | GLBIOTLBINV | GLBCTXTINV); |
| 181 | } |
| 182 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 183 | void haswell_early_initialization(int chipset_type) |
| 184 | { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 185 | /* Setup all BARs required for early PCIe and raminit */ |
| 186 | haswell_setup_bars(); |
| 187 | |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 188 | /* Setup IOMMU BARs */ |
| 189 | haswell_setup_iommu(); |
| 190 | |
Tristan Corrick | 334be32 | 2018-12-17 22:10:21 +1300 | [diff] [blame] | 191 | haswell_setup_peg(); |
| 192 | haswell_setup_igd(); |
Tristan Corrick | c5d367b | 2018-12-17 22:10:07 +1300 | [diff] [blame] | 193 | |
| 194 | haswell_setup_misc(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 195 | } |