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review.coreboot.org / coreboot / aa49608a2bf474355f0a7cf767e10326259254ed / . / src / soc / intel / alderlake / systemagent.c
blob: acdaded685dc240af6daa65a4d9d24868b14801a [file] [log] [blame]
Subrata Banik2871e0e2020-09-27 11:30:58 +0530[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
2
3/*
4 * This file is created based on Intel Alder Lake Processor SA Datasheet
5 * Document number: 619503
6 * Chapter number: 3
7 */
8
Sumeet Pawnikaraa496082021-05-07 20:11:53 +0530[diff] [blame^]9#include <console/console.h>
Subrata Banik2871e0e2020-09-27 11:30:58 +0530[diff] [blame]10#include <device/device.h>
11#include <device/pci.h>
Sumeet Pawnikaraa496082021-05-07 20:11:53 +0530[diff] [blame^]12#include <device/pci_ids.h>
Sumeet R Pawnikar77298c62021-03-10 21:09:37 +0530[diff] [blame]13#include <delay.h>
14#include <intelblocks/power_limit.h>
Subrata Banik2871e0e2020-09-27 11:30:58 +0530[diff] [blame]15#include <intelblocks/systemagent.h>
16#include <soc/iomap.h>
Sumeet R Pawnikar77298c62021-03-10 21:09:37 +0530[diff] [blame]17#include <soc/soc_chip.h>
Subrata Banik2871e0e2020-09-27 11:30:58 +0530[diff] [blame]18#include <soc/systemagent.h>
19
20/*
21 * SoC implementation
22 *
23 * Add all known fixed memory ranges for Host Controller/Memory
24 * controller.
25 */
26void soc_add_fixed_mmio_resources(struct device *dev, int *index)
27{
28 static const struct sa_mmio_descriptor soc_fixed_resources[] = {
Angel Pons98494882021-01-29 11:35:16 +0100[diff] [blame]29 { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH,
Subrata Banik2871e0e2020-09-27 11:30:58 +0530[diff] [blame]30 "PCIEXBAR" },
31 { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
32 { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" },
33 { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" },
34 { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" },
35 { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" },
36 };
37
38 sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources,
39 ARRAY_SIZE(soc_fixed_resources));
40
41 /* Add Vt-d resources if VT-d is enabled */
42 if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE))
43 return;
44
45 sa_add_fixed_mmio_resources(dev, index, soc_vtd_resources,
46 ARRAY_SIZE(soc_vtd_resources));
47}
48
49/*
50 * SoC implementation
51 *
52 * Perform System Agent Initialization during Ramstage phase.
53 */
54void soc_systemagent_init(struct device *dev)
55{
Sumeet R Pawnikar77298c62021-03-10 21:09:37 +0530[diff] [blame]56 struct soc_power_limits_config *soc_config;
Sumeet Pawnikaraa496082021-05-07 20:11:53 +0530[diff] [blame^]57 struct device *sa;
58 uint16_t sa_pci_id;
Sumeet R Pawnikar77298c62021-03-10 21:09:37 +0530[diff] [blame]59 config_t *config;
60
Subrata Banik2871e0e2020-09-27 11:30:58 +0530[diff] [blame]61 /* Enable Power Aware Interrupt Routing */
62 enable_power_aware_intr();
63
64 /* Enable BIOS Reset CPL */
65 enable_bios_reset_cpl();
Sumeet R Pawnikar77298c62021-03-10 21:09:37 +0530[diff] [blame]66
67 /* Configure turbo power limits 1ms after reset complete bit */
68 mdelay(1);
69 config = config_of_soc();
Sumeet Pawnikaraa496082021-05-07 20:11:53 +0530[diff] [blame^]70
71 /* Get System Agent PCI ID */
72 sa = pcidev_path_on_root(SA_DEVFN_ROOT);
73 sa_pci_id = sa ? pci_read_config16(sa, PCI_DEVICE_ID) : 0xFFFF;
74
75 /* Choose a power limits configuration based on the SoC SKU type,
76 * differentiated here based on SA PCI ID. */
77 switch (sa_pci_id) {
78 case PCI_DEVICE_ID_INTEL_ADL_P_ID_7:
79 soc_config = &config->power_limits_config[ADL_P_POWER_LIMITS_282_CORE];
80 break;
81 case PCI_DEVICE_ID_INTEL_ADL_P_ID_5:
82 soc_config = &config->power_limits_config[ADL_P_POWER_LIMITS_482_CORE];
83 break;
84 case PCI_DEVICE_ID_INTEL_ADL_P_ID_3:
85 soc_config = &config->power_limits_config[ADL_P_POWER_LIMITS_682_CORE];
86 break;
87 case PCI_DEVICE_ID_INTEL_ADL_M_ID_1:
88 soc_config = &config->power_limits_config[ADL_M_POWER_LIMITS_282_CORE];
89 break;
90 default:
91 printk(BIOS_ERR, "ADL: unknown SA ID: 0x%4x, skipping power limits configuration\n",
92 sa_pci_id);
93 return;
94 }
95
Sumeet R Pawnikar77298c62021-03-10 21:09:37 +0530[diff] [blame]96 set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config);
Subrata Banik2871e0e2020-09-27 11:30:58 +0530[diff] [blame]97}
98
99uint32_t soc_systemagent_max_chan_capacity_mib(u8 capid0_a_ddrsz)
100{
101 switch (capid0_a_ddrsz) {
102 case 1:
103 return 8192;
104 case 2:
105 return 4096;
106 case 3:
107 return 2048;
108 default:
109 return 65536;
110 }
111}