| Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | /* |
| 4 | * This file is created based on Intel Alder Lake Processor SA Datasheet |
| 5 | * Document number: 619503 |
| 6 | * Chapter number: 3 |
| 7 | */ |
| 8 | |
| 9 | #include <device/device.h> |
| 10 | #include <device/pci.h> |
| 11 | #include <intelblocks/systemagent.h> |
| 12 | #include <soc/iomap.h> |
| 13 | #include <soc/systemagent.h> |
| 14 | |
| 15 | /* |
| 16 | * SoC implementation |
| 17 | * |
| 18 | * Add all known fixed memory ranges for Host Controller/Memory |
| 19 | * controller. |
| 20 | */ |
| 21 | void soc_add_fixed_mmio_resources(struct device *dev, int *index) |
| 22 | { |
| 23 | static const struct sa_mmio_descriptor soc_fixed_resources[] = { |
| Angel Pons | 9849488 | 2021-01-29 11:35:16 +0100 | [diff] [blame^] | 24 | { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH, |
| Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 25 | "PCIEXBAR" }, |
| 26 | { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, |
| 27 | { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" }, |
| 28 | { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" }, |
| 29 | { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" }, |
| 30 | { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" }, |
| 31 | }; |
| 32 | |
| 33 | sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources, |
| 34 | ARRAY_SIZE(soc_fixed_resources)); |
| 35 | |
| 36 | /* Add Vt-d resources if VT-d is enabled */ |
| 37 | if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE)) |
| 38 | return; |
| 39 | |
| 40 | sa_add_fixed_mmio_resources(dev, index, soc_vtd_resources, |
| 41 | ARRAY_SIZE(soc_vtd_resources)); |
| 42 | } |
| 43 | |
| 44 | /* |
| 45 | * SoC implementation |
| 46 | * |
| 47 | * Perform System Agent Initialization during Ramstage phase. |
| 48 | */ |
| 49 | void soc_systemagent_init(struct device *dev) |
| 50 | { |
| 51 | /* Enable Power Aware Interrupt Routing */ |
| 52 | enable_power_aware_intr(); |
| 53 | |
| 54 | /* Enable BIOS Reset CPL */ |
| 55 | enable_bios_reset_cpl(); |
| 56 | /* TODO: Add set_power_limits() */ |
| 57 | } |
| 58 | |
| 59 | uint32_t soc_systemagent_max_chan_capacity_mib(u8 capid0_a_ddrsz) |
| 60 | { |
| 61 | switch (capid0_a_ddrsz) { |
| 62 | case 1: |
| 63 | return 8192; |
| 64 | case 2: |
| 65 | return 4096; |
| 66 | case 3: |
| 67 | return 2048; |
| 68 | default: |
| 69 | return 65536; |
| 70 | } |
| 71 | } |