Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | /* |
| 4 | * This file is created based on Intel Alder Lake Processor SA Datasheet |
| 5 | * Document number: 619503 |
| 6 | * Chapter number: 3 |
| 7 | */ |
| 8 | |
| 9 | #include <device/device.h> |
| 10 | #include <device/pci.h> |
Sumeet R Pawnikar | 77298c6 | 2021-03-10 21:09:37 +0530 | [diff] [blame] | 11 | #include <delay.h> |
| 12 | #include <intelblocks/power_limit.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 13 | #include <intelblocks/systemagent.h> |
| 14 | #include <soc/iomap.h> |
Sumeet R Pawnikar | 77298c6 | 2021-03-10 21:09:37 +0530 | [diff] [blame] | 15 | #include <soc/soc_chip.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 16 | #include <soc/systemagent.h> |
| 17 | |
| 18 | /* |
| 19 | * SoC implementation |
| 20 | * |
| 21 | * Add all known fixed memory ranges for Host Controller/Memory |
| 22 | * controller. |
| 23 | */ |
| 24 | void soc_add_fixed_mmio_resources(struct device *dev, int *index) |
| 25 | { |
| 26 | static const struct sa_mmio_descriptor soc_fixed_resources[] = { |
Angel Pons | 9849488 | 2021-01-29 11:35:16 +0100 | [diff] [blame] | 27 | { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH, |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 28 | "PCIEXBAR" }, |
| 29 | { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, |
| 30 | { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" }, |
| 31 | { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" }, |
| 32 | { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" }, |
| 33 | { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" }, |
| 34 | }; |
| 35 | |
| 36 | sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources, |
| 37 | ARRAY_SIZE(soc_fixed_resources)); |
| 38 | |
| 39 | /* Add Vt-d resources if VT-d is enabled */ |
| 40 | if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE)) |
| 41 | return; |
| 42 | |
| 43 | sa_add_fixed_mmio_resources(dev, index, soc_vtd_resources, |
| 44 | ARRAY_SIZE(soc_vtd_resources)); |
| 45 | } |
| 46 | |
| 47 | /* |
| 48 | * SoC implementation |
| 49 | * |
| 50 | * Perform System Agent Initialization during Ramstage phase. |
| 51 | */ |
| 52 | void soc_systemagent_init(struct device *dev) |
| 53 | { |
Sumeet R Pawnikar | 77298c6 | 2021-03-10 21:09:37 +0530 | [diff] [blame] | 54 | struct soc_power_limits_config *soc_config; |
| 55 | config_t *config; |
| 56 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 57 | /* Enable Power Aware Interrupt Routing */ |
| 58 | enable_power_aware_intr(); |
| 59 | |
| 60 | /* Enable BIOS Reset CPL */ |
| 61 | enable_bios_reset_cpl(); |
Sumeet R Pawnikar | 77298c6 | 2021-03-10 21:09:37 +0530 | [diff] [blame] | 62 | |
| 63 | /* Configure turbo power limits 1ms after reset complete bit */ |
| 64 | mdelay(1); |
| 65 | config = config_of_soc(); |
| 66 | soc_config = &config->power_limits_config; |
| 67 | set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 68 | } |
| 69 | |
| 70 | uint32_t soc_systemagent_max_chan_capacity_mib(u8 capid0_a_ddrsz) |
| 71 | { |
| 72 | switch (capid0_a_ddrsz) { |
| 73 | case 1: |
| 74 | return 8192; |
| 75 | case 2: |
| 76 | return 4096; |
| 77 | case 3: |
| 78 | return 2048; |
| 79 | default: |
| 80 | return 65536; |
| 81 | } |
| 82 | } |