Michał Żygowski | 72f06ca | 2020-04-13 21:42:24 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <bootblock_common.h> |
| 4 | #include <device/pci_ops.h> |
| 5 | #include <northbridge/intel/sandybridge/sandybridge.h> |
| 6 | #include <southbridge/intel/bd82x6x/pch.h> |
| 7 | #include <superio/smsc/sch5545/sch5545.h> |
| 8 | #include <superio/smsc/sch5545/sch5545_emi.h> |
| 9 | |
Michał Żygowski | 7e8b597 | 2022-02-20 23:27:18 +0100 | [diff] [blame] | 10 | #include <baseboard/sch5545_ec.h> |
Michał Żygowski | 72f06ca | 2020-04-13 21:42:24 +0200 | [diff] [blame] | 11 | |
Michał Żygowski | 72f06ca | 2020-04-13 21:42:24 +0200 | [diff] [blame] | 12 | void bootblock_mainboard_early_init(void) |
| 13 | { |
| 14 | /* |
| 15 | * FIXME: the board gets stuck in reset loop in |
| 16 | * mainboard_romstage_entry. Avoid that by clearing SSKPD |
| 17 | */ |
Angel Pons | d9e58dc | 2021-01-20 01:22:20 +0100 | [diff] [blame] | 18 | pci_write_config32(HOST_BRIDGE, MCHBAR, CONFIG_FIXED_MCHBAR_MMIO_BASE | 1); |
| 19 | pci_write_config32(HOST_BRIDGE, MCHBAR + 4, 0); |
Angel Pons | 528b471 | 2021-03-27 19:15:59 +0100 | [diff] [blame] | 20 | mchbar_write16(SSKPD_HI, 0); |
Michał Żygowski | 72f06ca | 2020-04-13 21:42:24 +0200 | [diff] [blame] | 21 | |
| 22 | sch5545_early_init(0x2e); |
| 23 | /* Bare EC and SIO GPIO initialization which allows to enable serial port */ |
| 24 | sch5545_emi_init(0x2e); |
| 25 | sch5545_emi_disable_interrupts(); |
| 26 | sch5545_ec_early_init(); |
| 27 | |
| 28 | if (CONFIG(CONSOLE_SERIAL)) |
| 29 | sch5545_enable_uart(0x2e, 0); |
| 30 | } |