blob: 5469c94f158311ea1f9d9d439431639eed436e56 [file] [log] [blame]
Michał Żygowski72f06ca2020-04-13 21:42:24 +02001/* SPDX-License-Identifier: GPL-2.0-only */
2
3#include <bootblock_common.h>
4#include <device/pci_ops.h>
5#include <northbridge/intel/sandybridge/sandybridge.h>
6#include <southbridge/intel/bd82x6x/pch.h>
7#include <superio/smsc/sch5545/sch5545.h>
8#include <superio/smsc/sch5545/sch5545_emi.h>
9
10#include "sch5545_ec.h"
11
12const struct southbridge_usb_port mainboard_usb_ports[] = {
13 { 1, 6, 0 },
14 { 1, 6, 0 },
15 { 1, 1, 1 },
16 { 1, 1, 1 },
17 { 1, 1, 2 },
18 { 1, 1, 2 },
19 { 1, 6, 3 },
20 { 1, 6, 3 },
21 { 1, 6, 4 },
22 { 1, 6, 4 },
23 { 1, 6, 5 },
24 { 1, 1, 5 },
25 { 1, 1, 6 },
26 { 1, 6, 6 },
27};
28
29void bootblock_mainboard_early_init(void)
30{
31 /*
32 * FIXME: the board gets stuck in reset loop in
33 * mainboard_romstage_entry. Avoid that by clearing SSKPD
34 */
35 pci_write_config32(HOST_BRIDGE, MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1);
36 pci_write_config32(HOST_BRIDGE, MCHBAR + 4, (0LL + (uintptr_t)DEFAULT_MCHBAR) >> 32);
37 MCHBAR16(SSKPD_HI) = 0;
38
39 sch5545_early_init(0x2e);
40 /* Bare EC and SIO GPIO initialization which allows to enable serial port */
41 sch5545_emi_init(0x2e);
42 sch5545_emi_disable_interrupts();
43 sch5545_ec_early_init();
44
45 if (CONFIG(CONSOLE_SERIAL))
46 sch5545_enable_uart(0x2e, 0);
47}